JPH06338619A - Non-volatile semiconductor memory and manufacture thereof - Google Patents

Abstract

PURPOSE:To suppress the generation of off-current in the gate voltage-drain current characteristic by a method wherein the high potential between a drain region and a gate electrode when data are read in the write state of a memory transistor is lowered by the MOS transistors in both side regions of a memory transistor. CONSTITUTION:A memory gate insulating film 19 comprising oxide film 13, a silicon nitride film 15 and a top oxide film 17 provided on a semiconductor substrate 11 is arranged. Next, MOS gate insulating films 21 are provided on both sides of the memory gate insulating film 19 further to provide a gate electrode 25 on the memory gate insulating film 19 and the MOS insulating films 21. Next, a source region 35 and a drain region 37 in inverse conductivity type to that of the semiconductor substrate 11 provided in the matching region with the gate electrode 25 are formed. Through these procedures, any defective date during the data writing-in time of a memory transistor shall not be obtained thereby enabling the title high reliable semiconductor non-volatile memory to be manufactured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor nonvolatile memory device and a method of manufacturing the same, and more particularly to a gate electrode-a top oxide film made of a silicon oxide film-a silicon nitride film-
The present invention relates to a structure of a semiconductor nonvolatile memory device having a so-called MONOS structure having a tunnel oxide film-semiconductor substrate structure made of a silicon oxide film and a manufacturing method thereof.

[0002]

2. Description of the Related Art In a memory transistor having a MONOS structure, a threshold voltage when electric charges are accumulated at an interface between a silicon nitride film and a top oxide film and a threshold voltage when electric charges are not accumulated. Information is stored using the difference between and.

In this MONOS structure memory transistor, a channel is formed in the channel region under the gate electrode because the threshold voltage is negative when no charge is stored.

At this time, a MOS (metal-oxide-semiconductor) transistor is required to allow the drain current to flow only when the memory transistor is selected so that the drain current flowing from the source region to the drain region does not flow. And

As a semiconductor non-volatile memory device having this memory transistor and a MOS transistor, for example, there is one described in Japanese Patent Laid-Open No. 4-337672.
The structure of the memory transistor and the MOS transistor described in this publication will be described with reference to the sectional view of FIG.

As shown in FIG. 17, a memory gate insulating film 19 including a top oxide film 17, a silicon nitride film 15, and a tunnel oxide film 13, and an MO including a silicon oxide film.
The S gate insulating film 21 is provided on the semiconductor substrate 11 so that the end faces thereof are in contact with each other.

The memory gate insulating film 19 and the MO
A gate electrode 25 is provided on the S gate insulating film 21.

Further, the source region 35 and the drain region 37 are formed on the semiconductor substrate 11 in the region where the gate electrode 25 is aligned.
And. That is, the memory transistor 31 and the MOS
The transistor 33 and the transistor 33 are provided adjacent to each other.

[0009]

In the semiconductor nonvolatile memory device described in the above-mentioned publication described with reference to FIG. 17, the memory transistor 31 and the MOS transistor 3 are included.
3 is provided so as to be in contact with. Therefore, there is an advantage that the semiconductor nonvolatile memory device can be downsized.

However, in the semiconductor nonvolatile memory device shown in FIG. 17, the memory transistor 31 is in contact with the drain region 37.

In the structure as shown in FIG. 17, when the memory transistor 31 reads out information in the written state, the relationship between the gate voltage and the drain current is shown in FIG.
As indicated by the curve 39 in the graph of FIG.

In the off current as shown in the graph of FIG. 18, trapped electrons increase the potential between the drain region 37 and the gate electrode 25, which causes a tunnel current between band bands. As shown in the graph of FIG. 18, which shows gate voltage-drain current characteristics, off-state current flows.

Therefore, there arises a problem that the reliability of the semiconductor nonvolatile memory device is lowered.

An object of the present invention is to solve the above problems and provide a structure of a semiconductor nonvolatile memory device having high reliability and a manufacturing method for obtaining this structure.

[0015]

In order to achieve the above object, the structure of the semiconductor nonvolatile memory device of the present invention and the manufacturing method thereof adopt the following means.

A semiconductor non-volatile memory device of the present invention comprises a memory gate insulating film formed on a semiconductor substrate, comprising a tunnel oxide film, a silicon nitride film and a top oxide film, and a MOS gate insulating film provided on both sides of the memory gate insulating film. A gate electrode provided on the memory gate insulating film and the MOS gate insulating film, a source region / drain region having a conductivity type opposite to that of the semiconductor substrate provided in a region where the gate electrodes are aligned, an interlayer insulating film having a contact hole, and a contact And a wiring connected to the source region and the drain region through the hole.

The semiconductor nonvolatile memory device of the present invention includes a MOS gate insulating film provided on a semiconductor substrate, a tunnel oxide film provided on the semiconductor substrate, and a silicon nitride film provided so as to partially overlap the MOS gate insulating film. An oxide film,
A gate electrode provided on a memory gate insulating film composed of a tunnel oxide film, a silicon nitride film, and a top oxide film, and a MOS gate insulating film, and a source region drain of a conductivity type opposite to that of a semiconductor substrate provided in a region where the gate electrode is aligned A region, an interlayer insulating film having a contact hole, and a wiring connected to the source region and the drain region through the contact hole are provided.

A method of manufacturing a semiconductor nonvolatile memory device according to the present invention comprises a step of sequentially forming a tunnel oxide film and a silicon nitride film on a semiconductor substrate and forming a photosensitive resin on the silicon nitride film, and a step of forming a photosensitive resin. Patterning the silicon nitride film and the tunnel oxide film using an etching mask; forming an MOS gate insulating film on the semiconductor substrate and a top oxide film on the silicon nitride film by performing an oxidation process; A step of forming an electrode material on the entire surface and forming a photosensitive resin on the gate electrode material, and forming a gate electrode by patterning the gate electrode material using the photosensitive resin as an etching mask, and an area aligned with the gate electrode The step of forming the source region and the drain region by introducing impurities into the semiconductor substrate, and forming an interlayer insulating film on the entire surface and contacting the interlayer insulating film. To form a hole, characterized in that a step of forming a wiring.

According to the method of manufacturing a semiconductor nonvolatile memory device of the present invention, a MOS gate insulating film is formed on a semiconductor substrate, and M
A step of forming a photosensitive resin on the OS gate insulating film and patterning the MOS gate insulating film using the photosensitive resin as an etching mask;
A step of forming a tunnel oxide film on the semiconductor substrate in the opening of the gate insulating film, forming a silicon nitride film and a top oxide film on the entire surface, forming a photosensitive resin on the top oxide film, and etching the photosensitive resin. Patterning the top oxide film and the silicon nitride film using a mask, forming a gate electrode material on the entire surface and forming a photosensitive resin on the gate electrode material, and using the photosensitive resin as an etching mask Patterning a gate electrode material to form a gate electrode, introducing impurities into a semiconductor substrate in a region aligned with the gate electrode to form a source region and a drain region, and forming an interlayer insulating film over the entire surface A step of forming a contact hole and forming a wiring.

[0020]

In the semiconductor nonvolatile memory device of the present invention,
A MOS transistor is also formed on the drain region side. That is, MOS transistors are formed in the regions on both sides of the memory transistor so as to contact the memory transistor.

Therefore, the high potential between the drain region and the gate electrode, which occurs when the information is read when the memory transistor is in the written state, can be lowered by the MOS transistor provided in contact with the drain region. .

Therefore, it is possible to suppress the generation of the off current in the gate voltage-drain current characteristic as shown in the graph of FIG.

As a result, a data defect at the time of writing information in the memory transistor does not occur, and a highly reliable semiconductor nonvolatile memory device can be obtained.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 16 showing the structure and the manufacturing method of the semiconductor nonvolatile memory device of the present invention, the element isolation insulating film for insulating isolation between elements is not shown.

First, the structure of the semiconductor nonvolatile memory device of the present invention will be described with reference to the sectional view of FIG.

As shown in FIG. 5, the semiconductor nonvolatile memory device of the present invention comprises a semiconductor substrate 11 made of single crystal silicon.
It has a memory gate insulating film 19 formed of a tunnel oxide film 13, a silicon nitride film 15, and a top oxide film 17 provided thereabove. Here, the tunnel oxide film 13 and the top oxide film 1
7 is made of a silicon oxide film.

Further, a MOS gate insulating film 21 made of a silicon oxide film is provided on the semiconductor substrate 11 on both sides of the memory gate insulating film 19. Here, the end face of the MOS gate insulating film 21 and the end faces of the tunnel oxide film 13, the silicon nitride film 15, and the top oxide film 17, which are the memory gate insulating film 19, are configured to be in contact with each other.

The memory gate insulating film 19 and the MO
A gate electrode 25 is provided on the S gate insulating film 21.

Further, in a region aligned with the gate electrode 25,
A source region 35 and a drain region 37 of opposite conductivity type to the semiconductor substrate 11 are provided.

Further, an interlayer insulating film 41 is provided, and a wiring 43 connecting the source region 35 and the drain region 37 via a contact hole formed in the interlayer insulating film 41 is provided.

That is, the semiconductor nonvolatile memory device of the present invention has a structure having the MOS transistors 33 on both sides of the memory transistor 31.

As described above, in the semiconductor nonvolatile memory device of the present invention, as shown in FIG. 5, the MOS transistor 33 is formed on the drain region 37 side as well as the source region 35 side.

Therefore, the high potential between the drain region 37 and the gate electrode 25, which is generated when the information is read while the memory transistor 31 is in the written state, can be lowered by the MOS transistor 33 provided on the drain region 37 side. it can.

Therefore, it is possible to suppress the generation of the off current in the gate voltage-drain current characteristic as shown in FIG.

As a result, it is possible to obtain a highly reliable semiconductor non-volatile memory device without causing a data defect when writing information in the memory transistor.

Next, a manufacturing method for forming the semiconductor nonvolatile memory device shown in FIG. 5 will be described with reference to the sectional views of FIGS.

First, as shown in FIG. 1, the tunnel oxide film 1 made of a silicon oxide film is subjected to an oxidation treatment on a semiconductor substrate 11 having a P type conductivity type on which an element isolation insulating film (not shown) is formed.
3 is formed with a film thickness of 2 nm.

This tunnel oxide film 13 is formed in a mixed gas atmosphere of oxygen and nitrogen at a temperature of 900.degree. C. for 3 hours.
It is formed by performing an oxidation treatment for 0 minutes.

Then, dichlorosilane (SiH ₂ Cl
₂ ) and ammonia (NH ₃ ) are used as reaction gases to form a silicon nitride film 15 having a film thickness of 11 nm by a chemical vapor deposition method.

After that, a photosensitive resin 27 is formed on the entire surface by a spin coating method, exposed and developed using a predetermined photomask, and patterned so that the photosensitive resin 27 is formed in the memory transistor formation region. To do.

Then, using the photosensitive resin 27 as an etching mask, the silicon nitride film 15 and the tunnel oxide film 13 are formed.
And pattern.

The etching of the silicon nitride film 15 is performed by
Using a reactive ion etching apparatus, a mixed gas of sulfur hexafluoride (SF ₆ ), helium (He), and trifluoromethane (CHF ₃ ) is used as an etching gas.

Further, the etching of the tunnel oxide film 13 is performed by wet etching using a hydrofluoric acid-based etching solution.

Then, the photosensitive resin 27 used as an etching mask for patterning the silicon nitride film 15 and the tunnel oxide film 13 is removed.

Then, as shown in FIG. 2, an oxidation treatment is performed to form a top oxide film 17 of a silicon oxide film on the silicon nitride film 15 in a thickness of 5 nm. By forming the top oxide film 17 on the silicon nitride film 15, the film thickness of the silicon nitride film 15 is reduced, and the initial film thickness is 11 nm.
To 8 nm.

Simultaneously with the oxidation treatment for forming the top oxide film 17, the MOS gate insulating film 21 made of a silicon oxide film can be formed on the semiconductor substrate 11 with a film thickness of 30 nm.

The top oxide film 17 and the MOS gate insulating film 21 are formed at a temperature of 900 in a steam oxidizing atmosphere.
It is carried out under conditions of 60 ° C. and 60 minutes.

As a result, the memory gate insulating film 19 including the tunnel oxide film 13, the silicon nitride film 15 and the top oxide film 17 is formed in the memory transistor forming region, and the MOS gate insulating film 21 is further formed in the MOS transistor forming region. Can be formed.

Here, with the end face of the MOS gate insulating film 21,
The end surface of the memory gate insulating film 19 including the tunnel oxide film 13, the silicon nitride film 15, and the top oxide film 17 is in contact with each other.

Next, as shown in FIG. 3, a gate electrode material 23 made of a polycrystalline silicon film having a film thickness of 400 nm is formed on the entire surface by a chemical vapor deposition method using monosilane (SiH ₄ ) as a reaction gas.

After that, a photosensitive resin 27 is formed on the entire surface by a spin coating method, and an exposure process and a development process are performed by using a predetermined photomask, and the photosensitive resin 27 is formed in a region where a memory transistor and a MOS transistor are formed. Pattern to form.

Next, as shown in FIG. 4, the photosensitive resin 27
Is used as an etching mask to pattern the gate electrode material 23 to form a gate electrode 25.

The etching of the gate electrode 25 is performed using a reactive ion etching apparatus using a mixed gas of sulfur hexafluoride (SF ₆ ) and oxygen (O ₂ ) as an etching gas. At this time, the MOS gate insulating film 21 is
It may be patterned or may be left unpatterned.

Next, the photosensitive resin 27 used as an etching mask for patterning the gate electrode 25 is removed.

After that, arsenic, which is an impurity having a conductivity type opposite to that of the semiconductor substrate 11, is introduced into the semiconductor substrate 11 in the region where the gate electrode 25 is aligned to form a source region 35 and a drain region 37.

The ion implantation dose of arsenic for forming the source region 35 and the drain region 37 is 3 × 10 ¹⁵ c.
Perform under the condition of m ^-2 .

Next, as shown in FIG.
An interlayer insulating film 41 made of a silicon oxide film containing m and phosphorus is formed on the entire surface by a chemical vapor deposition method.

After that, a photosensitive resin (not shown) is formed on the interlayer insulating film 41 by a spin coating method, and an exposure process and a development process are performed using a predetermined photomask to form an opening corresponding to the contact hole. Patterning the photosensitive resin having.

After that, the interlayer insulating film 41 is etched using the patterned photosensitive resin as an etching mask to form a contact hole.

The contact hole is etched by using a reactive ion etching apparatus using methane trifluoride (C
A mixed gas of HF ₃ ) and methane difluoride (CH ₂ F ₂ ) is used as an etching gas.

After that, a wiring material made of aluminum containing silicon and copper was formed by using a sputtering device.
It is formed with a film thickness of about 800 nm.

Thereafter, a photosensitive resin (not shown) is formed on the wiring material by a spin coating method, and an exposure process and a development process are performed using a predetermined photomask to pattern the photosensitive resin into the shape of the wiring 43. To do.

After that, the wiring material is patterned by using the patterned photosensitive resin as an etching mask to form the wiring 43.

The etching of the wiring 43 is performed by using a reactive ion etching device and using a mixed gas of boron trichloride (BCl ₃ ) and chlorine (Cl ₂ ) as an etching gas.

As a result, a semiconductor nonvolatile memory device having the MOS transistors 33 on both sides of the memory transistor 31 can be formed.

Next, the structure of a semiconductor nonvolatile memory device according to another embodiment will be described with reference to the sectional view of FIG.

As shown in FIG. 10, in the semiconductor nonvolatile memory device of the present invention, a MOS gate insulating film 21 made of a silicon oxide film is provided on the semiconductor substrate 11.

Further, a tunnel oxide film 13 made of a silicon oxide film is provided in the opening of the MOS gate insulating film 21.

Further, on the tunnel oxide film 13,
A silicon nitride film 15 and a top oxide film 17 are provided on the MOS gate insulating film 21 so as to partially overlap each other. Here, the end face of the MOS gate insulating film 21 is in contact with the end face of the silicon nitride film 15.

As shown in FIG. 10, MOS gate insulating films 21 are provided on both sides of the memory gate insulating film 19 including the tunnel oxide film 13, the silicon nitride film 15 and the top oxide film 17.

The memory gate insulating film 19 and the MO
The gate electrode 25 is provided on the S gate insulating film 21, and the semiconductor substrate 11 is formed in a region aligned with the gate electrode 25.
A source region 35 and a drain region 37 of opposite conductivity type are provided.

Further, an interlayer insulating film 41 is provided, and a wiring 43 connecting the source region 35 and the drain region 37 via a contact hole formed in the interlayer insulating film 41 is provided.

In the semiconductor nonvolatile memory device according to the embodiment of the present invention described with reference to FIG. 10, the structure having the MOS transistors 33 on both sides of the memory transistor 31 is the same as that of the embodiment described with reference to FIG. 520. Is. However, the positional relationship between the memory gate insulating film 19 and the MOS gate insulating film 21 is different.

That is, as shown in FIG. 10, the silicon nitride film 15 and the top oxide film 17 are provided on the MOS gate insulating film 21 so as to partially overlap each other. And MO
The end face of the S gate insulating film 21 and the end faces of the silicon nitride film 15 and the tunnel oxide film 13 are configured to be in contact with each other.

In the semiconductor nonvolatile memory device according to the embodiment of the present invention shown in FIG. 10, the MOS transistor 33 is formed on the drain region 37 side as well as the source region 35. Therefore, the high potential between the drain region 37 and the gate electrode 25, which occurs when the information is read while the memory transistor 31 is in the written state, can be lowered by the MOS transistor 33 provided so as to be in contact with the drain region 37. it can.

Therefore, it is possible to suppress the generation of the off current in the gate voltage-drain current characteristic as shown in FIG. As a result, no data failure occurs when writing information in the memory transistor, and a highly reliable semiconductor nonvolatile memory device can be obtained.

Next, a manufacturing method for forming the semiconductor nonvolatile memory device shown in FIG. 10 will be described with reference to the sectional views of FIGS.

First, as shown in FIG. 6, a MOS gate insulating film made of a silicon oxide film with a film thickness of about 30 nm is formed by oxidizing the semiconductor substrate 11 having a P type conductivity type on which an element isolation insulating film (not shown) is formed. 21 is formed.

The formation of the MOS gate insulating film 21 is performed in a mixed gas atmosphere of oxygen and nitrogen under the oxidizing conditions of temperature 1000 ° C. and time 60 minutes.

Then, the photosensitive resin 27 is applied by spin coating.
Are formed on the entire surface, and an exposure process and a development process are performed using a predetermined photomask to pattern the photosensitive resin 27 having an opening corresponding to the memory transistor formation region.

Thereafter, using the patterned photosensitive resin 27 as an etching mask, the MOS gate insulating film 21 is patterned.

The MOS gate insulating film 21 is etched by using a reactive ion etching apparatus and a mixed gas of methane trifluoride (CHF ₃ ) and carbon tetrafluoride (CF ₄ ) as an etching gas. To do.

After that, the photosensitive resin 2 used as an etching mask for patterning the MOS gate insulating film 21.
Remove 7.

Next, as shown in FIG. 7, the semiconductor substrate 11
Is oxidized to form a tunnel oxide film 13 of a silicon oxide film with a thickness of 2 nm on the semiconductor substrate 11 in the opening of the MOS gate insulating film 21.

This tunnel oxide film 13 is formed at a temperature of 900 ° C. for 3 hours in a mixed gas atmosphere of oxygen and nitrogen.
It is formed by performing an oxidation treatment for 0 minutes.

In the oxidation treatment step for forming the tunnel oxide film 13, the oxidant diffuses in the MOS gate insulating film 21 and reaches the semiconductor substrate 11, so that the semiconductor substrate 11 is also oxidized. Insulating film 21
The increase in the film thickness is very small, 0.5 nm or less.

Then, dichlorosilane (SiH ₂ Cl
₂ ) and ammonia (NH ₃ ) are used as reaction gases to form a silicon nitride film 15 having a film thickness of 11 nm on the entire surface by chemical vapor deposition.

After that, an oxidation process is performed to form a top oxide film 17 made of a silicon oxide film with a thickness of 5 nm on the silicon nitride film 15. By forming the top oxide film 17 on the silicon nitride film 15, the silicon nitride film 15 is formed.
The film thickness of is reduced to 8 nm from the initial film thickness of 11 nm. This top oxide film 17 is formed in a steam oxidizing atmosphere.
It is formed under the oxidizing conditions of a temperature of 900 ° C. and a time of 60 minutes.

After that, a photosensitive resin 27 is formed on the entire surface by a spin coating method, and an exposure process and a development process are performed using a predetermined photomask to form the photosensitive resin 27 in a region including a memory transistor formation region. So that the patterning is performed.

At this time, the photosensitive resin 27 for patterning the top oxide film 17 and the silicon nitride film 15 is formed.
Is patterned so as to overlap the MOS gate insulating film 21.

The amount of overlap of the photosensitive resin 27 formed on the MOS gate insulating film 21 depends on the amount of misalignment of the photomask in the alignment process and the amount of etching variation between the top oxide film 17 and the silicon nitride film 15 in the patterning process. In consideration of the above, the overlap dimension may be set.

Next, as shown in FIG.
Is used as an etching mask to pattern the top oxide film 17 and the silicon nitride film 15.

Top oxide film 17 made of silicon oxide film
The etching is performed by wet etching using a hydrofluoric acid-based etching solution.

The etching of the silicon nitride film 15 is performed by using a reactive ion etching apparatus, using sulfur hexafluoride (SF ₆ ) and helium (H) as etching gas.
e) and mixed gas of trifluoromethane (CHF ₃ ) are used.

As a result, a memory gate insulating film 19 consisting of the tunnel oxide film 13, the silicon nitride film 15 and the top oxide film 17 is formed in the memory transistor formation region,
Further, the MO of the regions on both sides of the memory gate insulating film 19 is
The MOS gate insulating film 21 can be formed in the formation region of the S transistor.

After that, monosilane (Si
The film thickness is 400 by the chemical vapor deposition method using H ₄ ).
A gate electrode material 23 made of a polycrystalline silicon film having a thickness of nm is formed on the entire surface.

After that, a photosensitive resin 27 is formed on the entire surface by a spin coating method, an exposure process and a development process are performed using a predetermined photomask, and the photosensitive resin 27 is formed in a region where a memory transistor and a MOS transistor are formed. The photosensitive resin 27 is patterned so as to be formed, that is, in the shape of the gate electrode.

Next, as shown in FIG. 9, the photosensitive resin 27
Is used as an etching mask to pattern the gate electrode material 23 to form a gate electrode 25.

Thereafter, using the photosensitive resin 27 as an etching mask, the MOS gate insulating film 21 in the region not covered with the gate electrode 25 is patterned so as to be aligned with the gate electrode 25. At this time, the MOS gate insulating film 21 may be left without patterning.

After that, arsenic, which is an impurity having a conductivity type opposite to that of the semiconductor substrate 11, is introduced into the semiconductor substrate 11 in the region where the gate electrode 25 is aligned to form a source region 35 and a drain region 37.

Next, as shown in FIG. 10, an interlayer insulating film 41 made of a silicon oxide film containing phosphorus and boron is formed on the entire surface by chemical vapor deposition.

Thereafter, a photosensitive resin (not shown) is formed on the interlayer insulating film 41 by a spin coating method, and an exposure process and a development process are performed using a predetermined photomask to form an opening corresponding to a contact hole. The photosensitive resin is patterned.

Thereafter, the patterned insulating resin is used as an etching mask to etch the interlayer insulating film 41 to form a contact hole.

After that, a wiring material made of aluminum containing silicon and copper was formed by using a sputtering device.
It is formed on the entire surface with a film thickness of about 800 nm.

Thereafter, a photosensitive resin (not shown) is formed on the wiring material by a spin coating method, and an exposure process and a development process are performed using a predetermined photomask to form a photosensitive film having a pattern corresponding to the wiring 43. Patterning the resin.

After that, the wiring material is etched using the patterned photosensitive resin as an etching mask to form the wiring 43.

As a result, a semiconductor nonvolatile memory device having the MOS transistor 33 on both sides of the memory transistor 31 can be formed.

Next, a method of manufacturing a semiconductor nonvolatile memory device according to another embodiment of the present invention will be described with reference to the sectional views of FIGS.

As shown in FIG. 11, the MOS gate insulating film 21 having a thickness of about 30 nm is formed on the semiconductor substrate 11 by performing the same processing steps as those of the embodiment described with reference to FIGS. 6 and 7. To do. That is, the MOS gate insulating film 2 is formed on the entire surface.
1 is formed and M is formed by using a photosensitive resin as an etching mask.
The OS gate insulating film 21 is patterned so as to form an opening corresponding to the memory transistor formation region.

Then, an oxidation process is performed to form the tunnel oxide film 1.
3 with a film thickness of 2 nm is formed on the semiconductor substrate 11 in the opening of the MOS gate insulating film 21.

After that, the film thickness is reduced to 1 by a chemical vapor deposition method using dichlorosilane and ammonia as reaction gases.
A 1 nm silicon nitride film 15 is formed on the entire surface.

After that, a photosensitive resin 27 is formed on the entire surface of the silicon nitride film 13 by a spin coating method, and an exposure process and a development process are performed using a predetermined photomask to form a region including a memory transistor formation region. Photosensitive resin 27
The photosensitive resin 27 is patterned so as to form

At this time, the photosensitive resin 27 used as an etching mask for patterning the silicon nitride film 15 is patterned so as to overlap the MOS gate insulating film 21. MOS of this photosensitive resin 27
The amount of overlap with the gate insulating film 21 is set in consideration of the amount of photomask misalignment in the alignment process and the amount of etching variation of the silicon nitride film 15 in the patterning process.

Next, as shown in FIG. 12, the photosensitive resin 2
Using 7 as an etching mask, the silicon nitride film 15 is patterned.

This silicon nitride film 15 is etched by
Using a reactive ion etching apparatus, a mixed gas of sulfur hexafluoride (SF ₆ ), helium (He), and trifluoromethane (CHF ₃ ) is used as an etching gas.

Then, an oxidation process is performed to form a top oxide film 17 made of a silicon oxide film on the silicon nitride film 15.
It is formed with a film thickness of 5 nm. The top oxide film 17 is formed under the oxidizing conditions of a temperature of 900 ° C. and a time of 60 minutes in a steam oxidizing atmosphere.

The top oxide film 17 is replaced with the silicon nitride film 1
The film thickness of the silicon nitride film 15 is reduced by forming it on the film 5, and the film thickness is changed from the initial film thickness of 11 nm to 8 nm.

As a result, the memory gate insulating film 19 including the tunnel oxide film 13, the silicon nitride film 15, and the top oxide film 17 is formed in the memory transistor formation region.
Further, the MO of the regions on both sides of the memory gate insulating film 19 is
The MOS gate insulating film 21 can be formed in the formation region of the S transistor.

In the oxidation process for forming the top oxide film 17, the oxidant diffuses in the MOS gate insulating film 21 and reaches the semiconductor substrate 11, so that the semiconductor substrate 11 is also oxidized. However, the increase in the film thickness of the MOS gate insulating film 21 is as small as 0.5 nm or less, together with the increase in the film thickness of the oxidation treatment at the time of forming the tunnel oxide film 13.

Thereafter, the gate electrode material 23 is formed on the entire surface by the same process steps as those of the embodiment described with reference to FIGS. 1 to 5 or the embodiment described with reference to FIGS. A photosensitive resin 27 is patterned on the gate electrode material 23 in the shape of a gate electrode.

Next, as shown in FIG. 13, the photosensitive resin 2
Using 7 as an etching mask, the gate electrode material 23 is etched to form a gate electrode 25.

After that, arsenic, which is an impurity of the conductivity type opposite to that of the semiconductor substrate 11, is introduced into the semiconductor substrate 11 in the region where the gate electrode 25 is aligned to form the source region 35 and the drain region 37.

Next, as shown in FIG. 14, the interlayer insulating film 4
1 is formed on the entire surface, and the interlayer insulating film 41 is etched using a photosensitive resin as an etching mask to form a contact hole.

After that, a wiring material is formed, and the wiring material is etched using the photosensitive resin as an etching mask to form the wiring 43.

As a result, a semiconductor nonvolatile memory device having the MOS transistor 37 adjacent to the memory transistor 35 and on both sides thereof can be formed.

The structure of a semiconductor nonvolatile memory device according to another embodiment of the present invention will be described with reference to FIG.

The difference between the embodiment described with reference to FIGS. 6 to 10 and the embodiment described with reference to FIGS. 11 to 14 and the embodiment described with reference to FIG. End face, silicon nitride film 15 and top oxide film 1
7 is a positional relationship with 7 and the end surface portion.

That is, as shown in FIG. 15, the end surface portion of the MOS gate insulating film 21 on the opposite side of the source region 35 and the drain region 37, that is, the opening end surface portion of the MOS gate insulating film 21, the silicon nitride film 15 and the top surface. The end surface of the oxide film 17 and the end surface of the oxide film 17 are arranged at substantially the same position.

The manufacturing method for obtaining the semiconductor nonvolatile memory device shown in FIG. 15 is the manufacturing method described with reference to FIGS. 6 to 10 or the manufacturing method described with reference to FIGS. 11 to 14. can do.

Although the end face of the MOS gate insulating film 21 and the end face of the silicon nitride film 15 are in contact with each other in FIG. 15, the end face of the MOS gate insulating film 21 and the silicon nitride film are not in contact with each other. It may be configured so as to be in contact with the top oxide film 17 on the end face portion of 15.

That is, it may be configured so that no gap is formed between the MOS gate insulating film 21 and the silicon nitride film 15 or the top oxide film 17.

Further, as shown in FIG.
The end surface portion of the gate insulating film 21 and the end surface portion of the silicon nitride film 15 are set to substantially the same position, and the top oxide film 17
May be configured so as to partially overlap with the MOS gate insulating film 21. At this time, the end face portion of the MOS gate insulating film 21 and the end face portion of the silicon nitride film 15 are in contact with each other, and M
The end face portion of the OS gate insulating film 21 and the end face portion of the tunnel oxide film 13 are also in contact with each other.

In the method of manufacturing the structure shown in FIG. 16, the tunnel oxide film 13 and the silicon nitride film 15 are formed after forming the MOS gate insulating film 21 having an opening, and the end face portion of the silicon nitride film 15 and the MOS gate are formed. The end surface of the insulating film 21 is patterned so as to be at substantially the same position, and then,
By performing an oxidation process, the top oxide film 17 is formed on the surface of the silicon nitride film 15. The subsequent process is shown in FIG.
10 to 10 or the same processing as the embodiment described with reference to FIGS. 11 to 14 may be performed.

[0134]

As is apparent from the above description, according to the structure and the manufacturing method of the semiconductor nonvolatile memory device of the present invention,
MOS transistors are formed on the drain region side as well as on the source region side.

Therefore, the high potential between the drain region and the gate electrode, which is generated when reading information from the memory transistor in the written state, can be lowered by the MOS transistor. Therefore, it is possible to suppress the generation of off-current in the gate voltage-drain current characteristics. As a result, a data failure does not occur when writing information in the memory transistor, and a highly reliable semiconductor nonvolatile memory device can be obtained.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a method for manufacturing a semiconductor nonvolatile memory device according to an example of the present invention.

FIG. 2 is a cross-sectional view showing the method of manufacturing the semiconductor nonvolatile memory device according to the example of the invention.

FIG. 3 is a cross-sectional view showing the method for manufacturing the semiconductor nonvolatile memory device in the example of the present invention.

FIG. 4 is a cross-sectional view showing the method for manufacturing the semiconductor nonvolatile memory device in the example of the present invention.

FIG. 5 is a cross-sectional view showing the structure and manufacturing method of a semiconductor nonvolatile memory device according to an example of the present invention.

FIG. 6 is a cross-sectional view showing the method for manufacturing the semiconductor nonvolatile memory device in the example of the present invention.

FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor nonvolatile memory device in the example of the present invention.

FIG. 8 is a cross-sectional view showing the method for manufacturing the semiconductor nonvolatile memory device in the example of the present invention.

FIG. 9 is a cross-sectional view showing the method for manufacturing the semiconductor nonvolatile memory device in the example of the present invention.

FIG. 10 is a cross-sectional view showing the structure and manufacturing method of a semiconductor nonvolatile memory device according to an example of the present invention.

FIG. 11 is a cross-sectional view showing the method of manufacturing the semiconductor nonvolatile memory device in the example of the present invention.

FIG. 12 is a cross-sectional view showing the method for manufacturing the semiconductor nonvolatile memory device in the example of the present invention.

FIG. 13 is a cross-sectional view showing the method for manufacturing the semiconductor nonvolatile memory device in the example of the present invention.

FIG. 14 is a cross-sectional view showing the structure and manufacturing method of a semiconductor nonvolatile memory device according to an example of the present invention.

FIG. 15 is a cross-sectional view showing the structure and manufacturing method of a semiconductor nonvolatile memory device according to an example of the present invention.

FIG. 16 is a cross-sectional view showing the structure and manufacturing method of a semiconductor nonvolatile memory device according to an example of the present invention.

FIG. 17 is a cross-sectional view showing a structure of a semiconductor nonvolatile memory device in a conventional example.

FIG. 18 is a graph showing the relationship between the gate voltage and the drain current for explaining the problems in the conventional example.

[Explanation of symbols]

 13 tunnel oxide film 15 silicon nitride film 17 top oxide film 19 memory gate insulating film 21 MOS gate insulating film 25 gate electrode 35 source region 37 drain region

Claims (10)

[Claims] 1. A memory gate insulating film comprising a tunnel oxide film, a silicon nitride film and a top oxide film provided on a semiconductor substrate, a MOS gate insulating film provided on both sides of the memory gate insulating film, a memory gate insulating film and a MOS gate. A gate electrode provided on the insulating film, a source region drain region having a conductivity type opposite to that of the semiconductor substrate provided in a region matching the gate electrode, an interlayer insulating film having a contact hole, and a source region drain region via the contact hole A semiconductor nonvolatile memory device, comprising: a wiring connected to the semiconductor nonvolatile memory device. 2. A memory gate insulating film comprising a tunnel oxide film, a silicon nitride film, and a top oxide film provided on a semiconductor substrate, and a MOS gate insulating film provided on both sides of the memory gate insulating film, and an end face of the MOS gate insulating film. A gate electrode provided on the memory gate insulating film and the MOS gate insulating film such that the tunnel oxide film, the silicon nitride film, and the end surface of the top oxide film are in contact with each other, and provided in a region where the gate electrode is aligned, and the semiconductor substrate has a reverse conductivity. A source region and a drain region of the mold,
A semiconductor nonvolatile memory device comprising: an interlayer insulating film having a contact hole; and a wiring connected to the source region and the drain region through the contact hole. 3. A MOS gate insulating film provided on a semiconductor substrate, a tunnel oxide film provided on a semiconductor substrate, a silicon nitride film and a top oxide film provided so as to partially overlap with each other on a MOS gate insulating film, and a tunnel oxide film. A gate electrode provided on a memory gate insulating film made of a silicon nitride film and a top oxide film and a MOS gate insulating film, a source region and a drain region of a conductivity type opposite to the semiconductor substrate provided in a region where the gate electrode is aligned, and a contact A semiconductor nonvolatile memory device comprising: an interlayer insulating film having a hole; and a wiring connected to a source region and a drain region through a contact hole. 4. A MOS gate insulating film provided on a semiconductor substrate, a tunnel oxide film provided on a semiconductor substrate, a silicon nitride film and a top oxide film provided at substantially the same position as an end face of the MOS gate insulating film, a tunnel oxide film and a nitride film. A gate electrode provided on a memory gate insulating film made of a silicon film and a top oxide film and a MOS gate insulating film, a source region and a drain region of a conductivity type opposite to that of a semiconductor substrate provided in a region where the gate electrode is aligned, and a contact hole A semiconductor non-volatile memory device comprising: an interlayer insulating film having: and a wiring connected to a source region and a drain region through a contact hole. 5. A MOS gate insulating film provided on a semiconductor substrate, and an end face of the MOS gate insulating film and an end face of a silicon nitride film and a top oxide film are provided at substantially the same position to form the MOS gate insulating film and the silicon nitride film. A gate electrode provided on the MOS gate insulating film and the memory gate insulating film made of the tunnel oxide film, the silicon nitride film, and the top oxide film so as to be in contact with each other, and provided in a region in which the gate electrode is aligned and having a conductivity opposite to that of the semiconductor substrate. A semiconductor non-volatile memory device comprising: a source region drain region of a mold, an interlayer insulating film having a contact hole, and a wiring connected to the source region drain region through the contact hole. 6. A MOS gate insulating film provided on a semiconductor substrate, an end surface of the MOS gate insulating film and an end surface of the silicon nitride film are provided at substantially the same position, and a part of the top oxide film is a MOS.
The MOS gate insulating film and the silicon nitride film are in contact with each other so as to overlap with the gate insulating film, and are provided on the memory gate insulating film including the tunnel oxide film, the silicon nitride film, and the top oxide film, and the MOS gate insulating film. A gate electrode, a source region / drain region having a conductivity type opposite to that of the semiconductor substrate provided in a region aligned with the gate electrode, an interlayer insulating film having a contact hole, and a wiring connected to the source region / drain region through the contact hole are provided. A semiconductor nonvolatile memory device, comprising: 7. A MOS gate insulating film provided on a semiconductor substrate, and an end surface of this MOS gate insulating film and an end surface of a silicon nitride film and a top oxide film are provided at substantially the same position to form a MOS.
The gate electrode is aligned with the gate electrode provided on the memory gate insulating film composed of the tunnel oxide film, the silicon nitride film and the top oxide film and the MOS gate insulating film so that the gate insulating film and the top oxide film are in contact with each other. A semiconductor nonvolatile memory comprising a source region drain region having a conductivity type opposite to that of a semiconductor substrate provided in the region, an interlayer insulating film having a contact hole, and a wiring connected to the source region drain region through the contact hole. apparatus. 8. A step of sequentially forming a tunnel oxide film and a silicon nitride film on a semiconductor substrate and forming a photosensitive resin on the silicon nitride film, and a step of forming the photosensitive resin on the silicon nitride film and the tunnel oxide film using the photosensitive resin as an etching mask. A step of patterning the film, a step of forming a MOS gate insulating film on the semiconductor substrate and a top oxide film on the silicon nitride film by performing an oxidation process, and a gate electrode material is formed on the entire surface,
A step of forming a photosensitive resin on the gate electrode material, patterning the gate electrode material using the photosensitive resin as an etching mask to form a gate electrode, and introducing impurities into the semiconductor substrate in a region aligned with the gate electrode. And a step of forming an interlayer insulating film over the entire surface, forming a contact hole in the interlayer insulating film, and forming a wiring. Method. 9. A step of forming a MOS gate insulating film on a semiconductor substrate, forming a photosensitive resin on the MOS gate insulating film, patterning the MOS gate insulating film by using the photosensitive resin as an etching mask, and oxidation. A step of forming a tunnel oxide film on the semiconductor substrate in the opening of the MOS gate insulating film by performing processing, forming a silicon nitride film and a top oxide film on the entire surface, and forming a photosensitive resin on the top oxide film; A step of patterning a top oxide film and a silicon nitride film using a photosensitive resin as an etching mask, a step of forming a gate electrode material on the entire surface and forming a photosensitive resin on the gate electrode material, and a photosensitive resin Is used as an etching mask to form the gate electrode by patterning the gate electrode material, and impurities are introduced into the semiconductor substrate in the region aligned with the gate electrode. Manufacturing a semiconductor non-volatile memory device, which includes a step of forming a drain region and a step of forming an interlayer insulating film on the entire surface, forming a contact hole in the interlayer insulating film, and forming a wiring. Method. 10. A step of forming a MOS gate insulating film on a semiconductor substrate, forming a photosensitive resin on the MOS gate insulating film, and patterning the MOS gate insulating film using the photosensitive resin as an etching mask. A step of forming a tunnel oxide film on the semiconductor substrate in the opening of the MOS gate insulating film by performing an oxidation process, forming a silicon nitride film on the entire surface, and forming a photosensitive resin on the silicon nitride film; The silicon nitride film is patterned using the resin as an etching mask, an oxidation treatment is performed to form a top oxide film on the silicon nitride film, a gate electrode material is formed on the entire surface, and a photosensitive resin is formed on the gate electrode material. Step and pattern the gate electrode material using the photosensitive resin as an etching mask to form the gate electrode, A step of introducing impurities into the body substrate to form a source region and a drain region, an interlayer insulating film is formed on the entire surface, and a contact hole is formed in the interlayer insulating film,
A method of manufacturing a semiconductor nonvolatile memory device, comprising the step of forming wiring.