JPH08250725A - Semiconductor device - Google Patents

Abstract

PURPOSE: To enable a leakage current to be reduced by a parasitic MOS region by a method wherein a gate electrode is provided on an element separating region opposite to the gate electrode in the lengthwise direction so that a current path formed beneath the gate electrode may be formed in the channel region excluding the channel region on the end of the element separating region. CONSTITUTION: Within the semiconductor device, a semiconductor layer 3 provided using an SOI substrate completely insulation-separated by an interlayer insulating film 32 while a gate electrode 8 provided on the semiconductor layer 3 is provided on an element separating region end part so as to cover the parasitic MOS region opposite to the element separating region in the long direction on the boundary between the simi-conductor layer 3 and the interlayer insulating film 32. On the other hand, a source 6 and a drain 5 made of high concentration impurity layers are provided on the semiconductor layer 3 matching this gate electrode 8. In such a semiconductor device, since the gate electrode 8 is also provided on the element separating region end part, the element separating region forming a parasitic MOS region does not exist in the current path running between the drain 5 and the spource 6 thereby enabling a leakage current application to be checked.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a MOS type semiconductor device or a MONOS type semiconductor nonvolatile memory device formed on a semiconductor substrate, and more particularly to a structure of a semiconductor device for reducing a leak current generated at an end of an element isolation region. .

[0002]

2. Description of the Related Art A semiconductor substrate having a semiconductor layer on an insulating film formed on a supporting substrate, a so-called SOI (Silicon)
A semiconductor device using an on insulator substrate is known.

It is known that a semiconductor device using this SOI substrate has an advantage that elements can be completely isolated from each other and latch-up and soft error can be suppressed.

Furthermore, in the semiconductor device in which the semiconductor layer formed on the insulating film is thinned, most of the depletion layer charges are governed by the potential of the gate, so that the short channel effect is suppressed and the current driving capability is improved. The effect is obtained.

The structure of a conventional semiconductor device using this SOI substrate will be described with reference to the sectional view of FIG. FIG.
As shown in FIG. 2, an SOI substrate 4 including a supporting substrate 1, an insulating film 2 and a semiconductor layer 3 is used. And the semiconductor layer 3 is
The interlayer insulating film 32 and the insulating film 2 completely insulate and separate.

A gate oxide film 14 and a gate electrode 8 are provided on the channel region 7 provided in the semiconductor layer 3, so-called M.
It constitutes an OS type semiconductor device.

Further, a source 6 and a drain 5 are provided in the semiconductor layer 3 in the region matching the gate electrode 8. Then, the high-concentration impurity layers of the source 6 and the drain 5 provided in alignment with the gate electrode 8 are in contact with the insulating film 2.

Further, a wiring 33 connected to the source 6 and the drain 5 is provided through a contact hole provided in the interlayer insulating film 32.

Next, the plane pattern structure of the conventional MOS type semiconductor device using the SOI substrate 4 will be described with reference to the plan view of FIG.

As shown in FIG. 13, the periphery of the semiconductor layer 3 formed on the SOI substrate is completely insulated and separated by the interlayer insulating film 32.

A gate electrode 8 is provided on the channel region 7 provided in the semiconductor layer 3 via a gate oxide film, so-called M.
It constitutes an OS type semiconductor device.

Further, a source 6 and a drain 5 are provided in the semiconductor layer 3 in the region matching the gate electrode 8.

Further, a wiring 33 connected to the source 6 and the drain 5 is provided through a contact hole provided in the interlayer insulating film 32.

A semiconductor device using this SOI substrate has an element isolation region edge which is a boundary between the semiconductor layer 3 and the interlayer insulating film 32 around the semiconductor layer 3, and a gate electrode formed on the element isolation region edge. And 8 form a parasitic MOS region 9.

The structure of the parasitic MOS region 9 will be described with reference to FIG. 14, which is a cross-sectional view of the prior art showing a cross section taken along the line AB in FIG. 13 showing the planar pattern shape of the prior art.

The parasitic MOS region 9 is a boundary between the semiconductor layer 3 and the interlayer insulating film 32, and is composed of a gate oxide film 14 and a gate electrode 8 in the direction perpendicular to the channel region 7.
Form the OS structure.

In the parasitic MOS region 9, the electric field from the normal channel region 7 and the electric field from the MOS formed on the side wall of the semiconductor layer 3 are added, and the normal channel region 7 is added.
A channel is formed in a lower electric field than that, and a leak current is generated.

[0018]

In the MOS type semiconductor device described with reference to FIG. 14, the parasitic MOS region 9 is formed. Therefore, when driving a MOS semiconductor device,
In the parasitic MOS region 9, an electric field in a direction perpendicular to the normal gate electrode 8 and an electric field in a parallel direction from the gate electrode 8 formed on the sidewall portion of the semiconductor layer 3 are added, so that a leak current is generated. .

The characteristic of the leak current due to the parasitic MOS region 9 will be described with reference to the graph of FIG.

FIG. 15 shows the correlation between the gate voltage and the drain current of the MOS semiconductor device. The horizontal axis represents the gate voltage, and the vertical axis represents the drain current in logarithm.

A normal MOS semiconductor device has a drain current of 1 at a gate voltage of zero V as shown by the solid line in FIG.
It is very small, below pA.

However, in the MOS type semiconductor device in which the parasitic MOS region 9 exists, the drain current flows even at the gate voltage of 0 V due to the leakage current as shown by the broken line in FIG. 15, which causes malfunction in the system and increase in power consumption. Causes problems.

Next, the structure of the semiconductor nonvolatile memory device having the similar SOI structure described in FIG. 12 will be described with reference to FIG.
Will be described with reference to the sectional view of FIG.

As shown in FIG. 3, the SOI substrate 4 comprises a support substrate 1, an insulating film 2 and a semiconductor layer 3. The periphery and the lower surface of the semiconductor layer 3 are completely insulated and separated by the interlayer insulating film 32 and the insulating film 2.

Further, a channel region 7 provided in the semiconductor layer 3
A tunnel oxide film 11, a silicon nitride film 12, a top oxide film 13 and a gate electrode 8 are provided on top of the so-called MON.
It constitutes an OS type semiconductor nonvolatile memory device.

The tunnel oxide film 11, the silicon nitride film 12, and the top oxide film 13 serve as a memory gate insulating film.

Further, the source 6 and the drain 5 are provided in the semiconductor layer 3 in the region matching the gate electrode 8.

The high-concentration impurity layer in the region of the source 6 and the drain 5 provided in alignment with the gate electrode 8 is in contact with the insulating film 2. Then, a wiring 33 connected to the source 6 and the drain 5 is provided through a contact hole provided in the interlayer insulating film 32.

Also in the semiconductor non-volatile memory device using the SOI substrate 4 including the supporting substrate 1, the insulating film 2 and the semiconductor layer 3, the MOS described with reference to FIGS.
However, there is a problem that a leak current is generated in the parasitic MOS region, which is a problem in the semiconductor device.

An object of the present invention is to solve the above problems and provide a structure for obtaining a semiconductor device capable of reducing a leak current due to a parasitic MOS region.

[0031]

In order to achieve the above object, the structure of the semiconductor device of the present invention adopts the following means.

The semiconductor device of the present invention is an MO device including a gate insulating film provided on a semiconductor substrate including a supporting substrate, an insulating film and a semiconductor layer, and a gate electrode provided on the gate insulating film.
In the S-type semiconductor device, a semiconductor layer surrounded by an element isolation region is provided, and a gate electrode is opposed in the longitudinal direction so that a current path formed under the gate electrode is formed in a channel region other than the channel region at the end of the element isolation region. It is characterized in that it is provided on the element isolation region.

The semiconductor device of the present invention comprises an MO including a gate insulating film provided on a semiconductor substrate composed of a supporting substrate, an insulating film and a semiconductor layer, and a gate electrode provided on the gate insulating film.
In the S-type semiconductor device, a quadrangular semiconductor layer surrounded from four sides is provided in the element isolation region, and a current path formed under the gate electrode is formed in a channel region other than the channel region at the end of the element isolation region. Are provided on the element isolation regions facing each other in the four directions.

The semiconductor device of the present invention is an MO device including a gate insulating film provided on a semiconductor substrate including a supporting substrate, an insulating film, and a semiconductor layer, and a gate electrode provided on the gate insulating film.
In the S-type semiconductor device, a semiconductor layer surrounded by an element isolation region is provided, and a gate length is set so that a current path formed under the gate electrode is formed in a channel region other than a channel region at an end of the element isolation region. In the above, it is characterized in that it is longer than this gate length.

The semiconductor device of the present invention is an MO device including a gate insulating film provided on a semiconductor substrate including a supporting substrate, an insulating film and a semiconductor layer, and a gate electrode provided on the gate insulating film.
In the S-type semiconductor device, a rectangular semiconductor layer surrounded from four sides is provided in the element isolation region, and a current path formed under the gate electrode is formed in a channel region other than the channel region at the end of the element isolation region. On the element isolation region,
It is characterized in that it is longer than this gate length.

The semiconductor device of the present invention is a MO device including a gate insulating film provided on a semiconductor substrate composed of a supporting substrate, an insulating film and a semiconductor layer, and a gate electrode provided on the gate insulating film.
The S-type semiconductor device is characterized in that the element isolation region formed under the gate electrode is provided with an element isolation region provided so as to lengthen the channel region under the gate electrode and increase the channel resistance in this region. .

A semiconductor device according to the present invention comprises a memory oxide film formed on a semiconductor substrate including a supporting substrate, an insulating film and a semiconductor layer, a memory insulating film including a silicon nitride film and a top oxide film, and a memory insulating film on the memory insulating film. In the MONOS type semiconductor device including the gate electrode provided in, the semiconductor layer surrounded by the element isolation region is provided, and the current path formed under the gate electrode is formed in the channel region other than the channel region at the end of the element isolation region. , The gate electrodes are provided on the element isolation regions facing each other in the longitudinal direction.

The semiconductor device according to the present invention includes a memory oxide film formed on a semiconductor substrate including a support substrate, an insulating film, and a semiconductor layer, a memory insulating film including a silicon nitride film, and a top oxide film, and a memory insulating film on the memory insulating film. In a MONOS type semiconductor device including a gate electrode provided in a device, a quadrilateral semiconductor layer surrounded by four sides is provided in an element isolation region, and a current path formed under the gate electrode is formed in a channel region other than a channel region at an end of the element isolation region. As described above, the gate electrode is provided on the opposing element isolation region in the four directions.

The semiconductor device according to the present invention includes a memory oxide film formed on a semiconductor substrate including a support substrate, an insulating film and a semiconductor layer, a memory insulating film including a silicon nitride film and a top oxide film, and a memory insulating film on the memory insulating film. In the MONOS type semiconductor device including the gate electrode provided in, the semiconductor layer surrounded by the element isolation region is provided, and the current path formed under the gate electrode is formed in the channel region other than the channel region at the end of the element isolation region. The gate length on the element isolation region is longer than this gate length.

The semiconductor device according to the present invention includes a memory oxide film formed on a semiconductor substrate including a support substrate, an insulating film and a semiconductor layer, a memory insulating film including a silicon nitride film and a top oxide film, and a memory insulating film on the memory insulating film. In a MONOS type semiconductor device including a gate electrode provided in a device, a quadrilateral semiconductor layer surrounded by four sides is provided in an element isolation region, and a current path formed under the gate electrode is formed in a channel region other than a channel region at an end of the element isolation region. It is characterized in that the gate length is made longer than the gate length on the element isolation region as described in (1).

The semiconductor device according to the present invention comprises a memory oxide film provided on a semiconductor substrate composed of a supporting substrate, an insulating film and a semiconductor layer, a memory insulating film composed of a silicon nitride film and a top oxide film, and a memory insulating film on the memory insulating film. In a MONOS type semiconductor device including a gate electrode provided under the gate electrode, the element isolation region formed under the gate electrode is formed under the gate electrode by extending the channel region and increasing the channel resistance in this region. It is characterized by including.

[0042]

In the semiconductor device of the present invention, the overlapping portion with the gate electrode at the end of the element isolation region is provided so as to be larger than the overlapping portion of the channel region.

Alternatively, in the semiconductor device of the present invention, a region overlapping the gate electrode at the end of the element isolation region, that is, a parasitic M
The semiconductor layer in the OS region is provided long so as to project below the gate electrode.

For this reason, the channel length of the parasitic MOS region becomes long, the channel resistance of the parasitic MOS region is increased, and the threshold voltage is made higher than that of the normal channel region.

Therefore, the leakage due to the parasitic MOS region can be reduced, and the leakage current at the gate voltage of zero V can be eliminated.

Similarly, in the semiconductor nonvolatile memory device, since the channel resistance of the parasitic MOS region can be increased, the leak current is not generated by the parasitic MOS region.

[0047]

Embodiments of the present invention will be described below with reference to the drawings. First, the structure of a semiconductor device according to an embodiment of the present invention will be described with reference to the sectional view of FIG.

The semiconductor device of the present invention uses an SOI substrate 4 including a supporting substrate 1, an insulating film 2 and a semiconductor layer 3 as shown in FIG. Then, a MOS type semiconductor device including the gate electrode 8, the gate oxide film 14, and the semiconductor layer 3 is provided on the SOI substrate 4.

Diffusion layers of the source 6 and the drain 5, which are high-concentration impurity layers, are provided in the region of the semiconductor layer 3 which is aligned with the gate electrode. Further, the semiconductor layer 3 is completely insulated and separated by the interlayer insulating film 32 and the insulating film 2, and the wiring 33 connected to the source 6 and the drain 5 is provided by the contact hole provided in the interlayer insulating film 32.

As described above, the semiconductor device of the present invention has the same cross-sectional structure as that of the prior art, but the plane structure is devised to reduce the leakage current due to the parasitic MOS.
Next, a planar structure of the semiconductor device for reducing the leak current will be described with reference to FIG.

FIG. 2 is a plan view showing a plane pattern shape of a semiconductor device according to an embodiment of the present invention. As shown in FIG. 2, in the semiconductor device of the present invention, the semiconductor layer 3 provided using the SOI substrate is completely insulated and separated by the interlayer insulating film 32, and the gate electrode 8 provided on the semiconductor layer 3 via the gate oxide film. Is provided on the edge of the element isolation region so as to cover the parasitic MOS regions facing each other in the longitudinal direction of the element isolation region which is the boundary between the semiconductor layer 3 and the interlayer insulating film 32.

The semiconductor layer 3 aligned with the gate electrode 8 is provided with a source 6 and a drain 5 which are high-concentration impurity layers. Further, a wiring 33 connected to the source 6 and the drain 5 is provided by a contact hole provided in the interlayer insulating film 32.

The semiconductor device of the present invention shown in FIGS. 1 and 2 has a current flowing between the drain 5 and the source 6 in the channel region formed under the gate electrode 8 as in the case of a normal MOS semiconductor device. Drive by flowing.

In the semiconductor device of the present invention shown in FIG. 2, the gate electrode 8 is provided also at the edge of the element isolation region, and the drain 5 is formed.
There is no element isolation region forming a parasitic MOS region in the current path flowing between the source 6 and the source 6. Therefore, no leak current is generated, the gate voltage-drain current characteristic shown by the solid line in the graph of FIG. 15 is obtained, and stable transistor operation can be obtained.

Next, the structure of the semiconductor nonvolatile memory device according to the embodiment of the present invention will be described. FIG. 3 is a sectional view showing a semiconductor nonvolatile memory device according to an embodiment of the present invention.
As shown in FIG. 3, the semiconductor nonvolatile memory device of the present invention has an ONO film including a tunnel oxide film 11, a silicon nitride film 12 and a top oxide film 13 formed on the semiconductor layer 3, and has a MONOS type semiconductor. It constitutes a non-volatile memory element.

In this MONOS type semiconductor non-volatile memory device, the gate electrode 8 is connected to the semiconductor layer 3 and the interlayer insulating film 32 as in the MOS type semiconductor device described with reference to FIG.
It is provided on the edge of the element isolation region so as to cover the parasitic MOS regions facing each other in the longitudinal direction of the element isolation region which is the boundary with

As described above, in the semiconductor nonvolatile memory device of the present invention, the element isolation region edge forming the parasitic MOS region does not exist in the current path flowing between the drain 5 and the source 6. Therefore, there is no leak current and a stable memory operation can be obtained.

Next, the structure of a semiconductor device according to another embodiment of the present invention will be described with reference to FIGS.

FIG. 4 shows an embodiment of a structure in which the channel length 91 formed by the gate electrode 8 of the semiconductor device of the present invention is made longer on the parasitic MOS region 9 than the region where the wiring 33 faces. That is, a part of the boundary area between the channel region 7 and the interlayer insulating film 32 facing each other is covered with the gate electrode 8.

In the embodiment shown in FIG. 4, the gate electrode 8 on the parasitic MOS region 9 is provided longer than the channel length 91 of the channel region 7 facing the wiring 33, and the parasitic MO region 9 is formed.
The channel resistance of the S region 9 can be designed higher than that of the channel region 7. Therefore, it is possible to suppress the leak current due to the parasitic MOS.

FIG. 5 shows an embodiment of a structure in which the semiconductor layer 3 of the parasitic MOS region 9 which is a region where the gate electrode 8 of the semiconductor device of the present invention overlaps the edge of the element isolation region is extended to the lower surface region of the gate electrode 8. Show.

In the embodiment shown in FIG. 5, since the semiconductor layer 3 of the parasitic MOS region 9 is extended below the gate electrode 8 in parallel with the gate electrode, the channel length of the parasitic MOS region 9 is extended. Therefore, the resistance of the channel region of the parasitic MOS can be increased, so that the leak current due to the parasitic MOS region 9 can be suppressed.

In the embodiments described with reference to FIGS. 4 and 5, the gate oxide film 14 is the tunnel oxide film 11, the silicon nitride film 12 and the top oxide film. M by changing to 13
An ONOS type semiconductor nonvolatile memory device can be obtained.

In this semiconductor nonvolatile memory device, the parasitic M
Since the gate electrode 8 on the OS region 9 is provided longer than the channel length 91 of the channel region 7, the channel resistance of the parasitic MOS region 9 can be designed higher than the resistance of the channel region 7.
Therefore, it is possible to suppress the leak current due to the parasitic MOS region.

Next, a manufacturing method for forming the semiconductor device shown in FIG. 1 will be described with reference to the sectional views of FIGS.

First, as shown in FIG. 6, oxygen ions were implanted into a P-type single crystal silicon substrate at a dose of 4 × 10 ¹⁷ c.
Ion implantation is performed at m ^-2 and energy of 120 KeV. After that, thermal annealing is performed at a temperature of 1320 ° C. for 6 hours, and the supporting substrate 1, the insulating film 2 having a film thickness of 80 nm, and the film thickness of 180 are formed.
nm type P-type semiconductor layer 3 and so-called SIMOX
(Separation by IMplanted
OXygen) SOI substrate is formed.

After that, a photosensitive resin 51 is formed on the entire surface of the SOI substrate by a spin coating method, and an exposure process and a development process are performed using a predetermined photomask, so that the semiconductor layer 3 is formed.
The photosensitive resin 51 is patterned so that the photosensitive resin 51 is formed on the formation region of.

After that, using the photosensitive resin 51 as an etching mask, the semiconductor layer 3 is formed 18 times until it reaches the insulating film 2.
Etch everything to a thickness of 0 nm. This etching process is performed by using a reactive ion etching apparatus using a mixed gas of sulfur hexafluoride (SF ₆ ), helium (He) and oxygen (O ₂ ) as an etching gas.

After etching the semiconductor layer 3, the photosensitive resin 5
Remove 1. As a result, the semiconductor layer 3 forming the MOS type semiconductor device can be formed.

Next, as shown in FIG. 7, the semiconductor layer 3 is oxidized to form a gate oxide film 14 of silicon oxide with a film thickness of 20 nm. The gate oxide film 14 is formed under the conditions of a temperature of 1 in a mixed gas atmosphere of oxygen and nitrogen.
It is carried out under conditions of 000 ° C. and time of 30 minutes.

After that, monosilane (Si
The film thickness is 400 by the chemical vapor deposition method using H ₄ ).
A gate electrode material 81 made of a polycrystalline silicon film of nm thickness is formed on the entire surface.

After that, a photosensitive resin 51 is formed on the entire surface by a spin coating method, and an exposure process and a development process are performed using a predetermined photomask to pattern the photosensitive resin 51 into the shape of the gate electrode 8.

Next, as shown in FIG.
Is used as an etching mask to pattern the gate electrode material 81 to form the gate electrode 8.

The etching of the gate electrode 8 is carried out by using a reactive ion etching apparatus using a mixed gas of sulfur hexafluoride (SF ₆ ) and oxygen (O ₂ ) as an etching gas. After etching the polycrystalline silicon film, the photosensitive resin 51 is removed.

Thereafter, arsenic, which is an impurity having a conductivity type opposite to that of the semiconductor layer 8, is introduced into the semiconductor layer 3 in a region aligned with the gate electrode 8 to form a high-concentration impurity layer to be the source 6 region and the drain 5 region. Form. The ion implantation amount of arsenic for forming this high-concentration impurity layer is performed under the condition of about 3 × 10 ¹⁵ cm ⁻² .

After that, an interlayer insulating film 32 made of a silicon oxide film containing phosphorus and boron is formed on the entire surface by chemical vapor deposition to have a film thickness of about 400 nm.

Next, the photosensitive resin 51 is formed on the interlayer insulating film 32.
Is formed by a spin coating method, and then an exposure process and a development process are performed using a predetermined photomask to pattern the photosensitive resin 51 having openings corresponding to the contact holes.

Then, as shown in FIG. 9, the interlayer insulating film 32 is etched using the patterned photosensitive resin 51 as an etching mask to form a contact hole.

This contact hole is etched by using a reactive ion etching apparatus and using trifluoromethane (C
A mixed gas of HF ₃ ) and methane difluoride (CH ₂ F ₂ ) is used as an etching gas.

After that, a wiring material made of aluminum containing silicon and copper was removed by using a sputtering device.
It is formed on the entire surface with a film thickness of about 800 nm.

Thereafter, a photosensitive resin (not shown) is formed on the wiring material by a spin coating method, and an exposure process and a development process are performed using a predetermined photomask to form a photosensitive film having a pattern corresponding to the wiring 33. Patterning the resin.

Thereafter, the wiring material is etched using the patterned photosensitive resin as a mask to form the wiring 33.

The wiring 33 is etched by using a reactive ion etching device and a mixed gas of chlorine (Cl ₂ ) and boron trichloride (BCl ₃ ) as an etching gas.

As a result, it is possible to form the semiconductor device of the present invention having the structure shown in FIG. 1 as a sectional structure and the planar shape shown in FIG.

Next, a method of manufacturing a semiconductor nonvolatile memory device according to another embodiment of the present invention will be described with reference to FIGS.

By performing the same processing steps as the manufacturing method described with reference to FIG. 6, the insulating film 2 and the semiconductor layer 3 are formed on the supporting substrate 1.

Next, as shown in FIG. 10, the semiconductor layer 3 is oxidized to form a tunnel oxide film 11 with a thickness of 2 nm. The conditions for forming the tunnel oxide film 11 are that the temperature is 850 ° C. and the time is 20 hours in a mixed gas atmosphere of oxygen and nitrogen.
Do in minutes.

Thereafter, the film thickness is reduced to 1 by the chemical vapor deposition method using dichlorosilane and ammonia as reaction gases.
A 1 nm silicon nitride film 12 is formed on the entire surface.

Then, in a steam oxidizing atmosphere, at a temperature of 90.
The top oxide film 13 made of silicon oxide is formed on the silicon nitride 12 under the oxidizing condition of 0 ° C. for 60 minutes.

The top oxide film 13 is replaced with the silicon nitride film 1
The film thickness of the silicon nitride film 12 is reduced by forming it on the second layer, and the film thickness is changed from the initial film thickness of 11 nm to 8 nm.

After that, monosilane (Si
The film thickness is 400 by the chemical vapor deposition method using H ₄ ).
A gate electrode material 81 made of a polycrystalline silicon film of nm thickness is formed on the entire surface.

After that, a photosensitive resin 51 is formed on the entire surface by a spin coating method, and an exposure process and a development process are performed using a predetermined photomask to pattern the photosensitive resin 51 into the shape of the gate electrode 8.

Next, as shown in FIG. 11, the photosensitive resin 5
Using 1 as an etching mask, the gate electrode material 81 is patterned to form the gate electrode 8.

The etching of the gate electrode 8 is carried out by using a reactive ion etching apparatus using a mixed gas of sulfur hexafluoride (SF ₆ ) and oxygen (O ₂ ) as an etching gas.

Subsequently, by etching the gate electrode 8, the lower top oxide film 13 and the silicon nitride film 12 are formed.
Etch and. After etching the polycrystalline silicon film, the photosensitive resin 51 is removed.

Thereafter, arsenic, which is an impurity having a conductivity type opposite to that of the semiconductor layer 8, is introduced into the semiconductor layer 3 in a region aligned with the gate electrode 8 to form a high-concentration impurity layer to be the source 6 region and the drain 5 region. Form. The ion implantation amount of arsenic for forming this high-concentration impurity layer is performed under the condition of about 3 × 10 ¹⁵ cm ⁻² .

After that, an interlayer insulating film 32 made of a silicon oxide film containing phosphorus and boron is formed on the entire surface by chemical vapor deposition so as to have a film thickness of about 400 nm.

Next, a photosensitive resin (not shown) is formed on the interlayer insulating film 32 by a spin coating method, exposed and developed using a predetermined photomask, and a photosensitive resin having openings corresponding to contact holes is formed. Pattern the resin.

After that, the interlayer insulating film 32 is etched using the patterned photosensitive resin as an etching mask to form a contact hole.

The etching of this contact hole was performed using a reactive ion etching apparatus using methane trifluoride (C
A mixed gas of HF ₃ ) and methane difluoride (CH ₂ F ₂ ) is used as an etching gas.

After that, a wiring material made of aluminum containing silicon and copper was changed by using a sputtering device.
It is formed on the entire surface with a film thickness of about 800 nm.

After that, a photosensitive resin (not shown) is formed on the wiring material by a spin coating method, and an exposure process and a development process are performed using a predetermined photomask to form a photosensitive film having a pattern corresponding to the wiring 33. Patterning the resin.

Thereafter, the wiring material is etched using the patterned photosensitive resin as an etching mask to form the wiring 33.

The etching of the wiring 33 is performed by using a reactive ion etching apparatus and a mixed gas of chlorine (Cl ₂ ) and boron trichloride (BCl ₃ ) as an etching gas.

As a result, it is possible to form the semiconductor nonvolatile memory device of the present invention, which has the sectional structure shown in FIG. 3 and the planar shape shown in FIG.

In the embodiments described above, the SIMOX substrate is used as the SOI substrate. However, after a silicon substrate on which a silicon oxide film is formed is bonded, the silicon substrate is polished to a DWB (Direct Wafer).
The semiconductor device and the semiconductor non-volatile memory device of the present invention can be formed also by using the (r Bonding) substrate.

[0107]

As is clear from the above description, in the semiconductor device of the present invention, in the semiconductor device using the SOI substrate, in the overlapping region of the element isolation region edge of the semiconductor layer and the gate electrode, which is a conventional problem. It is possible to increase the channel resistance of so-called parasitic MOS operation due to the increase of the electric field, reduce the leak current at low gate voltage when driving the semiconductor device, and obtain a semiconductor device having stable transistor operation. Further, in the structure of the semiconductor non-volatile memory device of the present invention, the leak current due to the parasitic MOS region can be reduced, and the semiconductor non-volatile memory device with improved stable write / erase operation and data retention characteristic can be obtained.

[Brief description of drawings]

FIG. 1 is a sectional view showing the structure of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a plan view showing a structure of a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a structure of a semiconductor nonvolatile device according to an embodiment of the present invention and a conventional example.

FIG. 4 is a plan view showing a structure of a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a plan view showing a structure of a semiconductor device according to an embodiment of the present invention.

FIG. 6 is a cross-sectional view showing the manufacturing method for obtaining the structure of the semiconductor device in one embodiment of the present invention.

FIG. 7 is a cross-sectional view showing the manufacturing method for obtaining the structure of the semiconductor device in one example of the present invention.

FIG. 8 is a cross-sectional view showing the manufacturing method for obtaining the structure of the semiconductor device in one embodiment of the present invention.

FIG. 9 is a cross-sectional view showing the manufacturing method for obtaining the structure of the semiconductor device in one embodiment of the present invention.

FIG. 10 is a cross-sectional view showing the manufacturing method for obtaining the structure of the semiconductor nonvolatile device in one example of the present invention.

FIG. 11 is a cross-sectional view showing the manufacturing method for obtaining the structure of the semiconductor nonvolatile device in one example of the present invention.

FIG. 12 is a cross-sectional view showing a structure of a semiconductor device in a conventional example.

FIG. 13 is a plan view showing a structure of a semiconductor device in a conventional example.

FIG. 14 is a cross-sectional view showing a structure of a semiconductor device in a conventional example.

FIG. 15 is a graph showing gate voltage and drain current characteristics of a semiconductor device according to the present invention and a conventional example.

[Explanation of symbols]

 1 Supporting Substrate 2 Insulating Film 3 Semiconductor Layer 4 SOI Substrate 5 Drain 6 Source 7 Channel Region 8 Gate Electrode 9 Parasitic MOS Region 11 Tunnel Oxide Film 12 Silicon Nitride Film 13 Top Oxide Film 14 Gate Oxide Film 21 Bulk Contact 32 Interlayer Insulation Film 33 wiring

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 29/788 H01L 29/78 613B 29/792 618Z 29/786 21/336

Claims (10)

[Claims] 1. A MOS type semiconductor device comprising a gate insulating film provided on a semiconductor substrate composed of a supporting substrate, an insulating film and a semiconductor layer, and a gate electrode provided on the gate insulating film is a semiconductor surrounded by an element isolation region. A semiconductor device, wherein a layer is provided, and the gate electrodes are provided on the element isolation regions facing each other in the longitudinal direction so that a current path formed under the gate electrode is formed in a channel region other than the channel region at the end of the element isolation region. . 2. A MOS semiconductor device comprising a gate insulating film provided on a semiconductor substrate including a supporting substrate, an insulating film and a semiconductor layer, and a gate electrode provided on the gate insulating film is surrounded by element isolation regions from four sides. A rectangular semiconductor layer is provided, and the gate electrode is provided on the opposing element isolation region in four directions so that the current path formed under the gate electrode is formed in the channel region other than the channel region at the end of the element isolation region. A semiconductor device characterized by the above. 3. A MOS type semiconductor device comprising a gate insulating film provided on a semiconductor substrate composed of a supporting substrate, an insulating film and a semiconductor layer, and a gate electrode provided on the gate insulating film is a semiconductor surrounded by an element isolation region. A semiconductor device having a layer and having a gate length longer than the gate length on the element isolation region so that a current path formed under the gate electrode is formed in a channel region other than the channel region at the end of the element isolation region. . 4. A MOS type semiconductor device comprising a gate insulating film provided on a semiconductor substrate composed of a supporting substrate, an insulating film and a semiconductor layer, and a gate electrode provided on the gate insulating film is surrounded by element isolation regions from four sides. A rectangular semiconductor layer is provided, and the gate length on the element isolation region should be longer than this gate length so that the current path formed under the gate electrode is formed on the channel region other than the channel region at the end of the element isolation region. Characteristic semiconductor device. 5. A MOS type semiconductor device comprising a gate insulating film provided on a semiconductor substrate including a supporting substrate, an insulating film and a semiconductor layer, and a gate electrode provided on the gate insulating film is an element isolation formed under the gate electrode. A semiconductor device comprising an element isolation region provided so as to lengthen the channel region under the gate electrode and increase the channel resistance in this region. 6. A memory oxide film provided on a semiconductor substrate including a supporting substrate, an insulating film and a semiconductor layer, a memory insulating film including a silicon nitride film and a top oxide film, and a gate electrode provided on the memory insulating film. In the MONOS type semiconductor device consisting of, a semiconductor layer surrounded by an element isolation region is provided, and a gate electrode is formed in a longitudinal direction so that a current path formed under the gate electrode is formed in a channel region other than the channel region at the end of the element isolation region. The semiconductor device is provided on the element isolation regions facing each other. 7. A memory oxide film provided on a semiconductor substrate including a supporting substrate, an insulating film and a semiconductor layer, a memory insulating film including a silicon nitride film and a top oxide film, and a gate electrode provided on the memory insulating film. In the MONOS type semiconductor device made of, a rectangular semiconductor layer surrounded by four sides is provided in the element isolation region, and the current path formed under the gate electrode is formed in the channel region other than the channel region at the end of the element isolation region. A semiconductor device, wherein gate electrodes are provided on opposing element isolation regions in four directions. 8. A memory oxide film provided on a semiconductor substrate including a supporting substrate, an insulating film and a semiconductor layer, a memory insulating film including a silicon nitride film and a top oxide film, and a gate electrode provided on the memory insulating film. In the MONOS type semiconductor device made of, the semiconductor layer surrounded by the element isolation region is provided, and the gate length is separated by the element so that the current path formed under the gate electrode is formed in the channel region other than the channel region at the end of the element isolation region. A semiconductor device characterized by being made longer than this gate length in a region. 9. A memory oxide film formed on a semiconductor substrate including a supporting substrate, an insulating film and a semiconductor layer, a memory insulating film including a silicon nitride film and a top oxide film, and a gate electrode provided on the memory insulating film. In the MONOS type semiconductor device made of, a rectangular semiconductor layer surrounded by four sides is provided in the element isolation region, and the current path formed under the gate electrode is formed in the channel region other than the channel region at the end of the element isolation region. A semiconductor device characterized in that the gate length is made longer than the gate length on the element isolation region. 10. A MONOS comprising a memory oxide film formed on a semiconductor substrate including a supporting substrate, an insulating film and a semiconductor layer, a memory insulating film including a silicon nitride film and a top oxide film, and a gate electrode provided on the memory insulating film. The semiconductor device is characterized by including an element isolation region formed under the gate electrode so as to lengthen the channel region under the gate electrode and increase the channel resistance in this region.