KR0166793B1 - Method of forming ldd structure in memory device - Google Patents
Method of forming ldd structure in memory device Download PDFInfo
- Publication number
- KR0166793B1 KR0166793B1 KR1019900012335A KR900012335A KR0166793B1 KR 0166793 B1 KR0166793 B1 KR 0166793B1 KR 1019900012335 A KR1019900012335 A KR 1019900012335A KR 900012335 A KR900012335 A KR 900012335A KR 0166793 B1 KR0166793 B1 KR 0166793B1
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- South Korea
- Prior art keywords
- forming
- mask
- region
- ldd structure
- gate
- Prior art date
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- 238000000034 method Methods 0.000 title abstract description 10
- 239000010408 film Substances 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 150000004767 nitrides Chemical class 0.000 claims abstract description 11
- 239000010409 thin film Substances 0.000 claims abstract description 9
- 238000005468 ion implantation Methods 0.000 claims abstract description 8
- 239000012535 impurity Substances 0.000 claims abstract description 6
- 150000002500 ions Chemical class 0.000 claims abstract description 5
- 230000015572 biosynthetic process Effects 0.000 claims abstract 4
- 239000004065 semiconductor Substances 0.000 claims abstract 3
- 230000003647 oxidation Effects 0.000 claims abstract 2
- 238000007254 oxidation reaction Methods 0.000 claims abstract 2
- 238000005530 etching Methods 0.000 description 3
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 ULSI 서브마이크론 메모리 소자의 LDD(Lightly Doping Drain) 구조 형성방법에 관한 것으로, 특히 측벽(Side Wall)을 사용하지 않고 간단한 공정에 의해 LDD 구조를 형성하기에 적당하도록 한 것이다.The present invention relates to a method of forming a lightly doping drain (LDD) structure of a ULSI submicron memory device, and in particular, is suitable for forming an LDD structure by a simple process without using a side wall.
이와 같은 본 발명의 메모리 소자의 LDD 구조 형성방법은 필드영역과 활성영역이 형성된 반도체 기판의 게이트 형성영역에 게이트패턴폭보다 작게 질화막 패턴을 형성하는 공정과, 상기 질화막 패턴을 마스크로 이용하여 활성영역에 저농도 이온주입을 실시하는 공정과, 상기 기판을 열산화하여 노출된 기판에 박막산화막을 형성하고 상기 질화막 패턴을 제거하는 공정과, 상기 박막산화막을 마스크로 이용하여 임계전압 조절용 이온주입을 실시하고 상기 박막산화막을 제거하는 공정과, 상기 반도체 기판의 게이트 형성영역에 게이트 전극을 형성하고 게이트 전극을 마스크로 활성영역에 고농도 이온주입을 실시하여 LDD 구조의 소오스 및 드레인 불순물 영역을 형성하는 공정을 포함하여 이루어진 것이다.The LDD structure forming method of the memory device of the present invention comprises the steps of forming a nitride film pattern smaller than the gate pattern width in the gate formation region of the semiconductor substrate in which the field region and the active region are formed, and using the nitride film pattern as a mask Performing a low concentration ion implantation on the substrate, forming a thin film oxide film on the exposed substrate by thermal oxidation of the substrate, removing the nitride film pattern, and performing ion implantation for controlling the threshold voltage using the thin film oxide film as a mask. Removing the thin film oxide layer, and forming a source electrode and a drain impurity region of an LDD structure by forming a gate electrode in a gate formation region of the semiconductor substrate and implanting high concentration ions into an active region using a gate electrode as a mask. It is done by.
Description
제1도는 종래 LDD 구조의 공정순서를 나타낸 단면도.1 is a cross-sectional view showing a process sequence of a conventional LDD structure.
제2도는 본 발명의 LDD 구조의 공정순서를 나타낸 단면도.2 is a cross-sectional view showing the process sequence of the LDD structure of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 기판 2 : 질화막1 substrate 2 nitride film
3 : 박막산화막 4 : 게이트전극3: thin film oxide film 4: gate electrode
5 : BPSG 6 : 메탈5: BPSG 6: metal
8 : 필드산화막 9 : 불순물 영역8: field oxide film 9: impurity region
본 발명은 ULSI 서브마이크론 메모리 소자의 LDD(Lightly Doping Drain) 구조 형성방법에 관한 것으로, 특히 측벽(Skde Wall)을 사용하지 않고 간단한 공정에 의해 LDD 구조를 형성하기에 적당하도록 한 것이다.The present invention relates to a method for forming a lightly doping drain (LDD) structure of a ULSI submicron memory device, and is particularly suitable for forming an LDD structure by a simple process without using a side wall.
종래에는 LDD 구조를 형성하기 위하여 제1도 (a)에 도시한 바와 같이 기판(1) 위에 폴리게이트(4)를 형성한 후 액티브 영역을 형성하기 위한 선택적 식각을 실시한 상태에서 예를 들어 N-를 이온주입하였으며 다음에 산화막 형성 후 RIE 식각을 실시하여 (B)와 같이 측벽(7)을 형성한 후 N+를 이온주입하여 소오스/드레인 영역을 형성하였다.Conventionally, in order to form an LDD structure, as shown in FIG. 1A, a polygate 4 is formed on a substrate 1, and then, in the state of performing selective etching to form an active region, for example, N − the ion implantation was by following the N + ions after forming the side wall 7, as shown in (B) subjected to RIE etching after forming an oxide film on the implanted to form the source / drain regions.
그러나, 상기한 바와 같은 종래 기술에 있어서는 RIE 식각을 이용하여 측벽(7)을 형성하기 때문에 공정콘트롤이 어렵고, 측벽에치시 N-영역기판에 손상을 주기 쉬운 결점이 있었다.However, in the prior art as described above, since sidewalls 7 are formed using RIE etching, process control is difficult, and there is a drawback that the N - region substrate is easily damaged when sidewalls are etched.
따라서, 본 발명은 이와 같은 종래의 결점을 해결하기 이한 것으로 측벽을 형성하지 않고 LDD 구조를 간단히 형성하는 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of simply forming an LDD structure without forming sidewalls to solve such a conventional drawback.
이하에서 본 발명은 첨부된 도면 제2도를 참고로 하여 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings of FIG. 2.
먼저 (A)와 같이 기판(1) 위에 필드영역과 액티브영역을 정의하여 필드영역에 필드산화막(8)을 형성하고 전면에 버퍼산화막과 질화막(2)을 차례로 증착한 후, 게이트패턴보다 작게 버퍼산화막 및 질화막(2) 패턴을 형성한다.First, as shown in (A), the field region and the active region are defined on the substrate 1 to form the field oxide film 8 in the field region, and the buffer oxide film and the nitride film 2 are sequentially deposited on the entire surface, and then the buffer is smaller than the gate pattern. The oxide film and nitride film 2 pattern is formed.
이어, 질화막(2) 패턴을 마스크로 이용하여 액티브 영역에 저농도(N-) 이온주입을 실시한다.Subsequently, low concentration (N − ) ion implantation is performed in the active region using the nitride film 2 pattern as a mask.
다음에 (B)와 같이 (A)와 같은 상태의 기판을 O₂분위기에서 열적산화시켜 노출된 기판에 박막산화막(3)을 형성하고, 상기 질화막(2) 패턴을 제거한 후 임계전압(VT) 이온주입을 실시한다.Next, as shown in (B), the substrate in the same state as in (A) is thermally oxidized in an O 2 atmosphere to form a thin film oxide film 3 on the exposed substrate, and after removing the nitride film 2 pattern, the threshold voltage (VT) ion Carry out the injection.
그리고 (C)와 같이 상기 박막산화막(3)을 선택적으로 제거한 후, 게이트 산화막과 폴리실리콘을 증착하고 게이트 마스크를 이용하여 게이트 전극(4)을 패터닝한다.After the thin film oxide film 3 is selectively removed as shown in (C), the gate oxide film and the polysilicon are deposited, and the gate electrode 4 is patterned using a gate mask.
그리고 게이트 전극(4)을 마스크로 기판에 고농도(N+) 이온주입을 실시하여 LDD 구조의 소오스 및 드레인 불순물 영역(9)을 형성한다.A high concentration (N + ) ion implantation is performed on the substrate using the gate electrode 4 as a mask to form the source and drain impurity regions 9 of the LDD structure.
(D)와 같이 전면에 BPSG(5)을 형성하고 상기 이온주입된 불순물 영역(9)이 노출되도록 콘택홀을 형성한 다음, 상기 불순물 영역(9)에 연결되도록 메탈(6)을 형성한다.As shown in (D), a BPSG 5 is formed on the entire surface, a contact hole is formed to expose the ion implanted impurity region 9, and then a metal 6 is formed to be connected to the impurity region 9.
이와 같이 본 발명에 의하면, 종래와 같이 측벽을 사용하지 않고도 간단한 공정으로 LDD 구조를 형성할 수 있으며, 박막산화막(3)을 이용하여 VT이온주입을 마스크 없이 조절 가능하므로 디바이스의 신뢰성을 향상시킬 수 있는 효과가 있다.Thus to be in accordance with the present invention, to form an LDD structure by a simple process without the use of the side wall as in the prior art, and can be adjusted to V T ion implantation using a thin oxide film (3) without a mask, so improving the reliability of the device It can be effective.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019900012335A KR0166793B1 (en) | 1990-08-10 | 1990-08-10 | Method of forming ldd structure in memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019900012335A KR0166793B1 (en) | 1990-08-10 | 1990-08-10 | Method of forming ldd structure in memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR920005360A KR920005360A (en) | 1992-03-28 |
| KR0166793B1 true KR0166793B1 (en) | 1999-01-15 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019900012335A KR0166793B1 (en) | 1990-08-10 | 1990-08-10 | Method of forming ldd structure in memory device |
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| Country | Link |
|---|---|
| KR (1) | KR0166793B1 (en) |
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1990
- 1990-08-10 KR KR1019900012335A patent/KR0166793B1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR920005360A (en) | 1992-03-28 |
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