KR930007101B1 - Manufacturing method of self ldd junction - Google Patents

Abstract

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Description

Self LDD Junction Transistor Manufacturing Method

1 is a conventional cross-sectional view of the process.

2 is a cross-sectional view of the process of the present invention.

3 is a cross-sectional view of a capacitor formed according to the prior art.

(b) is a cross-sectional view of the capacitor formation according to the present invention.

* Explanation of symbols for main parts of the drawings

1 substrate 2 P well

3: N well 4: Field oxide film

5: gate oxide film 6: gate polysilicon film

7: HTO 8: nitride film

9, 9a, 9b: photosensitive agent

The present invention relates to a method for manufacturing a self lightly doped drain (LDD) junction transistor, and is particularly suitable for a high grade device.

FIG. 1 is a view illustrating a general CMOS LDD junction transistor fabrication process performed after ion implantation processes for forming P wells 12, N wells 13, and field oxide films 14 and adjusting threshold voltages on a substrate 11 of the related art. A detailed description with reference to (a) to (d) is as follows.

First, as shown in (a), a high temperature oxide (HTD) (or HLD), which serves to deposit and gate capping a polysilicon layer (or polyside) 16 to be used as a gate and a gate oxide layer 15, may be used. LTO) (17) is grown and then gate masked and etched.

Then, after the masking process for limiting the N ^- S / D region is performed using the photosensitive agent 18, N ^- S / D ion implantation is performed and heat treatment is performed to form the N ^- S / D region.

Subsequently, as shown in (b), the photosensitive agent 18 is peeled off, and a masking process for limiting the P ^- S / D region is performed using another photosensitive agent 18a, followed by P ^- S / D ion implantation, followed by heat treatment. ^-Form S / D area.

As shown in (c), the photosensitive agent 18a is peeled off, and HTO (or HLD and LTO) for forming the sidewall spacers is deposited and etched back to form the sidewall spacers 19a, and then N ⁺ S using the photosensitive agent 18b. After the masking process for limiting the / D region is performed, N ⁺ S / D ion implantation is performed and heat treatment is performed to form the N ⁺ S / D region.

Finally, as shown in (d), the photoresist 18b is peeled off, and HTO (or HLD and LTO) for forming sidewall spacers is deposited and etched back to form sidewall spacers 19b, and then the photoresist 18c is used again. After performing a masking process to limit the P ⁺ S / D region, P ⁺ S / D ion implantation and heat treatment to form a P ⁺ S / D region.

However, the conventional process has the following disadvantages.

First, since the N ^- S / D region is formed before the N ⁺ S / D region, a junction is formed by injecting phosphorus (P) as N ^- ions, and then a junction is formed by implanting arsenic (As) as N ₊ ions. In this case, when the heat treatment process is performed to diffuse arsenic (As), the diffusion distance of the first implanted phosphorus (P) ion is longer than the diffusion distance of arsenic (As) ion, resulting in a deeper N ^- region junction. Lateral diffusion also occurs by about 70% of the junction length, which reduces the effective channel length.

Thus, a short channel effect occurs, and leakage current increases.

Second, N for forming LDD junction ^{-, N +, P -,} P + masking process should be performed four times for the ion injection, so this process is complicated.

Third, since the damage to the active region or the field region when the oxide layer is etched to form the sidewall spacer 19, the battery characteristics are deteriorated and the capacitance is reduced as the capacitor area is reduced as shown in FIG.

Disclosure of Invention The present invention has been made to solve the above problems, and an object of the present invention is to provide a method for obtaining the effect of shrinking a gate line through oxidation of a gate polysilicon and a shallow junction according to a self LDD. .

P wells 2, N wells 3, and field oxide films 4 are formed in predetermined portions on the substrate 1 during the self LDD junction transistor fabrication process according to the present invention, followed by an ion implantation process for adjusting the threshold voltage. Referring to the accompanying drawings 2 (a) to (f) process is as follows.

Like the surface bottom (a), the gate oxide film 5 and the polysilicon film (or polyside) 6 to be used as a gate, the HTO (or LTO, HLD) 7 serving as the gate capping, and the polysilicon film 6 The nitride film (8) and the HTO (7) are formed by sequentially forming a nitride film (8) for a masking role for selective oxidation and a capping role for ion implantation, and a masking process and an etching process using a photosensitive agent (9) to form a gate. The polysilicon film 6 and the gate oxide film 5 are patterned in a predetermined pattern.

In this case, the nitride film 8 may be formed without forming the cap gate oxide film 7.

Subsequently, the photoresist 9 is peeled off and the gate polysilicon film 6 is oxidized, so that the exposed side of the gate polysilicon film is oxidized to form an oxide film (not shown). Will be reduced by as much as

Subsequently, when the oxide film on the side of the gate polysilicon is removed, a gate pattern having a shape as shown in FIG. 2B is obtained.

Subsequently, N ⁺ S / D ion implantation is performed in a 0 ° tilt manner through a masking operation using the photosensitive agent 9a for N ⁺ S / D region limitation.

Next, as shown in (c), N ^- S / D ion implantation is performed in a tilt & rotation manner with the photosensitive agent 9a serving as the N ⁺ S / D region limitation mask intact.

Then, as shown in (d), the photosensitive agent 9a is peeled off and subjected to masking operation using the photosensitive agent 9b to limit the P ⁺ S / D region, and then P ⁺ S / D ion implantation is performed in a 0 ° tilting manner.

Then, P ^- S / D ion implantation is performed in a tilt and rotation manner with the P ⁺ S / D region limiting photosensitive agent 9b intact as shown in (e).

Finally, the process is completed by peeling off the nitride film 8 on the gate as shown in (f).

According to the process according to the present invention as described above has the following effects.

First, since N ⁺ S / D ion implantation is performed first and then N ^- S / D ion implantation is performed, the N ^- S / D junction formed in advance during the heat treatment process for forming the N ⁺ S / D region, as in the prior art, The disadvantage of deepening is eliminated, resulting in a shallow joint.

Therefore, there is an effect of preventing short channel generation and reducing leakage current.

Second, the process can be simplified because the N ^- S / D region limited masking process and the P ^- S / D region limited masking process are not performed separately.

Third, in forming the S / D region of the LDD structure, a high concentration of impurities (N ⁺ , P ⁺ ) are implanted using a gate as a mask, a spacer is formed on the sidewall of the gate, and a low concentration impurity (a gate and a sidewall spacer is used as a mask). N ^-, P ^-) a, but injection, in the present invention, the 0 ° tilt room during, or after subjected to ion implantation to the vertical forming a high concentration impurity region (N ⁺ S / D, P ⁺ S / D), a tilt-and- The gate < RTI ID = 0.0 > Tilt & Rotation < / RTI > i.e., vertical and inclined ion implantation are formed to form low concentration impurity regions N ^- S / D and P ^- S / D, thus eliminating the need for gate sidewall spacers.

Therefore, since the sidewall forming process is not performed, the active region or the field region is not damaged during the oxide film forming / etching process for forming the sidewall, and since there is no sidewall spacer, as shown in FIG. Since the portion has a terminal than the portion A smoothed by the gate sidewall spacer in FIG. 3 (a), the capacitor area is increased compared to FIG. 3 (b), thereby increasing capacitance.

Claims (4)

In the process of forming a P well 2, an N well 3, and a field oxide film 4 in a predetermined region on the substrate 1 and implanting ions for adjusting the threshold voltage, the gate oxide film 5 and the gate Forming a polysilicon film (6), a capgate oxide film (7), and a nitride film (8) for the oxidation of the selective gate polysilicon film in order, and then forming the films formed in a predetermined pattern through a masking / etching process; Forming a polysilicon oxide film on the exposed side of the gate polysilicon film by an oxidation process, removing the polysilicon oxide film formed, and performing a masking process defining a N ⁺ S / D region, followed by N ⁺ S / D ions. Performing implantation and N ^- S / D ion implantation in sequence, performing a masking process defining a P ⁺ S / D region, and then performing P ⁺ S / D ion implantation and P ^- S / D ion implantation in sequence, the nitride film Consisting of stripping off Self-LDD junction transistor manufacturing method as claimed. The method of claim 1, wherein only the nitride layer is deposited without forming a cap gate oxide layer on the gate polysilicon. The self LDD according to claim 1 or 2, wherein the N ⁺ and P ⁺ S / D ion implants are tilted at 0 ° and the N ^- and P ^- S / D ion implants are tilted and rotated. Method of manufacturing a junction transistor. The method of claim 1, wherein the cap gate oxide film is HTO, LTO, or HLD.

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