KR940022829A - MOS transistor manufacturing method - Google Patents

MOS transistor manufacturing method Download PDF

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Publication number
KR940022829A
KR940022829A KR1019930003646A KR930003646A KR940022829A KR 940022829 A KR940022829 A KR 940022829A KR 1019930003646 A KR1019930003646 A KR 1019930003646A KR 930003646 A KR930003646 A KR 930003646A KR 940022829 A KR940022829 A KR 940022829A
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South Korea
Prior art keywords
insulating film
forming
mos transistor
manufacturing
field oxide
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KR1019930003646A
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Korean (ko)
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KR100304974B1 (en
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김영기
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문정환
금성일렉트론 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 MOS 트랜지스터 제조방법에 관한 것으로, 종래의 트랜지스터에서 문제시되었던 숏 채널 효과에 의한 펀치-드루(punch-htrough) 및 핫 캐리어(hot ca -rrier)의 문제점을 해결하기 위해, 게이트 제1,2 측벽산화막(6,10 )을 이중으로 형성하고, LDD(11a) 구조와 필드산화막(2)의 하단에 채널 스톱층(3)을 형성하여 종래 기술의 문제점이었던, GIDL(Cate Induced Drain Leakage), 펀치드루, 핫 캐리어의 발생을 방지할 수 있다.The present invention relates to a method of manufacturing a MOS transistor, and to solve the problems of punch-htrough and hot carrier due to the short channel effect, which is a problem in the conventional transistor, the gate first, 2 sidewall oxide films 6 and 10 are formed in double, and the channel stop layer 3 is formed at the bottom of the LDD 11a structure and the field oxide film 2, which is a problem of Cat Induced Drain Leakage (GIDL). It is possible to prevent the occurrence of punch draw and hot carrier.

Description

모스(MOS) 트랜지스터 제조방법MOS transistor manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 트랜지스터 제조 공정 단면도이다.2 is a cross-sectional view of a transistor manufacturing process of the present invention.

Claims (10)

제1도전형 반도체 기판(1)상에 필드산화막(2)을 형성하고, 상기 필드산화막 (2)을 선택적으로 제거하여, 계단 형상의 활성영역을 형성하는 공정과, 전표면에 제1절연막(5)을 형성하고, 활성 영역중 게이트 영역으로 선택된 단차를 갖는 부분의 상측 제1절연막(5)을 제거하는 공정과, 상기 전표면에 절연막을 형성하고, 에치백하여 제1측벽절연막(6)을 형성하는 공정과, 노출된 전표면상에 제2절연막(7)과 제1도전체(8)를 차례로 형성하고 이들중 게이트 전극과 게이트 절연막으로 사용하기 위한 게이트 영역내의 부분을 제외한 나머지 부분을 제거하는 공정과, 잔존하는 제1도전체(8)를 마스크로 하여, 제2도전형 불순물을 제1도전형 반도체 기판(1)에 주입하여 저농도의 소오스/드레인 영역(11)을 형성하는 공정과, 잔존하는 제1도전체(8)와 제2절연막(7)의 측벽에 제2측벽절연막(10)을 형성하는 공정과, 제2측벽절연막(10)과 잔존하는 제1도전체(8)를 마스크로 하여 제2도전형 불순물을 제1도전형 반도체 기판(1)에 주입하여 고농도의 소오스/드레인 영역(12)을 형성하고, LDD(1 1a)를 형성하는 공정을 구비함을 특징으로 하는 MOS 트랜지스터 제조방법.Forming a field oxide film 2 on the first conductive semiconductor substrate 1, selectively removing the field oxide film 2 to form a stepped active region, and forming a first insulating film on the entire surface thereof. 5) and removing the upper first insulating film 5 of the portion having the step selected in the gate region of the active region; forming an insulating film on the entire surface and etching back to form the first side wall insulating film 6; Forming the second insulating film 7 and the first conductor 8 on the exposed entire surface, and removing the remaining portions except for the portion in the gate region for use as the gate electrode and the gate insulating film. Forming a low concentration source / drain region 11 by injecting the second conductive impurity into the first conductive semiconductor substrate 1 using the remaining first conductive material 8 as a mask; On the remaining sidewalls of the first conductor 8 and the second insulating film 7. The second conductive impurity is implanted into the first conductive semiconductor substrate 1 using the process of forming the second side insulating film 10 and the first conductive material 8 remaining with the second side insulating film 10 as a mask. Forming a high concentration source / drain region (12) and forming an LDD (1 1a). 제1항에 있어서, 필드산화막(2)은 4000~7500Å의 두께로 형성함을 특징으로 하는 MOS 트랜지스터 제조방법.The method of manufacturing a MOS transistor according to claim 1, wherein the field oxide film (2) is formed to a thickness of 4000 to 7500 kPa. 제1항에 있어서, 필드산화막(6)은 2000~4000Å의 두께로 형성함을 특징으로 하는 MOS 트랜지스터 제조방법.The method of manufacturing a MOS transistor according to claim 1, wherein the field oxide film (6) is formed to a thickness of 2000 to 4000 GPa. 제1항에 있어서, 제2절연막(7)은 800~1000℃의 온도범위에서 100~500Å의 두께로 열산화하여 형성하는 것을 특징으로 하는 MOS 트랜지스터 제조방법.The method of manufacturing a MOS transistor according to claim 1, wherein the second insulating film (7) is formed by thermal oxidation to a thickness of 100 to 500 kPa in a temperature range of 800 to 1000 ° C. 제1항에 있어서, 제1도전체(8)은 2000~5000Å의 두께로 형성함을 특징으로 하는 MOS 트랜지스터 제조방법.2. The method of claim 1 wherein the first conductor (8) is formed to a thickness of 2000 to 5000 microns. 제1항에 있어서, LDD(11a)을 형성하기 위한 저농도의 소오스/드레인 영역의 제2도전형 불순물 주입농도는 0.5×3×1013atom/㎠ 으로 함을 특징으로 하는 MOS 트랜지스터 제조방법.The method of claim 1, wherein the second conductivity type impurity implantation concentration of the low concentration source / drain region for forming the LDD (11a) is 0.5 x 3 x 10 13 atom / cm 2. 제1항에 있어서, 고농도의 소오스/드레인 영역(12)의 농도는 2~6×1015atom/㎠ 으로 형성함을 특징으로 하는 MOS 트랜지스터 제조방법.The method of claim 1, wherein the concentration of the high concentration source / drain region (12) is 2 to 6 x 10 15 atoms / cm 2. 제1항에 있어서, 게이트(8a)의 측벽절연막(6,10)을 이중으로 형성함을 특징으로 하는 MOS 트랜지스터 제조방법.2. A method according to claim 1, wherein the sidewall insulating films (6, 10) of the gate (8a) are formed in duplicate. 제1항에 있어서, 활성영역을 필드산화막(2)의 일부분에까지 확장하여 단차를 갖는 부분을 포함하여 형성함을 특징으로 하는 MOS 트랜지스터 제조방법.The method of manufacturing a MOS transistor according to claim 1, wherein the active region is extended to a portion of the field oxide film (2) to include a portion having a step. 제1항에 있어서, LDD(11a)을 형성하기 위해 소오스/드레인 영역(11)에 불순물 이온 주입시 주입 각도를 경사지게 하여 주입함을 특징으로 하는 MOS 트랜지스터 제조방법.The method of manufacturing a MOS transistor according to claim 1, wherein the implant angle is inclined when implanting impurity ions into the source / drain region (11) to form the LDD (11a). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930003646A 1993-03-11 1993-03-11 Method for manufacturing mos transistor KR100304974B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100248200B1 (en) * 1996-12-30 2000-03-15 김영환 Soi semiconductor device

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* Cited by examiner, † Cited by third party
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JP2006301955A (en) 2005-04-20 2006-11-02 Quants Research Kk Stock information providing device, stock information providing method, and stock information providing program

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JPS6366967A (en) * 1986-09-08 1988-03-25 Hitachi Ltd Semiconductor device and manufacture thereof
KR930004301B1 (en) * 1990-12-18 1993-05-22 금성일렉트론 주식회사 Making method of transistor of short channel effect structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100248200B1 (en) * 1996-12-30 2000-03-15 김영환 Soi semiconductor device

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