KR100259362B1 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- KR100259362B1 KR100259362B1 KR1019980007638A KR19980007638A KR100259362B1 KR 100259362 B1 KR100259362 B1 KR 100259362B1 KR 1019980007638 A KR1019980007638 A KR 1019980007638A KR 19980007638 A KR19980007638 A KR 19980007638A KR 100259362 B1 KR100259362 B1 KR 100259362B1
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- South Korea
- Prior art keywords
- gate
- well
- oxide film
- forming
- etched
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000000034 method Methods 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000012535 impurity Substances 0.000 claims abstract description 13
- 150000002500 ions Chemical class 0.000 claims abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 13
- 229920005591 polysilicon Polymers 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 8
- 238000000206 photolithography Methods 0.000 claims description 9
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims description 6
- 229910052742 iron Inorganic materials 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 5
- 125000006850 spacer group Chemical group 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 18
- 238000007796 conventional method Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 반도체소자의 고집적화에 따라 게이트 길이가 축소됨으로써 야기되는 단채널효과(short channel effect)를 방지하기에 적당하도록 한 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device suitable for preventing short channel effects caused by shortening of gate length due to high integration of the semiconductor device.
종래 반도체소자의 제조방법을 첨부한 도면을 참조하여 설명하면 다음과 같다.Referring to the accompanying drawings, a conventional method for manufacturing a semiconductor device is as follows.
도1a 내지 도1e는 종래 반도체소자의 제조방법을 보인 수순단면도로서, 이에 도시한 바와같이 반도체기판(1)상에 웰(2)을 형성한 후, 그 웰(2)의 상부에 게이트산화막(3)을 형성하는 단계(도1a)와; 그 게이트산화막(3)의 상부에 도핑된 폴리실리콘(4)과 캡(cap) 산화막(5)을 순차적으로 증착하는 단계(도1b)와; 그 산화막(5)의 상부에 포토레지스트(PR1)를 도포하고 일부를 노광 및 현상한 후, 노출된 산화막(5), 폴리실리콘(4) 및 게이트산화막(3)을 순차적으로 식각하여 게이트를 형성하는 단계(도1c)와; 포토레지스트(PR1)를 제거하고, 그 게이트를 마스크로 반도체기판(1)상에 저농도의 불순물이온을 주입하여 저농도 소스/드레인(6)을 형성한 후, 반도체기판(1)의 상부전면에 산화막(7)을 형성하는 단계(도1d)와; 그 산화막(7)을 선택적으로 식각하여 게이트의 측면에 측벽(8)을 형성한 후, 그 게이트 및 측벽(8)을 마스크로 반도체기판(1)상에 고농도의 불순물이온을 주입하여 고농도 소스/드레인(9)을 형성하는 단계(도1e)로 이루어진다. 이하, 상기한 바와같은 종래 반도체소자의 제조방법을 좀더 상세히 설명한다.1A through 1E are cross-sectional views showing a conventional method of manufacturing a semiconductor device. As shown in FIG. 1A to 1E, after forming a well 2 on a semiconductor substrate 1, a gate oxide film ( 3) forming (FIG. 1A); Sequentially depositing the doped polysilicon 4 and the cap oxide film 5 on the gate oxide film 3 (FIG. 1B); After applying photoresist PR1 on the oxide film 5, exposing and developing part thereof, the exposed oxide film 5, polysilicon 4 and gate oxide film 3 are sequentially etched to form a gate. (Step 1c); After removing the photoresist PR1 and injecting a low concentration of impurity ions onto the semiconductor substrate 1 using the gate as a mask to form a low concentration source / drain 6, an oxide film is formed on the upper surface of the semiconductor substrate 1. (7) forming (FIG. 1D); The oxide film 7 is selectively etched to form sidewalls 8 on the side of the gate, and then a high concentration of impurity ions are implanted onto the semiconductor substrate 1 using the gate and sidewalls 8 as masks. The drain 9 is formed (Fig. 1E). Hereinafter, a method of manufacturing a conventional semiconductor device as described above will be described in more detail.
먼저, 도1a에 도시한 바와같이 반도체기판(1)상에 웰(2)을 형성한 후, 그 웰(2)의 상부에 게이트산화막(3)을 형성한다. 이때, 웰(2)은 반도체기판(1)의 표면을 산화한 후, 불순물 이온을 주입하여 이온주입에 의한 손상을 방지하고, 열처리공정을 통해 확산하여 형성한다.First, as shown in FIG. 1A, the well 2 is formed on the semiconductor substrate 1, and then the gate oxide film 3 is formed on the well 2. At this time, the well 2 is formed by oxidizing the surface of the semiconductor substrate 1, implanting impurity ions to prevent damage due to ion implantation, and diffusing them through a heat treatment process.
그리고, 도1b에 도시한 바와같이 게이트산화막(3)의 상부에 폴리실리콘(4)과 산화막(5)을 순차적으로 증착한다.As shown in FIG. 1B, the polysilicon 4 and the oxide film 5 are sequentially deposited on the gate oxide film 3.
그리고, 도1c에 도시한 바와같이 산화막(5)의 상부에 포토레지스트(PR1)를 도포하고 일부를 노광 및 현상한 후, 노출된 산화막(5), 폴리실리콘(4) 및 게이트산화막(3)을 순차적으로 식각하여 게이트를 형성한다. 이때, 포토레지스트(PR1)를 이용한 게이트의 형성은 통상의 사진식각공정으로 포토레지스트(PR1)를 통해 게이트영역을 제외한 영역에 증착된 산화막(5), 폴리실리콘(4) 및 게이트산화막(3)을 노출시키고, 이를 순차적으로 식각하여 웰(2)을 노출시킨다.Then, as shown in FIG. 1C, after the photoresist PR1 is applied on the oxide film 5, a part of the light is exposed and developed, the exposed oxide film 5, the polysilicon 4, and the gate oxide film 3 are exposed. Are sequentially etched to form a gate. At this time, the formation of the gate using the photoresist PR1 is a conventional photolithography process, and the oxide film 5, the polysilicon 4, and the gate oxide film 3 deposited in the region except the gate region through the photoresist PR1. Are exposed, and they are sequentially etched to expose the wells 2.
그리고, 도1d에 도시한 바와같이 포토레지스트(PR1)를 제거하고, 그 게이트를 마스크로 반도체기판(1)상에 저농도의 불순물이온을 주입하여 저농도 소스/드레인(6)을 형성한 후, 반도체기판(1)의 상부전면에 산화막(7)을 형성한다.Then, as shown in Fig. 1D, the photoresist PR1 is removed, and a low concentration source / drain 6 is formed by implanting low concentration impurity ions onto the semiconductor substrate 1 using the gate as a mask. An oxide film 7 is formed on the entire upper surface of the substrate 1.
그리고, 도1e에 도시한 바와같이 산화막(7)을 선택적으로 식각하여 게이트의 측면에 측벽(8)을 형성한 후, 그 게이트 및 측벽(8)을 마스크로 반도체기판(1)상에 고농도의 불순물이온을 주입하여 고농도 소스/드레인(9)을 형성한다.Then, as shown in FIG. 1E, the oxide film 7 is selectively etched to form sidewalls 8 on the side surfaces of the gate, and then the gate and sidewalls 8 are masked on the semiconductor substrate 1 with high concentration. Impurity ions are implanted to form a high concentration source / drain 9.
이때, 측벽(8)을 통해 저농도 및 고농도 소스/드레인(6,9)을 형성하는 이유는 엘디디(lightly doped drain : LDD)구조를 형성하여 단채널에 의한 영향으로 펀치쓰루(punch through)가 발생하는 것을 최대한 억제하기 위해서이다.At this time, the reason for forming the low concentration and high concentration source / drain (6,9) through the side wall (8) is to form a lightly doped drain (LDD) structure to punch through (punch through) due to the influence of the short channel This is to suppress the occurrence as much as possible.
그러나, 상기한 바와같은 종래 반도체소자의 제조방법은 반도체소자가 점점 고집적화됨에 따라 게이트의 임계치수(critical dimension : CD)가 작아져 게이트산화막의 하부에 형성되는 채널의 길이가 극히 짧아짐으로써, 단채널효과에 의해 반도체소자의 신뢰성이 저하되는 문제점이 있었다.However, in the conventional method of manufacturing a semiconductor device as described above, as the semiconductor device becomes more and more integrated, the critical dimension (CD) of the gate becomes smaller and the length of the channel formed under the gate oxide film becomes extremely short, thereby shortening the channel. There is a problem that the reliability of the semiconductor device is lowered by the effect.
본 발명은 상기한 바와같은 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 게이트의 임계치수에는 변화가 없으면서도 채널의 길이를 증가시킬수 있는 반도체소자의 제조방법을 제공하는데 있다.The present invention has been made to solve the above problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can increase the length of the channel without changing the threshold of the gate.
도1은 종래 반도체소자의 제조방법을 보인 수순단면도.1 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device.
도2는 본 발명의 일 실시예를 보인 수순단면도.Figure 2 is a cross-sectional view showing an embodiment of the present invention.
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
11:반도체기판 12:웰11: semiconductor substrate 12: well
13,16,18:산화막 14:게이트산화막13,16,18 oxide film 14 gate oxide film
15:폴리실리콘 17:저농도 소스/드레인15: polysilicon 17: low concentration source / drain
19:측벽 20:고농도 소스/드레인19: side wall 20: high concentration source / drain
상기한 바와같은 본 발명의 목적은 반도체기판의 상부에 웰을 형성한 후, 1차 사진식각공정을 통해 웰의 일부를 소정깊이로 식각하는 단계와; 상기 웰의 식각된 영역에 제1산화막을 채운 후, 2차 사진식각공정을 통해 1차식각되지 않은 웰의 상부를 1차 사진식각공정과 동일한 깊이로 식각한 후, 제1산화막을 제거하여 웰의 상부를 요철(凹凸)형태로 형성하는 단계와; 상기 요철형태의 웰 상부에 순차적으로 게이트산화막, 폴리실리콘, 제2산화막을 형성한 후, 3차 사진식각공정을 통해 철(凸)형태의 웰 상부에 게이트를 형성하는 단계와; 상기 게이트가 형성된 반도체기판상에 저농도의 불순물이온을 주입한 후, 게이트측벽을 형성하고, 고농도의 불순물이온을 주입하여 저농도 및 고농도 소스/드레인의 엘디디구조를 형성하는 단계로 이루어짐으로써 달성되는 것으로, 본 발명에 의한 반도체소자의 제조방법을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.An object of the present invention as described above is to form a well on the upper portion of the semiconductor substrate, and then etching a portion of the well to a predetermined depth through the first photolithography process; After filling the first oxide layer in the etched region of the well, the upper portion of the well that is not primary etched through the secondary photolithography process is etched to the same depth as the primary photolithography process, and then the first oxide layer is removed. Forming an upper portion of the upper portion in an uneven shape; Forming a gate oxide film, a polysilicon, and a second oxide film sequentially on the wells of the uneven shape, and then forming a gate on the wells of the iron type through a third photolithography process; It is achieved by injecting a low concentration of impurity ions onto the gate formed semiconductor substrate, forming a gate sidewall, and injecting a high concentration of impurity ions to form an LED structure of low concentration and high concentration source / drain. When described in detail with reference to the accompanying drawings, a method for manufacturing a semiconductor device according to the present invention.
도2a 내지 도2j는 본 발명의 일 실시예를 보인 수순단면도로서, 이에 도시한 바와같이 반도체기판(11)의 상부에 웰(12)을 형성하고, 그 웰(12)의 상부에 포토레지스트(PR1)를 도포한 후, 노광 및 현상하여 웰(12)의 일부를 노출시키는 단계(도2a)와; 그 노출된 웰(12)의 일부를 소정깊이로 1차 식각한 후, 포토레지스트(PR1)를 제거하는 단계(도2b)와; 웰(12)의 식각된 영역에 산화막(13)을 채우는 단계(도2c)와; 그 산화막(13) 및 웰(12)의 상부에 포토레지스트(PR2)를 도포한 후, 노광 및 현상하여 1차 식각되지 않은 영역의 웰(12)을 노출시키는 단계(도2d)와; 그 노출된 웰(12)을 1차 식각과 동일한 깊이로 2차 식각한 후, 포토레지스트(PR2)를 제거하여 웰(12)의 상부를 요철형태로 형성하는 단계(도2e)와; 그 웰(12)의 1차 식각된 영역에 채워진 산화막(13)을 제거하여 웰(12)을 노출시키는 단계(도2f)와; 그 웰(12)의 상부에 순차적으로 게이트산화막(14), 폴리실리콘(15) 및 산화막(16)을 형성하는 단계(도2g)와; 그 산화막(16)의 상부에 포토레지스트(PR3)를 도포한 후, 노광 및 현상하여 웰(12)상부 철(凸)형태의 영역을 정의하고, 노출된 산화막(16), 폴리실리콘(15) 및 게이트산화막(14)을 식각하여 게이트를 형성하는 단계(도2h)와; 그 포토레지스트(PR3)를 제거하고, 게이트를 마스크로 반도체기판(11)상에 저농도의 불순물이온을 주입하여 저농도 소스/드레인(17)을 형성한 후, 반도체기판(11)의 상부전면에 산화막(18)을 형성하는 단계(도2i)와; 그 산화막(18)을 선택적으로 식각하여 게이트의 측면에 측벽(19)을 형성한 후, 그 게이트 및 측벽(19)을 마스크로 반도체기판(11)상에 고농도의 불순물이온을 주입하여 고농도 소스/드레인(20)을 형성하는 단계(도2j)로 이루어진다. 이하, 상기한 바와같은 본 발명의 일 실시예를 좀더 상세히 설명한다.2A to 2J are cross-sectional views showing an embodiment of the present invention. As shown therein, a well 12 is formed on an upper portion of a semiconductor substrate 11 and a photoresist is formed on the well 12. After applying PR1), exposing and developing to expose a portion of well 12 (FIG. 2A); First etching a part of the exposed well 12 to a predetermined depth, and then removing the photoresist PR1 (FIG. 2B); Filling the oxide film 13 in the etched region of the well 12 (FIG. 2C); Applying photoresist PR2 on top of the oxide film 13 and the well 12, and then exposing and developing to expose the well 12 in the unetched region (FIG. 2D); Etching the exposed well 12 to the same depth as the primary etching, and then removing the photoresist PR2 to form an upper portion of the well 12 in an uneven shape (FIG. 2E); Removing the oxide film 13 filled in the primary etched region of the well 12 to expose the well 12 (FIG. 2F); Sequentially forming a gate oxide film 14, a polysilicon 15, and an oxide film 16 on the well 12 (Fig. 2G); After photoresist PR3 is applied on the oxide film 16, it is exposed and developed to define an iron-shaped region on the well 12, and the exposed oxide film 16 and polysilicon 15 are defined. And etching the gate oxide film 14 to form a gate (FIG. 2H); The photoresist PR3 is removed and a low concentration source / drain 17 is formed by implanting low concentration impurity ions onto the semiconductor substrate 11 using the gate as a mask, and then an oxide film is formed on the upper surface of the semiconductor substrate 11. Forming 18 (FIG. 2I); The oxide film 18 is selectively etched to form sidewalls 19 on the side of the gate, and then a high concentration of impurity ions are implanted onto the semiconductor substrate 11 using the gate and sidewalls 19 as masks. Forming a drain 20 (FIG. 2J). Hereinafter, an embodiment of the present invention as described above will be described in more detail.
먼저, 도2a에 도시한 바와같이 반도체기판(11)의 상부에 웰(12)을 형성하고, 그 웰(12)의 상부에 포토레지스트(PR1)를 도포한 후, 노광 및 현상하여 웰(12)의 일부를 노출시킨다. 이때, 웰(12)은 종래와 동일하게 반도체기판(11)의 표면을 산화한 후, 불순물 이온을 주입하고, 열처리공정을 통해 확산하여 형성한다.First, as shown in FIG. 2A, the well 12 is formed on the semiconductor substrate 11, the photoresist PR1 is applied on the well 12, and then exposed and developed to expose the well 12. Part of the At this time, the well 12 is formed by oxidizing the surface of the semiconductor substrate 11 as in the prior art, implanting impurity ions, and diffusing them through a heat treatment process.
그리고, 도2b에 도시한 바와같이 노출된 웰(12)의 일부를 소정깊이로 1차 식각한 후, 포토레지스트(PR1)를 제거한다.As shown in FIG. 2B, a part of the exposed well 12 is first etched to a predetermined depth, and then the photoresist PR1 is removed.
그리고, 도2c에 도시한 바와같이 웰(12)의 식각된 영역에 산화막(13)을 채운다. 이때, 산화막(13)은 웰(12)의 상부전면에 증착한 후, 평탄화를 위한 에치-백(etch back)을 수행한다.As shown in FIG. 2C, the oxide film 13 is filled in the etched region of the well 12. At this time, the oxide film 13 is deposited on the upper front surface of the well 12 and then etched back for planarization.
그리고, 도2d에 도시한 바와같이 산화막(13) 및 웰(12)의 상부에 포토레지스트(PR2)를 도포한 후, 노광 및 현상하여 1차 식각되지 않은 영역의 웰(12)을 노출시킨다.As shown in FIG. 2D, the photoresist PR2 is coated on the oxide film 13 and the wells 12, and then exposed and developed to expose the wells 12 in the unetched region.
그리고, 도2e에 도시한 바와같이 노출된 웰(12)을 1차 식각과 동일한 깊이로 2차 식각한 후, 포토레지스트(PR2)를 제거하여 웰(12)의 상부를 요철형태로 형성한다. 이때, 웰(12)의 상부는 1차식각된 영역과 2차식각된 영역의 경계에 철(凸)형태가 형성된다.As shown in FIG. 2E, the exposed well 12 is secondly etched to the same depth as the first etching, and then the photoresist PR2 is removed to form an upper portion of the well 12 in an uneven form. At this time, the upper portion of the well 12 is formed in the form of iron on the boundary between the primary etched region and the secondary etched region.
그리고, 도2f에 도시한 바와같이 산화막(16)의 상부에 포토레지스트(PR3)를 도포한 후, 노광 및 현상하여 웰(12)상부 철(凸)형태의 영역을 정의하고, 노출된 산화막(16), 폴리실리콘(15) 및 게이트산화막(14)을 식각하여 게이트를 형성한다.Then, as shown in FIG. 2F, after the photoresist PR3 is applied on the oxide film 16, the photoresist PR3 is exposed and developed to define an iron-shaped region on the well 12, and the exposed oxide film ( 16), the polysilicon 15 and the gate oxide film 14 are etched to form a gate.
이후, 도2g 내지 도2j에 도시한 엘디디구조를 형성하기 위한 공정은 종래 도1d 및 도1e에 도시한 바와 동일하므로 생략한다.Thereafter, the process for forming the LED structure shown in Figs. 2G to 2J is the same as that shown in Figs. 1D and 1E, and thus will be omitted.
상기한 바와같은 본 발명에 의한 반도체소자의 제조방법은 동일한 임계치수의 게이트에서 채널의 길이를 증가시킴으로써, 고집적화에 따른 단채널효과를 최대한 억제하여 반도체소자의 신뢰성을 향상시킬 수 있는 효과가 있다.The method of manufacturing a semiconductor device according to the present invention as described above has the effect of increasing the length of the channel in the gate of the same critical dimension, thereby improving the reliability of the semiconductor device by suppressing the short channel effect due to the high integration.
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