KR0172552B1 - Semiconductor device fabrication method - Google Patents
Semiconductor device fabrication method Download PDFInfo
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- KR0172552B1 KR0172552B1 KR1019950050440A KR19950050440A KR0172552B1 KR 0172552 B1 KR0172552 B1 KR 0172552B1 KR 1019950050440 A KR1019950050440 A KR 1019950050440A KR 19950050440 A KR19950050440 A KR 19950050440A KR 0172552 B1 KR0172552 B1 KR 0172552B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
Abstract
본 발명은 반도체소자의 제조방법에 관한 것으로서, 전하저장전극 콘택홀을 통하여 소자분리 산화막의 가장자리 부분 일부가 제거되어 노출되는 반도체기판을 열산화시켜 희생산화막을 형성하되, 소오스/드레인 접합의 일부도 함께 열산화되어 희생산화막의 두께차가 나도록하고, 이온주입을 통하여 누설전류 방지용 접합을 형성하고, 희생산화막을 제거하여 전하저장전극콘택을 형성하였으므로, 소오스/드레인 접합과 게이트전극과의 중첩 정도가 변화되지 않아 숏채널 현상이 감소되고, 펀치쓰루가 방지되며, 누설전류 방지용 접합의 형성으로 누설전류가 감소되어 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있다.The present invention relates to a method for fabricating a semiconductor device, wherein a portion of the edge of the isolation oxide film is removed through thermal charge oxidation to form a sacrificial oxide film by thermally oxidizing the exposed semiconductor substrate. Thermal oxidation was performed together to make the thickness difference of the sacrificial oxide film, the junction for preventing the leakage current was formed through ion implantation, and the charge storage electrode contact was formed by removing the sacrificial oxide film. Thus, the degree of overlap between the source / drain junction and the gate electrode is changed. Therefore, short channel phenomenon is reduced, punch-through is prevented, and leakage current is reduced by forming a leakage current preventing junction, thereby improving process yield and device operation reliability.
Description
제1a도 내지 제1c도는 종래 기술의 일실시예에 따른 반도체소자의 제조 공정도.1a to 1c is a manufacturing process diagram of a semiconductor device according to an embodiment of the prior art.
제2도는 종래 기술의 다른 실시예에 따른 반도체소자의 단면도.2 is a cross-sectional view of a semiconductor device according to another embodiment of the prior art.
제3a도 내지 제3d도는 본발명에 따른 반도체소자의 제조공정도.3A to 3D are manufacturing process diagrams of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반도체기판 2 : 소자분리 산화막1: semiconductor substrate 2: device isolation oxide film
3 : 게이트 산화막 4 : 게이트전극3: gate oxide film 4: gate electrode
5 : 소오스/드레인 접합 6 : 산화막 스페이서5: source / drain junction 6: oxide film spacer
7 : 층간절연막 8 : 콘택홀7 interlayer insulating film 8 contact hole
9 : 누설전류 방지용 접합 10 : 희생산화막9: junction for preventing leakage current 10: sacrificial oxide film
본 발명은 반도체 소자의 제조방법에 관한 것으로서, 특히 초고집적 반도체 소자의 전하저장전극용 콘택홀을 형성한 후, 희생산화막을 이용한 이온 주입을 통하여 누설 방지용 접합을 형성하므로써 셀 트랜지스터(Cell Transistor)의 특성에 영향을 주지 않으면서 콘택홀의 누설 전류를 감소시킬 수 있어 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, a contact hole for a charge storage electrode of an ultra-high density semiconductor device is formed, and then a junction for preventing leakage is formed by ion implantation using a sacrificial oxide film. The present invention relates to a method of manufacturing a semiconductor device capable of reducing leakage current of a contact hole without affecting characteristics, thereby improving process yield and reliability of device operation.
반도체 장치의 고집적화는 미세 패턴 형성기술의 발전에 큰 영향을 받고 있다. 특히 감광막패턴은 반도체 장치의 제조 공정중에서 식각 또는 이온 주입 공정 등의 마스크로 매우 폭 넓게 사용되고 있다.High integration of semiconductor devices is greatly influenced by the development of fine pattern formation technology. In particular, the photoresist pattern is widely used as a mask for etching or ion implantation in the semiconductor device manufacturing process.
따라서 반도체 소자의 고집적화를 위해서는 감광막 패턴의 미세화가 필수 요건인데, 상기 감광막패턴의 분해능은 축소노광장치의 광원의 파장 및 공정변수에 비례하고, 축소노광장치의 렌즈구경(Numerical Aperture; NA)에 반비례한다.Therefore, miniaturization of the photoresist pattern is essential for high integration of semiconductor devices. The resolution of the photoresist pattern is proportional to the wavelength and process variables of the light source of the reduction exposure apparatus, and inversely proportional to the lens aperture of the reduction exposure apparatus. do.
여기서 상기 축소노광장치의 광분해능을 향상시키기 위하여 광원의 파장을 감소시키게 되며, 예를들어 파장이 436 및 365㎚인 G-라인 및 i-라인 축소노광장치는 공정 분해능이 각각 약 0.7, 0.5㎛정도가 한계이다.Here, the wavelength of the light source is reduced in order to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of about 0.7 and 0.5 µm, respectively. Degree is the limit.
따라서 0.5㎛ 이하의 미세 패턴을 형성하기 위해 파장이 적은 원자외선(Deep Ultra Violet), 예를들어 파장이 248㎚ KrF 레이저나 193㎚인 ArF 레이저를 광원으로 사용하는 축소노광장치를 이용한다.Therefore, in order to form a fine pattern of 0.5 mu m or less, a reduced exposure apparatus using a deep ultraviolet light having a small wavelength, for example, a 248 nm KrF laser or an ArF laser having a wavelength of 193 nm, is used as a light source.
일반적으로 반도체 소자는 집적도가 증가함에 따라 단위셀을 구성하는 면적이 감소되므로 실리콘 기판에 형성되는 콘택의 크기 및 전도체 사이의 간격이 좁아지게 된다. 또한 소자분리 산화막 형성시 발생하는 버즈 빅(Bird's Beak)에 의한 활성 영역의 감소도 심각한 수준이 되어 콘택을 형성하기 위하여 제조 공정에서 공정여유도가 감소된다.In general, since the area of a semiconductor cell decreases as the degree of integration increases, the size of the contact formed on the silicon substrate and the distance between the conductors are narrowed. In addition, the reduction of the active area caused by Bird's Beak, which occurs when the device isolation oxide film is formed, is also a serious level, and the process margin is reduced in the manufacturing process to form a contact.
따라서 256M DRAM 이상의 초 고집적도를 갖는 반도체 소자에 있어서는 실리콘 기판에 콘택을 형성할 경우, 특히 활성 영역의 가장자리에 형성되는 전하저장전극 콘택의 경우에는 콘택홀 형성시 소자분리 산화막의 가장자리 부분이 함께 식각되므로 콘택에서 실리콘 기판으로 누설전류가 흐르게 된다.Therefore, in the case of a semiconductor device having an ultra-high density of 256M DRAM or more, when forming a contact on a silicon substrate, particularly in the case of a charge storage electrode contact formed at the edge of the active region, the edge of the isolation oxide layer is etched together when forming the contact hole. Therefore, leakage current flows from the contact to the silicon substrate.
이와 같이 콘택 형성시 Field 산화막이 함께 식각되므로써 발생하는 실리콘 기판의 노출에 의한 누설전류를 막기 위한 방법으로, 종래에는 콘택홀을 형성한 후 이온 주입을 통한 누설 전류 방지용 접합을 형성하는 방법을 사용하여 누설 전류를 제어하였다.As a method for preventing leakage current due to the exposure of the silicon substrate generated by the etching of the field oxide film at the time of contact formation, a method of forming a contact hole for preventing leakage current through ion implantation is conventionally used. Leakage current was controlled.
제1a도 내지 제1c도는 종래 기술에 따른 반도체소자의 제조 공정도로서, 집적도가 낮은 반도체소자의 예이다.1A to 1C are manufacturing process diagrams of a semiconductor device according to the prior art, which is an example of a semiconductor device having a low integration degree.
먼저, 실리콘 반도체기판(1)의 일측에 소자간의 분리를 위하여 소자분리 산화막(2)을 형성하고, 게이트 산화막(3)과 다결정실리콘층 패턴으로 된 게이트전극(4)을 형성한 후, 상기 게이트전극(4) 양측의 반도체기판(1)에 이온 주입 방법으로 소오스/드레인 접합(5)을 형성한다. 이때 상기 소오스/드레인 접합(5)의 엘.디.디(Lightly Doped Drain; LDD) 접합을 형성하기 위해 산화막이나 질화막 등의 절연물질을 이용하여 스페이서(6)를 형성하기도 한다.(제1a도 참조).First, a device isolation oxide film 2 is formed on one side of the silicon semiconductor substrate 1 to separate the devices, and a gate oxide film 3 and a gate electrode 4 having a polysilicon layer pattern are formed. The source / drain junction 5 is formed in the semiconductor substrate 1 on both sides of the electrode 4 by an ion implantation method. At this time, the spacer 6 may be formed using an insulating material such as an oxide film or a nitride film to form an L. D. junction of the source / drain junction 5 (FIG. 1A). Reference).
그다음 상기 구조의 전표면에 층간절연막(7)을 형성한 후, 상기 소오스/드레인 접합(5)에서 전하저장전극 콘택으로 예정되어 있는 부분상측의 층간절연막(7)을 제거하여 전하저장전극 콘택홀(8)을 형성한다. 이때 소오스/드레인 접합(5)과 게이트 전극(4)은 A 만큼 어버랩되어 있으며, 콘택홀(8)과 게이트전극(4)과는 B 만큼 떨어져 있다. 또한 상기 콘택홀(8) 형성시 소자분리 산화막(2)의 일부분이 식각되어 콘택홀(8)의 일부분(21)은 반도체기판(1)이 노출되며, 노출된 반도체기판(1)을 통하여 누설 전류가 흐르게 된다. (제1b도 참조).Then, the interlayer insulating film 7 is formed on the entire surface of the structure, and then the interlayer insulating film 7 on the portion scheduled as the charge storage electrode contact is removed from the source / drain junction 5 so as to form the charge storage electrode contact hole. (8) is formed. At this time, the source / drain junction 5 and the gate electrode 4 are overlapped by A, and the contact hole 8 and the gate electrode 4 are separated by B. In addition, when the contact hole 8 is formed, a portion of the isolation oxide layer 2 is etched so that a portion 21 of the contact hole 8 is exposed to the semiconductor substrate 1 and leaks through the exposed semiconductor substrate 1. Current will flow. (See also Figure 1b).
그후, 상기 콘택홀(8)을 통하여 노출된 반도체기판(1)을 통한 누설 전류를 방지하기 위해 이온 주입의 방법으로 콘택홀(8)의 하부에 누설 전류 방지용 접합(9)을 형성한다. (제1c도 참조).Thereafter, in order to prevent leakage current through the semiconductor substrate 1 exposed through the contact hole 8, a leakage current preventing junction 9 is formed in the lower portion of the contact hole 8 by a method of ion implantation. (See also Figure 1c).
상기와 같은 집적도가 낮아 공정 여유가 있는 반도체소자에서는 누설전류 방지용 접합(9)은 게이트전극(4)과는 중첩되지 않으며, 소오스/드레인 접합(5)과 게이트전극(4)과의 중첩 정도 A는 변하지 않는다.In a semiconductor device having a low integration degree and a process margin, the leakage current preventing junction 9 does not overlap the gate electrode 4, but the overlapping degree A between the source / drain junction 5 and the gate electrode 4. Does not change.
그러나 제2도에 도시되어 있는 바와 같은, 고집적화된 반도체 소자에서는 콘택홀(8)과 게이트 전극(4)간의 간격이 C(＜B)로 줄어들게 되어 누설 전류 방지용 접합(9)과 게이트 전극(4)과의 중첩 정도가 D(＞A)로 늘어나게 되며, 이는 채널 길이의 감소를 가져오게 되어 숏 채널(Short Channel) 효과를 증가시고, 펀치쓰루(Punchthrough)가 발생하는 등의 소자 동작의 신뢰성을 떨어뜨리는 문제점이 있다.However, in the highly integrated semiconductor device as shown in FIG. 2, the distance between the contact hole 8 and the gate electrode 4 is reduced to C (<B), so that the leakage current preventing junction 9 and the gate electrode 4 are reduced. ) Overlaps with D (> A), which reduces the channel length, increases the short channel effect, and improves the reliability of device operation such as punchthrough. There is a problem to drop.
본발명은 상기와 같은 문제점을 해결하기 위한 것으로서, 본발명의 목적은 소자분리 산화막의 가장자리 부분 일부가 콘택홀 형성시 제거되고, 그 하부의 노출되는 반도체기판상에 희생산화막을 형성한 후, 누설전류 방지용 접합을 이온주입 방법으로 형성하여 소자의 누설전류를 감소시키고, 펀치쓰루를 방지하여 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 반도체소자의 제조방법을 제공함에 있다.The present invention is to solve the above problems, the object of the present invention is to remove a portion of the edge portion of the isolation oxide film when forming a contact hole, the sacrificial oxide film formed on the exposed semiconductor substrate below the leakage, The present invention provides a method of manufacturing a semiconductor device capable of forming a current preventing junction by an ion implantation method to reduce the leakage current of the device and to prevent punch-through to improve process yield and reliability of device operation.
상기와 같은 목적을 달성하기 위한 본발명에 따른 반도체소자의 제조방법의 특징은, 반도체기판의 일측에 소자분리 산화막을 형성하는 공정과, 상기 구조의 전표면에 게이트 산화막을 형성하는 공정과, 상기 게이트산화막상에 게이트전극을 형성하는 공정과, 상기 게이트전극 양측의 반도체기판에 소오스/드레인 접합을 형성하는 공정과, 상기 구조의 전표면에 층간절연막을 형성하는 공정과, 상기 소오스/드레인 접합에서 전하저장전극 콘택으로 예정되어 있는 부분상측의 층간절연막을 제거하여 전하저장전극용 콘택홀을 형성하되, 상기 콘택홀을 통하여 노출되는 소자분리 산화막의 가장자리 부분을 함께 제거하여 반도체기판을 노출시키는 공정과, 상기 콘택홀을 통하여 노출되어있는 반도체기판상에 희생산화막을 형성하는 공정과, 상기 희생산화막 하부의 반도체기판에 누설전류 방지용 접합을 형성하는 공정과, 상기 희생산화막을 제거하는 공정을 구비함에 있다.Features of the semiconductor device manufacturing method according to the present invention for achieving the above object is the step of forming a device isolation oxide film on one side of the semiconductor substrate, the step of forming a gate oxide film on the entire surface of the structure, and Forming a gate electrode on the gate oxide film, forming a source / drain junction on the semiconductor substrate on both sides of the gate electrode, forming an interlayer insulating film on the entire surface of the structure, and Forming a contact hole for the charge storage electrode by removing the interlayer insulating film on the upper part, which is supposed to be the charge storage electrode contact, and exposing the semiconductor substrate by removing the edge portions of the isolation oxide film exposed through the contact hole; Forming a sacrificial oxide film on the semiconductor substrate exposed through the contact hole; And forming a junction for preventing leakage current on the semiconductor substrate under the oxide film and removing the sacrificial oxide film.
이하, 본발명에 따른 반도체소자의 제조방법에 관하여 첨부 도면을 참조하여 상세히 설명한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
제 3a도 내지 제3d도는 본 발명에 따른 반도체소자의 제조공정도이다.3A to 3D are manufacturing process diagrams of a semiconductor device according to the present invention.
먼저, 제2도에 도시되어있는 바와 같은 고집적 반도체소자를 형성하여, 소자간의 분리를 위하여 소자분리 산화막(2)과 게이트 산화막(3)과 다결정실리콘층 패턴으로된 게이트전극(4)과, 상기 게이트전극(4) 양측의 반도체기판(1)에 형성된 소오스/드레인 접합(5)과, 산화막이나 질화막 등의 절연물질을 이용하여 스페이서(6) 및 콘택홀(8)을 구비하는 층간절연막(7)을 형성한다.First, a highly integrated semiconductor device as shown in FIG. 2 is formed, and the device isolation oxide film 2, the gate oxide film 3, and the gate electrode 4 having a polysilicon layer pattern are formed to separate the devices. An interlayer insulating film 7 having a spacer 6 and a contact hole 8 by using a source / drain junction 5 formed on the semiconductor substrate 1 on both sides of the gate electrode 4 and an insulating material such as an oxide film or a nitride film. ).
이때 상기 콘택홀(8)을 통하여 소자분리 산화막(2)의 가장자리 부분이 일부 제거되어 반도체기판(1)이 노출되며, 상기 소오스/드레인 접합(5)과 게이트 전극(4)과는 E 만큼 중첩되어 있으며 콘택홀(8)과 게이트 전극(4)과의 거리는 F 이다. 여기서 상기 소오스/드레인 접합(5)의 불순물 농도는 1.0×1019∼1.0×1020/㎤ 이상으로 게이트 전극(4) 하부의 채널 영역 또는 소자분리 산화막(2) 아래 영역의 불순물 농도인 1.0×1018∼1.0×1018/㎤ 보다 약 100배 내지 1000배 정도 높다. (제3a도 참조).In this case, a portion of the edge of the device isolation oxide film 2 is partially removed through the contact hole 8 to expose the semiconductor substrate 1, and the source / drain junction 5 and the gate electrode 4 overlap with each other by E. FIG. The distance between the contact hole 8 and the gate electrode 4 is F. Here, the impurity concentration of the source / drain junction 5 is 1.0 × 10 19 to 1.0 × 10 20 / cm 3 or more, which is 1.0 × which is the impurity concentration of the channel region under the gate electrode 4 or the region under the device isolation oxide film 2. It is about 100 to 1000 times higher than 10 18 to 1.0 × 10 18 / cm 3. (See also 3a).
그다음 상기 콘택홀(8)을 통하여 노출되어있는 반도체기판(1)을 소정의 분위기, 예를들어 600∼900℃의 온도에서 열산화시켜 30∼300Å 정도 두께의 희생산화막(10)을 형성한다. 여기서 상기 희생산화막(10)의 형성속도는 산화 분위기나 실리콘 기판내의 불순물 농도에 따라 달라지며, O2와 H2를 이용한 습식 산화에서는 산화 속도가 더욱 차이를 보이며, 높은 불순물 농도에서 산화 속도는 빠르다. 따라서 상기 희생산화막(10)은 소오스/드레인 접합(5)의 상측에서 훨씬 두껍게 형성된다. (제3b도 참조).Thereafter, the semiconductor substrate 1 exposed through the contact hole 8 is thermally oxidized at a predetermined atmosphere, for example, at a temperature of 600 to 900 ° C. to form a sacrificial oxide film 10 having a thickness of about 30 to about 300 kPa. Here, the formation rate of the sacrificial oxide film 10 depends on the concentration of impurities in the oxidizing atmosphere or the silicon substrate, and the oxidation rate is different in wet oxidation using O 2 and H 2 , and the oxidation rate is high at high impurity concentrations. . Therefore, the sacrificial oxide film 10 is formed much thicker on the source / drain junction 5. (See also 3b).
그후, 상기 희생 산화막(10)을 통하여 반도체기판(1)에 누설전류 방지를 위한 이온 주입을 실시하여 누설전류 방지용 접합(9)을 형성한다. 이때 희생 산화막(10)은 소오스/드레인 접합(5)의 상측에서 훨씬 두껍게 형성되어 있으므로, 주입된 이온에 의해 형성된 소오스/드레인 접합(5)과 게이트 전극(4)과의 중첩 정도는 최초의 간격인 E로서 변화가 없게 되므로 소자의 동작에는 영향을 미치지 않는다. (제3c도 참조).Thereafter, the semiconductor substrate 1 is implanted with ions for preventing leakage current through the sacrificial oxide film 10 to form the leakage current preventing junction 9. At this time, since the sacrificial oxide film 10 is formed much thicker on the source / drain junction 5, the overlapping degree between the source / drain junction 5 formed by the implanted ions and the gate electrode 4 is initially separated. Since phosphorus E does not change, it does not affect the operation of the device. (See also 3c).
그다음 상기 희생 산화막(10)을 건식 식각이나 HF 또는 비.오.이(Buffer Oxide Etchant; BOE) 용액을 이용하는 습식 식각방법으로 제거하여 반도체기판(1)을 노출시킨다. (제3d도 참조).The sacrificial oxide layer 10 is then removed by dry etching, or by wet etching using HF or Buffer Oxide Etchant (BOE) solution to expose the semiconductor substrate 1. (See also 3d).
이상에서 설명한 바와 같이, 본 발명에 따른 반도체소자의 제조방법은 전하저장전극 콘택홀을 통하여 소자분리 산화막의 가장자리부분 일부가 제거되어 노출되는 반도체기판을 열산화시켜 희생산화막을 형성하되, 소오스/드레인 접합의 일부도 함께 열산화되어 희생산화막의 두께차가 나도록하고, 이온주입을 통하여 누설전류 방지용 접합을 형성하고, 희생산화막을 제거하여 전하저장전극 콘택을 형성하였으므로, 소오스/드레인 접합과 게이트 전극과의 중첩 정도가 변화되지 않아 숏채널 현상이 감소되고, 펀치쓰루가 방지되며, 누설전류 방지용 접합의 형성으로 누설전류가 감소되어 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 이쓴 이점이 있다.As described above, in the method of fabricating a semiconductor device according to the present invention, a portion of the edge of the isolation oxide film is removed through thermal charge oxidation electrode contact hole to thermally oxidize the exposed semiconductor substrate to form a sacrificial oxide film, and thus source / drain. Some of the junctions were also thermally oxidized to increase the thickness of the sacrificial oxide film, the junction for preventing the leakage current was formed through ion implantation, and the sacrificial oxide film was removed to form the charge storage electrode contact. Thus, the source / drain junction was formed with the gate electrode. Since the degree of overlap does not change, short channel phenomenon is reduced, punch-through is prevented, and leakage current is reduced by forming a leakage current preventing junction, thereby improving process yield and device operation reliability.
Claims (5)
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