KR0179788B1 - Sram cell - Google Patents
Sram cell Download PDFInfo
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- KR0179788B1 KR0179788B1 KR1019950055621A KR19950055621A KR0179788B1 KR 0179788 B1 KR0179788 B1 KR 0179788B1 KR 1019950055621 A KR1019950055621 A KR 1019950055621A KR 19950055621 A KR19950055621 A KR 19950055621A KR 0179788 B1 KR0179788 B1 KR 0179788B1
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- gate
- oxide film
- buried contact
- silicon substrate
- polysilicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
Abstract
본 발명은 드라이브 트랜지스터의 게이트에 매몰콘택(Buried Contact)측벽을 형성하여 액세스 트랜지스터의 드레인과 매몰콘택을 형성하는 에스-램 셀의 제조방법에 관한 것으로, 상기 트랜지스터의 얼라인 마진을 향상시킴과 아울러 실리콘 기판의 손상을 방지하여 소자의 특성열화를 방지한 에스-램 셀의 제조방법을 제공하는 것을 목적으로 한다. 이에 본 발명은 필드 산화막과 게이트산화막이 형성된 실리콘 기판위에 제1게이트(Access TR)와 제2게이트(Drive TR)를 형성한 후, 상기 제1게이트와 제2게이트에 캡(CAP) 산화막을 형성하고, 포토레지스트 패턴을 이용하여 매몰콘택창을 형성한다. 이어서, 저농도 소오스/드레인 영역을 형성한 다음, 그 위에 폴리실리콘을 증착하고 에치백하여 제1게이트에는 엘디디측벽을, 제2게이트에는 매몰콘택측벽을 형성한 후, 고농도 소오스/드레인 영역을 형성하는 것을 요지로 하여 이루어진다. 따라서, 본 발명은 실리콘 기판에 손상을 주지 않고 매몰콘택을 형성할 수 있으면서도 제 1게이트와 제2케이트의 얼라인 마진이 증대되는 효과 발생한다.The present invention relates to a method for fabricating an S-RAM cell in which a buried contact side wall is formed in a gate of a drive transistor to form a drain and an buried contact of an access transistor. The present invention provides an improvement in alignment margin of the transistor. An object of the present invention is to provide a method of manufacturing an S-ram cell, which prevents damage to a silicon substrate and thus prevents deterioration of device characteristics. Accordingly, the present invention forms a first gate (Access TR) and a second gate (Drive TR) on the silicon substrate on which the field oxide film and the gate oxide film are formed, and then form a cap oxide film on the first gate and the second gate. A buried contact window is formed using the photoresist pattern. Subsequently, a low concentration source / drain region is formed, and then polysilicon is deposited and etched back to form an LED side wall at the first gate and a buried contact side wall at the second gate, and then a high concentration source / drain region is formed. It is done with the gist. Accordingly, the present invention produces an effect of increasing the alignment margin of the first gate and the second gate while being able to form a buried contact without damaging the silicon substrate.
Description
제1도의 (a) 내지 (d)는 종래의 기술에 따른 에스-램 셀의 제조방법을 도시한 공정수순도.(A) to (d) of FIG. 1 is a process flowchart showing a method of manufacturing an S-ram cell according to the prior art.
제2도는 본 발명에 따른 에스-램 레이아웃도.2 is an S-RAM layout diagram according to the present invention.
제3도의 (a) 내지 (f)는 본 발명에 따른 에스-램 셀의 제조방법을 도시한 공정수순도.Figure 3 (a) to (f) is a process flowchart showing a manufacturing method of the S-RAM cell according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
101 : 실리콘 기판 102 : 필드 산화막101 silicon substrate 102 field oxide film
103(103a, 103b) : 게이트 산화막 104 : 제1게이트103 (103a, 103b): gate oxide film 104: first gate
105 : 제2게이트 106, 107 : 캡 산화막105: second gate 106, 107: cap oxide film
110 : 폴리실리콘층 111 : 엘디디 측벽110 polysilicon layer 111 LED side wall
112 : 매몰콘택 측벽 120 : 매몰콘택112: investment contact side wall 120: investment contact
130, 140 : 소오스/드레인130, 140: source / drain
본 발명은 에스-램 셀(S-RAM CELL)의 제조방법에 관한 것으로, 특히 폴리실리콘으로 제1게이트(액세스 트랜지스터의 게이트)의 엘디디(LDD)측벽 과 제2게이트(드라이버 트랜지스터의 게이트)의 매몰콘택(Buried Contact)측벽을 형성하여 매몰콘택(Buried Contact)을 이루는 에스-램 셀의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an S-RAM cell, and more particularly, to poly-silicon (LDD) sidewalls of a first gate (gate of an access transistor) and a second gate (gate of a driver transistor). The present invention relates to a method of manufacturing an S-RAM cell forming a buried contact sidewall to form a buried contact.
종래 기술에 따른 에스-램 셀의 제조방법에 대해서 첨부한 제1도의 (a) 내지 (d)를 참조하여 설명하면 다음과 같다.A method of manufacturing an S-RAM cell according to the prior art will be described below with reference to (a) to (d) of FIG. 1.
먼저, 제1도의 (a)에 도시된 바와 같이 실리콘 기판(110)에 필드 산화막(12)을 형성한 후, 게이트 산화막(13)을 형성하고, 그 위에 매몰콘택창 형성용 포토레지스트패턴(14)을 형성한다. 이후, (b)도에 도시된 바와 같이 상기 포토레지스트패턴(14)을 마스크로 하여 식각함으로써, 매몰 콘택창을 형성한다.First, as shown in FIG. 1A, after forming the field oxide film 12 on the silicon substrate 110, the gate oxide film 13 is formed, and the photoresist pattern 14 for forming a buried contact window thereon. ). Thereafter, as shown in (b), the buried contact window is formed by etching the photoresist pattern 14 as a mask.
이어서, (c)도에 도시된 바와 같이 상기 결과물(11,12,13)위에 폴리 실리콘(20)을 증착한 후, (d)도에 도시된 바와 같이 상기 폴리실리콘층(20)을 선택적으로 식각함으로써, 제1게이트(21) 및 실리콘 기판(11)과 폴리실리콘(22)의 매몰콘택(15)이 형성된 제2게이트(22)가 정의된다.Subsequently, as shown in (c), the polysilicon 20 is deposited on the results 11, 12 and 13, and then the polysilicon layer 20 is selectively formed as shown in (d). By etching, the second gate 22 in which the first gate 21 and the buried contact 15 of the silicon substrate 11 and the polysilicon 22 is formed is defined.
이와 같은 종래 기술에 따른 에스-램 셀의 제조방법은 제1게이트와 실리콘 기판과 다결정실리콘이 매몰콘택을 이루는 제2게이트를 형성하기 위하여 폴리실리콘을 선택식각하게 되는데, 이때 식각되는 영역에 있어서 폴리실리콘과 실리콘기판이 직접 접촉하는 영역과 폴리실리콘과 게이트산화막이 접촉하는 영역의 물성의 차이에 의하여 폴리실리콘과 실리콘기판이 직접 첩촉하는 영역에서 과식각이 발생하였다. 따라서, 상기 과삭각에 의하여 누설전류가 증가하고, 또한 매몰콘택저항이 증가하게 되어 에스-램 소자의 특성을 열화시키는 문제점이 있었다.In the conventional method of manufacturing an S-RAM cell, polysilicon is selectively etched to form a second gate in which a first gate, a silicon substrate, and polycrystalline silicon form a buried contact. Due to the difference in physical properties between the region where silicon and the silicon substrate are in direct contact and the region where the polysilicon and the gate oxide film are in contact, overetching occurred in the region where the polysilicon and the silicon substrate directly contact each other. Therefore, the leakage current increases and the buried contact resistance increases due to the overcut angle, thereby deteriorating the characteristics of the S-RAM device.
또한, 선택적 식각으로 제1게이트와 제2게이트를 형성하기 위해서는 상호간에 얼라인 마진이 필요한 문제점도 있었다.In addition, in order to form the first gate and the second gate by selective etching, there is a problem that alignment margins are required between each other.
이에 본 발명은 상기와 같은 문제점을 해결하기 위하여 창안한 것으로, 폴리실리콘을 이용하여 제1게이트의 엘디디측벽과 제2게이트의 매몰콘택측벽을 형성하여 실리콘 기판과 폴리실리콘의 매몰콘택을 형성함으로써, 실리콘 기판의 손상을 방지하고 소자의 특성열화를 방지함과 아울러 제1게이트와 제2게이트의 얼라인 마진(Align Magin)을 향상시킨 에스-램 셀의 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems, by forming the buried contact side wall of the LED gate and the second gate of the first gate using polysilicon to form a buried contact of the silicon substrate and polysilicon It is an object of the present invention to provide a method of manufacturing an S-RAM cell which prevents damage to a silicon substrate and prevents deterioration of device characteristics and improves alignment margins of the first and second gates.
상기와 같은 목적을 달성하기 위한 본 발명에 따른 에스-램 셀의 제조방법은 필드산화막과 게이트산화막이 형성된 실리콘 기판위에 제1게이트와 제2게이트를 형성하는 공정과; 상기 제1게이트와 제2게이트의 측면과 상단면에 캡(CAP) 산화막을 형성하는 공정과; 상기 결과물위에 매몰콘택창을 형성하기 위한 포토레지스트 패턴을 형성하는 공정과; 상기 포토레지스트 패턴을 이용하여 상기 캡 산화막과 게이트산화막을 선택적으로 식각하여 매몰콘택창을 형성하는 공정과; 상기 결과물에 이온을 주입하여 저농도 소오스/드레인 영역을 형성한 후, 그 위에 폴리실리콘을 증착하는 공정과; 상기 폴리실리콘을 마스크 없이 에치백하여 제1게이트에는 엘디디측벽을 형성함과 아울러 제2게이트에는 매몰콘택측벽을 형성하는 공정과; 상기 결과물에 이온을 주입하여 고농도 소오스/드레인 영역을 형성하는 공정을 구비하여 이루어진 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing an S-RAM cell, including: forming a first gate and a second gate on a silicon substrate on which a field oxide film and a gate oxide film are formed; Forming a cap oxide film on side surfaces and top surfaces of the first and second gates; Forming a photoresist pattern for forming a buried contact window on the resultant material; Selectively etching the cap oxide film and the gate oxide film using the photoresist pattern to form a buried contact window; Implanting ions into the resultant to form a low concentration source / drain region, and then depositing polysilicon thereon; Etching back the polysilicon without a mask to form an LED side wall at the first gate and a buried contact side wall at the second gate; And implanting ions into the resultant to form a high concentration source / drain region.
상기와 같은 공정은 제1게이트와 제2게이트의 얼라인 마진을 향상시킴과 아울러 실리콘 기판의 손상을 줄일 수 있게 된다.Such a process can improve the alignment margin of the first gate and the second gate and reduce damage to the silicon substrate.
이하, 첨부된 도면 제2도와 제3도를 참조하여 본 발명에 따른 에스-램 셀의 제조방법을 설명한다.Hereinafter, a method of manufacturing an S-RAM cell according to the present invention will be described with reference to FIGS. 2 and 3.
제2도는 일반적인 에스-램 셀의 레이아웃도로서, 이에 도시된 바와 같이 액세스 트랜지스터의 드레인영역(140)과 드라이브 트랜지스터의 게이트(105)가 매몰콘택(120)을 형성한다.FIG. 2 is a layout diagram of a typical S-RAM cell. As shown therein, a drain region 140 of an access transistor and a gate 105 of a drive transistor form an investment contact 120.
제3도의 (a) 내지 (f)는 본 발명에 따른 에스-램 셀의 제조방법을 도시한 공정수순도로서, 이를 참조하여 자세히 설명하면 다음과 같다.3 (a) to (f) is a process flowchart showing a method of manufacturing an S-ram cell according to the present invention, which will be described in detail with reference to the following.
먼저, (a)도에 도시된 바와 같이 필드 산화막(102)과 게이트 산화막(103)이 형성된 실리콘 기판(101)위에 액세스(Access)트랜지스터의 제1게이트(104)와 드라이브(Drive) 트랜지스터의 제2게이트(105)를 형성한다. 이때 상기 제1게이트(104)는 게이트 산화막(103a;(d)도 참조)위에 형성되고, 제2게이트(105)는 게이트 산화막(103b;(d) 참조)과 필드 산화막(102)위에 형성되는 폴리실리콘 도전층이다.First, as shown in (a), the first gate 104 of the access transistor and the drive transistor of the access transistor are formed on the silicon substrate 101 on which the field oxide film 102 and the gate oxide film 103 are formed. Two gates 105 are formed. In this case, the first gate 104 is formed on the gate oxide film 103a (see also (d)), and the second gate 105 is formed on the gate oxide film 103b (see (d)) and the field oxide film 102. It is a polysilicon conductive layer.
이후, (b)도에 도시된 바와 같이 상기 제1게이트(104)와 제2게이트(105)의 측면과 상단면에 화학 기상 성장법(CVD) 또는 열산화법으로 캡(CAP) 산화막(106,107)을 형성한 후, (c)도에 도시된 바와 같이 상기 결과물위에 매몰콘택창을 형성하기 위한 포토레지스트 패턴(108)을 형성하고, 이어서 (d)도에 도시된 바와 같이 상기 포토레지스트 패턴(108)을 마스크로 하여 캡 산화막(107)과 게이트산화막(103)을 선택적으로 식각하여 매몰콘택창을 형성한 후 포토레지스트 패턴(108)을 제거한다. 이때, 상기 산화막(107,108)이 실리콘 기판(101)과 폴리실리콘(105)에 대하여 선택적으로 제거되도록 하는 식각은 특히 산화막(103)과 실리콘 기판(101)에 대한 선택식각성이 우수한 식각원과 방식을 선택한다.Subsequently, cap oxide films 106 and 107 are formed on the side and top surfaces of the first gate 104 and the second gate 105 by chemical vapor deposition (CVD) or thermal oxidation, as shown in (b). After forming the photoresist pattern 108, a photoresist pattern 108 for forming a buried contact window is formed on the resultant product as shown in (c), and then the photoresist pattern 108 as shown in (d). ), The cap oxide film 107 and the gate oxide film 103 are selectively etched to form a buried contact window, and then the photoresist pattern 108 is removed. In this case, the etching to selectively remove the oxide films 107 and 108 with respect to the silicon substrate 101 and the polysilicon 105 is particularly an etching source and a method having excellent selectivity to the oxide film 103 and the silicon substrate 101. Select.
그리고, (e)도에 도시된 바와 같이 상기 결과물에 대하여 이온을 주입하여 저농도 소오스/드레인 영역(130,140; (f)도 참조)을 형성한 후, 그 위에 폴리실리콘(110)을 증착한다. 이때, 게이트산화막(103a)이 있는 제1게이트(104) 부근영역에는 게이트 산화막이 제거된 제2게이트(105)부근영역보다 불순물 이온의 확산이 적게 된다.As shown in (e), ions are implanted into the resultant to form low concentration source / drain regions 130 and 140 (see also (f)), and then polysilicon 110 is deposited thereon. At this time, the diffusion of impurity ions is less in the region near the first gate 104 where the gate oxide film 103a is located than in the region near the second gate 105 where the gate oxide film is removed.
이어서, (f)도에 도시된 바와 같이 상기 폴리실리콘(110)을 마스크 없이 에치백(Etch Back)하여 제1게이트(104)의 측면에는 엘디디측벽(111)을 형성함과 아울러 제2게이트(105)의 측면에는 매몰콘택측벽(112)을 형성한 후, 다시 상기 결과물에 대하여 이온을 주입하여 고농도 소오스/드레인영역(130,140)을 형성한다.Subsequently, as shown in (f), the polysilicon 110 is etched back without a mask to form the LED side wall 111 on the side of the first gate 104 and the second gate. After the buried contact side wall 112 is formed on the side surface of 105, ions are implanted again to form the high concentration source / drain regions 130 and 140.
따라서, 상기와 같은 공정에 의하여 폴리실리콘(110)으로 이루어진 제2게이트(105)의 매몰콘택측벽(112)은 실리콘기판(101)(액세스 트랜지스터의 드레인영역;140)과 매몰콘택(120)을 형성하게 된다. 이때, 상기 매몰콘택(120)은 액세스 트랜지스터의 전기적 신호가 드라이브 트랜지스터의 제2게이트(105)로 인가되는 통로가 된다. 한편, 엘디디측벽(111)을 포함한 상기 제1게이트(104)와 매몰콘택측벽(112)을 포함한 제2게이트(105)를 마스크로 이용하여 고농도 이온을 주입함으로써, 고농도 소오스/드레인 영역(130,140)을 형성하게 된다.Accordingly, the buried contact side wall 112 of the second gate 105 made of the polysilicon 110 may form the silicon substrate 101 (drain region 140 of the access transistor) 140 and the buried contact 120 by the above process. To form. In this case, the investment contact 120 is a passage through which an electrical signal of the access transistor is applied to the second gate 105 of the drive transistor. Meanwhile, high concentration source / drain regions 130 and 140 are implanted using high concentration ions by using the first gate 104 including the LED side wall 111 and the second gate 105 including the buried contact side wall 112 as a mask. ).
상술한 바와 같이 본 발명에 의하면, 드라이브 트랜지스터의 게이트에 폴리실리콘측벽을 형성하여 액세스 트랜지스터의 드레인과 매몰콘택을 형성함으로써, 실리콘 기판에 손상을 주지 않고 매몰콘택을 형성할 수 있으면서도 제1게이트와 제2게이트의 얼라인 마진이 증대되는 효과 발생한다.As described above, according to the present invention, the polysilicon sidewalls are formed in the gate of the drive transistor to form the drain and the buried contact of the access transistor, so that the first gate and the first contact can be formed without damaging the silicon substrate. The effect is to increase the alignment margin of the two gates.
Claims (6)
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