JP3128304B2 - Method for manufacturing semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor memory.

[0002]

2. Description of the Related Art FIG. 4 shows a multilayer capacitor type DRAM manufactured according to a conventional example of the present invention. In this conventional example, memory cells for two bits are formed in one active region 31, and these memory cells are arranged symmetrically with respect to one contact hole 32 with a bit line.

The gate electrode 33 of the MOS transistor constituting the memory cell, that is, the word line and the contact hole 3
Between them, a design margin 35 having a certain distance in pattern is provided so that the gate electrode 33 and the bit line 34 are not in electrical contact with each other.

The design margin 35 is a margin for matching a mask for patterning the gate electrode 33 by photolithography and a mask for patterning the contact hole 32 by photolithography, and the gate electrode 33 and the contact. The variation in the pattern finish of the holes 32 is included.

[0005] Incidentally, DR of 1 μm class design rule
In the manufacture of AM, usually, a design margin 35 of about 0.5 to 1.0 μm is expected. Since the design margin 35 is required in this manner, the gate electrode 33 is laid out so as to avoid the contact hole 32, as is clear from FIG.

[0006]

However, if the design margin 35 is necessary as described above, the design margin 35 is added to the size of the memory cell in a direction perpendicular to the direction in which the gate electrode 33 extends. Must. Therefore, the memory cell area cannot be reduced, and a high-density DRAM cannot be manufactured.

When the gate electrode 33 is laid out so as to avoid the contact hole 32 as described above, the length of the gate electrode 33 is increased by the amount of the avoidance. For this reason, the processing speed of memory information is slow, and a high-performance semiconductor memory cannot be manufactured. Therefore, an object of the present invention is to provide a method for manufacturing a high-density and high-performance semiconductor memory.

[0008]

In order to achieve the above object, the present invention provides a gate electrode of a transistor in each of a pair of memory cells sharing one source / drain region of a transistor contacting a bit line. Forming a pattern connected to each other at a connection portion on the semiconductor region to be the source / drain region, and forming an opening on the semiconductor region, and simultaneously removing the connection portion to form the gate. A step of dividing the electrode, a step of introducing an impurity of a conductivity type opposite to that of the semiconductor substrate into the semiconductor region through the opening, and forming at least a part of the source / drain region; Forming a side wall made of an insulating film inside the opening to form a contact hole with the bit line.

It is preferable that at least a portion of the gate electrode above the channel region of the transistor is formed to be wider than other portions.

Further, it is preferable that the size of the opening in a direction perpendicular to the direction in which the gate electrodes extend is formed smaller than the interval between the gate electrodes.

[0011]

According to the present invention, the gate electrode of the transistor and the contact hole for the bit line are formed in self-alignment with each other. Therefore, there is no need to allow for a design margin between the gate electrode and the contact hole, and the memory cell area can be reduced.

In addition, since it is not necessary to allow for a design margin as described above, it is not necessary to extend the gate electrode by the design margin while avoiding the contact hole for the bit line, and the gate electrode can be shortened.

Further, even if the position where the opening is formed is displaced in a direction perpendicular to the direction in which the gate electrode extends, a predetermined gate length can be secured and the short channel effect can be avoided. .

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The first and second embodiments of the present invention applied to the manufacture of a stacked capacitor type DRAM will be described below with reference to FIGS.

FIGS. 1 and 2 show a first embodiment. In the first embodiment, as shown in FIG.
Next, an active region 2 and a field oxide film 3 are formed by an element isolation technique.

A gate oxide film 4 is formed on the surface of the active region 2, and a gate electrode 5 of a MOS transistor constituting a memory cell, that is, a word line is formed on the gate oxide film 4 and the field oxide film 3 with a polycrystalline Si film or the like. Formed.

However, at this time, as shown in FIG. 2A, a pair of gate electrodes 5 adjacent to each other are connected to each other at a connection portion 5a on the active region 2, and this connection portion 5a The active region 2 between the pair of gate electrodes 5 is covered.

After that, using the gate electrode 5 and the field oxide film 3 as a mask, an impurity of a conductivity type opposite to that of the Si substrate 1 is ion-implanted into the active region 2 to form a diffusion layer 6 in the active region 2. I do.

Next, as shown in FIG. 1B, an interlayer insulating film 7 is formed from a SiO ₂ film deposited by the CVD method, and a contact hole 8 reaching the diffusion layer 6 is formed in the interlayer insulating film 7. I do.
Thereafter, the lower electrode 9, the capacitor dielectric film 10, and the upper electrode 11 of the capacitor constituting the memory cell are formed of an N-type polycrystalline Si film, an ONO film, and an N-type polycrystalline Si film, respectively. Then, the interlayer insulating film 12 is made of BPSG film or P
It is formed of an SG film.

Next, as shown in FIG. 1C, an opening 13 penetrating through the interlayer insulating films 12, 7 and the gate electrode 5 is formed by using a photolithography technique and an etching technique.

At this time, as shown in FIG. 2B, the width 15 of the opening 13 in the extending direction of the gate electrode 5 is
A value including a margin for mask alignment is selected so that a can be removed and the gate electrodes 5 can be separated from each other.

The width 14 of the opening 13 in a direction perpendicular to the direction in which the gate electrode 5 extends,
Since the gate length of the S transistor is affected, the width 14 is set small so that the short channel effect does not occur in these MOS transistors.

Thereafter, a diffusion layer 16 is formed in the active region 2 by ion-implanting an impurity of a conductivity type opposite to that of the Si substrate 1 into the active region 2 through the opening 13. This diffusion layer 16 becomes one source / drain region common to a pair of MOS transistors in one active region 2.

Next, an insulating film 17 (FIG. 1D) such as a SiO ₂ film or a Si ₃ N ₄ film is deposited on the entire surface by the CVD method, and the entire surface of the insulating film 17 is anisotropically dry-etched. hand,
As shown in FIG. 1D, a side wall made of the insulating film 17 is formed inside the opening 13. As a result, a contact hole 13a with the bit line is formed.

The width of the insulating film 17 to be left as a side wall is
It is sufficient that the bit line and the gate electrode can be electrically separated. Thereafter, the bit line 18 is formed to complete the multilayer capacitor type DRAM.

FIG. 3 shows a multilayer capacitor type DRAM manufactured according to the second embodiment. In the second embodiment, as is clear from the comparison between FIGS. 3A and 2B, the width of the gate electrode 22 on the active region 2 and in the vicinity thereof is reduced. Substantially the same steps as those of the first embodiment are performed except that the width is larger than the width of the portion.

In the second embodiment, the opening 21 for forming the contact hole 21a for the bit line is located in a direction perpendicular to the extending direction of the gate electrode 22, as shown in FIG. Even if it is shifted, the gate length 23 can be ensured so that the short channel effect does not occur in the MOS transistor.

In order to prevent the short channel effect from occurring in the MOS transistor as described above, instead of increasing the width of the gate electrode 22 as in the second embodiment, the extending direction of the gate electrode 22 is not limited. The size of the opening 21 in a direction perpendicular to the direction may be smaller than the interval between the gate electrodes 22.

[0029]

According to the present invention, since the memory cell area can be reduced and the gate electrode can be shortened, a high-density and high-performance semiconductor memory can be manufactured.

Further, it is possible to manufacture a high-density and high-speed semiconductor memory while avoiding the short channel effect.

[Brief description of the drawings]

FIG. 1 is a side sectional view sequentially showing a first embodiment of the present invention.

FIGS. 2A and 2B are plan views sequentially showing the first embodiment, and FIG.
The portion along the line Ia-Ia corresponds to FIG. 1A, and the portion along the line Id-Id in FIG. 1B corresponds to FIG.

3A and 3B show a stacked capacitor type DRAM manufactured according to a second embodiment, in which FIG. 3A is a plan view, and FIG. 3B is a side sectional view taken along line bb of FIG. 3A.

4A and 4B show a stacked capacitor type DRAM manufactured according to a conventional example of the present invention, wherein FIG.
(B) is a side sectional view along the bb line of (a).

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Si substrate 5 Gate electrode 5 5a Connection part 13 Opening 13a Contact hole 16 Diffusion layer 17 Insulating film 18 Bit line 21 Opening 21a Contact hole

Claims (3)

(57) [Claims] 1. A method of manufacturing a semiconductor memory in which a memory cell is constituted by a transistor and a capacitor, and a pair of said memory cells shares one source / drain region of said transistor contacting a bit line. Forming a gate electrode of the transistor in each of the pair of memory cells in a pattern connected to each other at a connection portion on a semiconductor region to be the source / drain region; and forming an opening on the semiconductor region. Simultaneously with the formation, removing the connection portion to divide the gate electrode; and introducing an impurity of a conductivity type opposite to that of the semiconductor substrate into the semiconductor region through the opening to form the source / drain region. Forming at least a part, and after the introduction, forming a sidewall made of an insulating film inside the opening, The method of manufacturing a semiconductor memory and a step of forming a contact hole in the bit line. 2. The method according to claim 1, wherein at least a portion of the gate electrode on the channel region of the transistor is formed to be wider than other portions. 3. The method according to claim 1, wherein the size of the opening in a direction perpendicular to the direction in which the gate electrode extends is smaller than the distance between the gate electrodes.