JP2017017359A - Semiconductor device and manufacturing method of the same - Google Patents

Semiconductor device and manufacturing method of the same Download PDF

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Publication number
JP2017017359A
JP2017017359A JP2016204868A JP2016204868A JP2017017359A JP 2017017359 A JP2017017359 A JP 2017017359A JP 2016204868 A JP2016204868 A JP 2016204868A JP 2016204868 A JP2016204868 A JP 2016204868A JP 2017017359 A JP2017017359 A JP 2017017359A
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layer
etching stopper
formed
insulating film
stopper layer
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Japanese (ja)
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吉原 郁夫
Ikuo Yoshihara
郁夫 吉原
渉 布藤
Wataru Futo
渉 布藤
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ソニー株式会社
Sony Corp
富士通セミコンダクター株式会社
Fujitsu Semiconductor Ltd
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Abstract

PROBLEM TO BE SOLVED: To inhibit over etching of an element isolation insulation film and an impurity diffusion layer to suppress junction leakage in a contact structure having a high aspect ratio in an LSI device on which a DRAM cell and a logic are loaded in a mixed manner.SOLUTION: A semiconductor device comprises: a first etching stopper layer 121 which covers a peripheral MOS transistor; a second etching stopper layer 122 formed on an upper layer of a capacitor part of a DRAM memory cell; and impurity diffusion layers 113 of the peripheral MOS transistor connected to a metal wiring layer formed in the upper layer of the capacitor part by an electrode layer 131 which pierces the first and second etching stopper layers 121, 122, wherein at least one of the impurity diffusion layers 113 is connected with an electrode layer 131 on a boundary of an element isolation insulation layer 102 and a depth of a bottom of the electrode layer 131 formed on the element isolation insulation film 102 from a surface of the impurity diffusion layer 113 is formed shorter than a junction depth of the impurity diffusion layer 113.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a contact connecting an impurity diffusion layer formed on a semiconductor substrate and a gate electrode from a metal wiring layer formed on a capacitor upper layer of a DRAM without increasing junction leakage. The present invention relates to a device structure that can be stably formed and a manufacturing method thereof.

  A conventional LSI device mixed with a DRAM cell and logic will be described with reference to FIGS. 37, 38, and 39. FIG.

  FIG. 38 is an enlarged cross-sectional view centering on one MOS transistor. As shown in FIG. 38, the surface of the semiconductor substrate 91 is connected to the impurity diffusion layer 93 formed on the semiconductor substrate 91 and the gate electrode 92 from the metal wiring layer (not shown) formed in the upper layer of the DRAM cell. A contact hole 94 is provided. In order to achieve higher density, a DRAM memory cell capacitor needs to have a large capacity without increasing the area occupied by the capacitor, and is required to have a high height. Therefore, since a very deep contact is required, it is necessary to perform an etching process for a longer time, and accordingly, the contact hole 94 tends to be excessively etched.

  As shown in FIG. 38, the aspect ratio of the contact hole 94 (ratio of “contact depth” / “contact hole diameter”) is from 5 to 10, and the impurity diffusion layer 93 of the semiconductor substrate 91 and between the elements are arranged. It is very difficult to form a separation film (not shown) without etching, and in the worst case, an opening is formed beyond the bonding interface, leading to an increase in junction leakage.

  Therefore, in Japanese Patent Laid-Open No. 10-79430, as an improved technique, an impurity diffusion layer is formed without etching by etching by forming a silicon nitride film as an etching stopper layer in a contact opening on a semiconductor substrate. A technique for preventing the increase is disclosed.

  On the other hand, as shown in FIG. 37, in an LSI device in which DRAM cells and logic are mixedly mounted, the alignment margin between the impurity diffusion layer 93 and the contact hole 94 connected to the impurity diffusion layer 93 cannot be made large, and is drawn in FIG. As described above, the contact hole 94 may open at the boundary between the impurity diffusion layer 93 and the element isolation insulating film 95.

  In such a case, if the etching stopper layer formed immediately above the impurity diffusion layer 93 has an insufficient film thickness, the element isolation insulating film 95 is also etched and deeply etched beyond the surface of the impurity region. Cause a leak. In order to prevent this, it is necessary to form a thick etching stopper layer.

  However, as shown in FIG. 39, if the etching stopper layer 96 is formed thick, it causes a void (cavity) 98 in the interlayer insulating film 97 to be formed later. Alternatively, if a nitride film is used as the etching stopper film 96, the high relative dielectric constant causes an increase in inter-wiring capacitance, which in turn causes another problem of hindering device speedup. FIG. 39 is an explanatory view of problems in the prior art, and (a) and (b) each schematically show a cross section of the main part of the apparatus.

  As shown in FIG. 39A, when the insulating film sidewalls 910 are formed on both sides of the gate electrode 99, and the etching stopper film (silicon nitride film) 96 formed on the entire surface thereafter is thin, Even when the interlayer insulating film 97 is embedded thereon, it can be easily embedded between the gate electrodes 99 by a commonly used CVD (chemical vapor deposition) method. This is because, since the silicon nitride film is thin, a sufficient space between the gate electrodes 99 can be secured accordingly.

  However, when the film thickness is increased considerably as shown in FIG. 5B in order to perform a sufficient function as the etching stopper film 96, the gap between the gate electrodes 99 approaches abnormally and becomes a slit. Even if an interlayer insulating film 97 is to be formed later by CVD, a void (cavity) 98 is generated, so that even if it is heated and reflowed, it cannot be buried. As described above, when the etching stopper film 96 is thickened and a void (cavity) 98 is generated in the interlayer insulating film 97, the polysilicon electrode in the self-aligned contact portion in the DRAM cell is short-circuited through the void 98. Product yield will be significantly reduced.

  The formation of the etching stopper layer 96 in the intermediate layer of the interlayer insulating film 97 is not described in the prior art Japanese Patent Laid-Open No. 10-79430, but the prior art Japanese Patent Laid-Open No. 7-130873 discloses a cylinder type capacitor. A technique for forming a stopper layer against isotropic etching when forming the film is disclosed. By combining these two prior arts, it can be easily invented to form an etching stopper layer in the intermediate layer. However, it is not described that the etching layer is divided into multiple layers, and even if the etching layer is simply divided into two layers, if the first etching stopper layer at the lowest layer is thickened, in the above-described DRAM memory cell embedding, for example, formation of an interlayer insulating film Occasionally voids occur.

  The present invention relates to an LSI device in which DRAM cells and logic are mixedly mounted. When a contact hole having a large aspect ratio between an impurity diffusion layer formed on a semiconductor substrate and a gate electrode is formed from a metal layer, the hole is formed in the impurity diffusion layer. Even when the position is shifted, the etching of the element isolation insulating film and the impurity diffusion layer due to the over-etching is suppressed to suppress the junction leakage. Further, voids (cavities) are prevented from being generated in the embedding of the DRAM cell forming the first etching stopper layer.

  In order to solve the above problems, the present invention uses, for example, the following configuration.

  In a semiconductor device having a DRAM memory cell and a peripheral MOS transistor, an insulating film serving as a first etching stopper layer is formed so as to cover the surface including the gate electrode of the peripheral MOS transistor, and an upper layer or a lower layer of the capacitor portion of the DRAM memory cell A second etching stopper layer is formed on at least one of the transistors, and the impurity diffusion layer and the gate electrode of the peripheral MOS transistor are formed by the electrode layer penetrating the first etching stopper layer and the second etching stopper layer. It is connected to a metal wiring layer formed on the upper layer of the capacitor portion of the memory cell, and (a) at least one of the impurity diffusion layers is connected to the electrode layer on the boundary between the impurity diffusion layer and the element isolation insulating film. The impurity at the bottom of the electrode layer formed on the element isolation insulating film Depth from goldenrod surface of the thickness dimension of the junction depth and the first etching stopper layer of the impurity diffusion layer is a semiconductor device which is characterized by shorter than either one.

  (B) A sidewall formation layer of the peripheral MOS transistor and the first etching stopper layer are stacked on the word transistor in the DRAM memory cell region, and the sidewall formation layer of the peripheral MOS transistor and the The thickness of the laminated film of the first etching stopper layer is a semiconductor device characterized in that it is not less than 1/4 and not more than 1/2 of the minimum distance between word transistors in the DRAM memory cell region.

  In the semiconductor device of the present invention, in the semiconductor device having a DRAM memory cell and a peripheral MOS transistor, an insulating film serving as a first etching stopper layer is formed so as to cover the impurity diffusion region of the peripheral MOS transistor region and the gate electrode, A second etching stopper layer is formed above or below the capacitor portion of the DRAM memory cell, or above and below the capacitor portion of the DRAM memory cell, and the impurity diffusion layer and gate electrode of the peripheral MOS transistor are An electrode layer penetrating the first etching stopper layer and the second etching stopper layer is connected to a metal wiring layer formed on the capacitor portion of the DRAM memory cell, and at least one of the impurity diffusion layers includes the electrode The layer is the boundary between the impurity diffusion layer and the element isolation insulating film The depth of the bottom of the electrode layer formed on the element isolation insulating film from the surface of the impurity diffusion layer is a semiconductor device formed to be shorter than the junction depth of the impurity diffusion layer. is there.

  Furthermore, in another semiconductor device of the present invention, at least one of the impurity diffusion layers is formed on the element isolation insulating film, with the electrode layer connected on a boundary between the impurity diffusion layer and the element isolation insulating film. The depth of the bottom of the electrode layer from the surface of the impurity diffusion layer is a semiconductor device formed shorter than the thickness of the first etching stopper layer.

  Furthermore, in another semiconductor device of the present invention, the thickness of the laminated film of the sidewall formation layer of the peripheral MOS transistor and the first etching stopper layer is 1 / of the minimum distance between the word transistors in the DRAM memory cell region. The semiconductor device has 4 or more and 1/2 or less.

  Furthermore, in another semiconductor device of the present invention, the thickness of the laminated film of the sidewall formation layer of the peripheral MOS transistor and the first etching stopper layer is 1 / of the minimum distance between the word transistors in the DRAM memory cell region. The semiconductor device has 4 or more and 1/3 or less.

  Furthermore, in another semiconductor device of the present invention, at least one of the gate electrodes of the peripheral MOS transistor includes an electrode layer penetrating the first etching stopper layer and the second etching stopper layer, the gate electrode and the gate. The depth dimension from the upper surface of the element isolation insulating film at the bottom of the electrode layer formed on the sidewall insulating film is connected to the boundary of the sidewall insulating film formed on the electrode side wall. This is a semiconductor device formed shorter than the depth of the bottom.

  In the semiconductor device of the present invention, in the semiconductor device having a DRAM memory cell and a peripheral MOS transistor, an insulating film serving as a first etching stopper layer is formed so as to cover the impurity diffusion region of the peripheral MOS transistor region and the gate electrode, A second etching stopper layer is formed above or below the capacitor portion of the DRAM memory cell, or above and below the capacitor portion of the DRAM memory cell, and penetrates the second etching stopper layer to form the DRAM memory cell. At least one of the electrode layers connected to the bit line is disposed on the element isolation insulating film, and the depth of the bottom of the electrode layer from the surface of the element isolation insulating film is determined by the element isolation insulating film This is a semiconductor device formed with a shorter thickness dimension.

  Furthermore, in another semiconductor device of the present invention, at least one electrode layer that penetrates the second etching stopper layer and is connected to the bit line of the DRAM memory cell is disposed on the impurity diffusion region, and the impurity The depth dimension from the surface of the impurity diffusion region at the bottom of the electrode layer that reaches the impurity diffusion region through the first etching stopper layer among the electrode layers disposed on the diffusion region is the impurity diffusion region. This is a semiconductor device formed shorter than the junction depth dimension. The potential of the impurity diffusion layer to which the electrode layer is connected and the potential of the bit line of the DRAM memory cell have the same potential.

  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a DRAM memory cell and a peripheral MOS transistor. The word transistor of the DRAM memory cell is formed on a semiconductor substrate on which an element isolation insulating film and an element formation region are formed. Forming a peripheral MOS transistor, forming an insulating film serving as a first etching stopper layer on the impurity diffusion region and the gate electrode of the peripheral MOS transistor formation region, and forming the insulating film on the first etching stopper layer. Burying and planarizing the space of the word transistor of the DRAM memory cell with an interlayer insulating film different from the first etching stopper layer, forming a second etching stopper layer on the interlayer insulating film, and the second A capacity of the DRAM memory cell is formed on the etching stopper layer. Forming an insulating film on the capacitor, forming an opening on the insulating film, and temporarily stopping etching on the second etching stopper layer; and (2) etching and removing the etching stopper layer and the interlayer insulating film, and further stopping etching on the first etching stopper layer; and etching and removing the first etching stopper layer in the opening; Is formed on the boundary between the impurity diffusion layer and the element isolation insulating film, and the depth dimension of the bottom of the opening from the upper surface of the element isolation insulating film is (c) the impurity diffusion layer Or (d) a step of forming smaller than the thickness dimension of the first etching stopper layer, and Forming an electrode layer in the mouth, it is a manufacturing method of a semiconductor device and forming a metal wiring layer connected to the electrode layer.

  Furthermore, another manufacturing method of the present invention is a method for manufacturing a semiconductor device having a DRAM memory cell and a peripheral MOS transistor, wherein the word memory of the DRAM memory cell is formed on a semiconductor substrate on which an element isolation insulating film and an element forming region are formed. Forming a gate electrode of the transistor and a gate electrode of the peripheral MOS transistor; and forming an insulating film to be a sidewall formation layer covering the gate electrode of the word transistor of the DRAM memory cell and the gate electrode of the peripheral MOS transistor Then, the sidewall formation layer is anisotropically etched only in the peripheral MOS transistor formation region to form a sidewall on the gate sidewall of the peripheral MOS transistor, and the sidewall formation layer is left in the DRAM memory cell formation region. Process and the peripheral MOS transistor An insulating film serving as a first etching stopper layer is formed on the impurity diffusion region of the star formation region and the gate electrode, and the film thickness of the laminated film of the sidewall formation layer and the first etching stopper layer is the word transistor of the DRAM memory cell. A step of forming a film with a thickness of ¼ or more and ½ or less of the minimum interval of the above, and an interlayer insulating film different from the first etching stopper layer on the first etching stopper layer. Filling and planarizing the space of the transistor, forming a second etching stopper layer on the interlayer insulating film, forming a capacitor of the DRAM memory cell on the second etching stopper layer, and the capacitor Forming an insulating film thereon; forming an opening on the insulating film; and the second etching stopper. A step of temporarily stopping the etching, a step of etching and removing the second etching stopper layer and the interlayer insulating film in the opening, and a step of temporarily stopping the etching on the first etching stopper layer; In the method of manufacturing a semiconductor device, the method includes: a step of etching and removing the first etching stopper layer; a step of forming an electrode layer in the opening; and a step of forming a metal wiring layer connected to the electrode layer. is there.

  Further, according to another manufacturing method of the present invention, the insulating film to be the first etching stopper layer is formed so that the film thickness of the laminated film of the sidewall forming layer and the first etching stopper layer is the word transistor of the DRAM memory cell. A method of manufacturing a semiconductor device, characterized in that the film is formed with a film thickness of ¼ or more and 1 / or less of the minimum interval.

  Furthermore, in another manufacturing method of the present invention, at least one of the openings is formed on a boundary between the gate electrode and the sidewall insulating film, and an opening formed on the sidewall insulating film is formed. The depth of the bottom part from the upper surface of the element isolation insulating film is smaller than the depth dimension of the element isolation insulating film.

  Furthermore, another manufacturing method of the present invention includes: a step of forming a capacitor of the DRAM memory cell on the second etching stopper layer; a step of forming an insulating film on the capacitor; Forming a first opening in the gate electrode of the peripheral MOS transistor and temporarily stopping the etching on the second etching stopper layer; and forming the second etching stopper layer and the interlayer insulating film in the first opening. Etching is removed, and the etching is temporarily stopped on the first etching stopper layer, the first etching stopper layer is removed by etching in the first opening, and the insulating film formed on the capacitor Forming a second opening on the insulating film and on the impurity diffusion region of the peripheral MOS transistor. A step of temporarily stopping etching on the etching stopper layer; a step of etching and removing the second etching stopper layer and the interlayer insulating film in the second opening; and a step of temporarily stopping etching on the etching stopper layer; Etching the first etching stopper layer in the second opening, forming an electrode layer in the first opening and in the second opening, and metal wiring connected to the electrode layer And a step of forming a layer.

  Furthermore, another manufacturing method of the present invention includes a step of forming an insulating film removable by isotropic etching on the second etching stopper layer, and an insulating film removable by the isotropic etching selectively. Forming an opening and forming a capacitor lower electrode of the DRAM memory cell in the guide opening; and insulating that can be removed by the isotropic etching using the second etching stopper layer as a stopper for isotropic etching. Removing the film, forming a capacitor dielectric film and a capacitor upper electrode on the capacitor lower electrode, forming an insulating film on the capacitor upper electrode, and forming an opening on the insulating film A step of temporarily stopping etching on the second etching stopper layer, and the second etching stopper layer and the interlayer in the opening. Etching and removing the edge film, further stopping the etching once on the first etching stopper layer, etching and removing the first etching stopper layer in the opening, and forming an electrode layer in the opening And a step of forming a metal wiring layer connected to the electrode layer.

  Furthermore, in another manufacturing method of the present invention, an opening is formed on an electrode layer connected to the impurity diffusion region of the DRAM memory cell of the second etching stopper layer, and a sidewall is formed on the sidewall of the opening. Forming an etching mask having a contact hole meter smaller than the opening and forming the opening on the electrode layer connected to the impurity diffusion region of the DRAM memory cell; and an electrode DRAM through the opening. Forming a DRAM capacitor connected to the impurity diffusion region of the memory cell; forming an insulating film on the capacitor; forming an opening on the insulating film; and temporarily forming on the second etching stopper layer A step of stopping the etching, the second etching stopper layer and the interlayer insulating film are removed by etching in the opening, and the second A step of temporarily stopping etching on the etching stopper layer, a step of etching and removing the first etching stopper layer in the opening, a step of forming an electrode layer in the opening, and a metal connected to the electrode layer And a step of forming a wiring layer.

  Furthermore, in another manufacturing method of the present invention, a capacitor dielectric film and a capacitor upper electrode are formed on the capacitor lower electrode of the DRAM memory cell, and at least one of the second etching stopper layers is formed during etching of the capacitor upper electrode. Removing a portion, forming a third etching stopper layer on the capacitor lower electrode of the DRAM memory cell, forming an insulating film on the third etching stopper layer, and on the insulating film Forming an opening and temporarily stopping the etching on the third etching stopper layer; removing the third etching stopper layer and the interlayer insulating film by etching in the opening; and further on the first etching stopper layer And once stopping etching, and the first etching stopper in the opening A step of etching away, and forming an electrode layer in the opening, a manufacturing method of a semiconductor device and forming a metal wiring layer connected to the electrode layer.

  [Operation] In a semiconductor device (LSI device) in which a DRAM cell and logic are mixedly mounted and a method for manufacturing the same, a contact connecting from a metal wiring layer formed on the upper layer of the DRAM cell to an impurity diffusion layer formed on the semiconductor substrate and a gate electrode Is temporarily stopped by the second etching stopper layer formed under the capacitor formation layer of the DRAM memory cell, and the etching is stopped by the first etching stopper layer formed on the impurity diffusion layer and the gate electrode, thereby over-etching the semiconductor substrate. Suppresses junction leakage.

  The contact connecting the impurity diffusion layer formed on the semiconductor substrate and the gate electrode from the metal wiring layer formed on the upper layer of the DRAM cell and the second etching stopper layer formed below the capacitor forming layer of the DRAM memory cell are temporarily stopped. Thereby, the film thickness variation of the interlayer insulating film can be reset once. Since the film thickness of the remaining interlayer insulating film is more uniform and thinner, the first etching stopper layer formed on the impurity diffusion layer and the gate electrode can be formed thinner than the second etching stopper layer. Therefore, in the embedding of the DRAM cell for forming the first etching stopper layer, it is possible to prevent the formation of voids (cavities) in the buried interlayer insulating film between the word transistors in the DRAM cell.

The etching stopper formed under the DRAM cell can also be used as an etching mask for forming a contact connecting the capacitor of the DRAM cell and the substrate.
Further, the etching stopper under the DRAM cell can also be used as an etching stopper when forming the cylinder type capacitor.

It is a schematic structure sectional view showing the important section of one embodiment concerning the present invention. It is a schematic structure sectional view showing the important section of one embodiment concerning the present invention. It is a schematic structure sectional view and a plane layout figure showing an important section of one embodiment concerning the present invention. It is a schematic structure sectional view and a plane layout figure showing an important section of one embodiment concerning the present invention. It is apparatus sectional drawing (process 1) in the middle of the process based on one embodiment of this invention. It is apparatus sectional drawing (process 2) in the middle of the process based on one embodiment of this invention. It is apparatus sectional drawing (process 3) in the middle of the process based on one embodiment of this invention. It is apparatus sectional drawing (process 4) in the middle of the process based on one embodiment of this invention. It is apparatus sectional drawing (process 5) in the middle of the process based on one embodiment of this invention. It is apparatus sectional drawing (process 6) in the middle of the process based on one embodiment of this invention. It is apparatus sectional drawing (process 7) in the middle of the process based on one embodiment of this invention. It is apparatus sectional drawing (process 8) in the middle of the process based on one embodiment of this invention. It is apparatus sectional drawing (process 9) in the middle of the process based on one embodiment of this invention. It is apparatus sectional drawing (process 10) in the middle of the process based on one embodiment of this invention. It is apparatus sectional drawing (process 11) in the middle of the process based on one embodiment of this invention. It is apparatus sectional drawing (process 12) in the middle of the process based on one embodiment of this invention. It is apparatus sectional drawing (process 13) in the middle of the process based on one embodiment of this invention. It is apparatus sectional drawing (process 14) in the middle of the process based on one embodiment of this invention. It is apparatus sectional drawing (process 15) in the middle of the process based on one embodiment of this invention. It is apparatus sectional drawing (process 16) in the middle of the process based on one embodiment of this invention. It is apparatus sectional drawing (process 17) in the middle of the process based on one embodiment of this invention. It is apparatus sectional drawing (process 18) in the middle of the process based on one embodiment of this invention. It is apparatus sectional drawing (process 19) in the middle of the process based on one embodiment of this invention. It is apparatus sectional drawing (process 20) in the middle of the process based on one embodiment of this invention. It is apparatus sectional drawing (process 21) in the middle of the process based on one embodiment of this invention. It is apparatus sectional drawing (process 22) in the middle of the process based on one embodiment of this invention. It is apparatus sectional drawing (process 23) in the middle of the process based on one embodiment of this invention. It is apparatus sectional drawing (process 24) in the middle of the process based on one embodiment of this invention. It is apparatus sectional drawing (process 25) in the middle of the process based on one embodiment of this invention. It is apparatus sectional drawing (process 26) in the middle of the process based on one embodiment of this invention. It is apparatus sectional drawing (process 27) in the middle of the process based on one embodiment of this invention. It is apparatus sectional drawing (process 28) in the middle of the process based on one embodiment of this invention. It is apparatus sectional drawing (process 29) in the middle of the process based on one embodiment of this invention. It is a figure which shows the relationship between the memory cell word transistor space | interval, the contact failure occurrence rate resulting from void generation, and the failure occurrence rate due to junction leakage due to insufficient etching stopper film thickness. In the configuration of the present invention, it is a diagram showing a junction leakage reduction effect when at least one of the impurity diffusion layers is connected to the boundary between the impurity diffusion layer and the element isolation insulating film. In the structure of the present invention, it is a diagram showing a reduction effect of the element isolation insulating film digging amount when the electrode layer that penetrates the etching stopper layer is connected on the boundary between the gate electrode and the sidewall insulating film formed on the side wall of the gate electrode is there. It is explanatory drawing of the problem of a prior art. It is explanatory drawing of the problem of a prior art. It is explanatory drawing of the problem of a prior art.

  An example of an embodiment of the semiconductor device according to the present invention will be described with reference to FIGS. The semiconductor device of the present invention has a DRAM memory cell and a peripheral MOS transistor, and FIG. 1 shows a schematic cross-sectional view of the main part of the peripheral MOS transistor.

  As shown in FIG. 1, a DRAM memory cell and a peripheral MOS transistor are formed in an element formation region isolated by an element isolation insulating film 102 on a semiconductor substrate 101. A first etching stopper layer 121 made of an insulating film is formed so as to cover the gate electrode 111 in the peripheral MOS transistor region and the impurity diffusion region 113. The first etching stopper layer 121 is made of, for example, a silicon nitride film. A second etching stopper layer 122 is formed of, for example, a silicon nitride film on the upper layer of the capacitor portion of the DRAM memory cell. Although not shown, the second etching stopper layer 122 may be formed in the lower layer of the capacitor portion of the DRAM memory cell, or the upper layer and the lower layer of the capacitor portion of the DRAM memory cell. An interlayer insulating film 103 is formed between the layers of the DRAM memory cell and the peripheral MOS transistor.

  The impurity diffusion layer 113 of the peripheral MOS transistor is a metal wiring layer (not shown) formed on the upper layer of the capacitor portion of the DRAM memory cell by an electrode layer 131 penetrating the second etching stopper layer 122 and the first etching stopper layer 121. ). Although not shown, the gate electrode of the peripheral MOS transistor is connected to a metal wiring layer formed on the upper layer of the capacitor portion of the DRAM memory cell by an electrode layer penetrating the second etching stopper layer 122 and the first etching stopper layer 121. Has been.

In at least one impurity diffusion layer 113 of the impurity diffusion layer, the electrode layer 131 is connected on the boundary between the impurity diffusion layer 113 and the element isolation insulating film 102. The depth dimension t S from the surface of the impurity diffusion layer 113 at the bottom of the electrode layer 131 formed on the element isolation insulating film 102 is shorter than the junction depth dimension t J of the impurity diffusion layer 113.

Since the first etching stopper layer 121 is formed thinner than the impurity diffusion layer 113, the depth dimension from the surface of the impurity diffusion layer 113 at the bottom of the electrode layer 131 formed on the element isolation insulating film 102. t S may be formed shorter than the thickness t 1 of the first etching stopper layer 121.

  Next, an example of an embodiment according to the semiconductor device of the present invention will be described with reference to FIG. The semiconductor device of the present invention has a DRAM memory cell and a peripheral MOS transistor, and FIG. 2 shows a schematic cross-sectional view of the main part of the peripheral MOS transistor.

  As shown in FIG. 2, DRAM memory cells and peripheral MOS transistors are formed in an element formation region separated by an element isolation insulating film 102 on a semiconductor substrate 101. A first etching stopper layer 121 made of an insulating film so as to cover the gate electrode 111 in the peripheral MOS transistor region, the sidewall 115 formed on the side wall of the gate electrode 111, the impurity diffusion region (not shown), and the like. Is formed. The first etching stopper layer 121 is made of, for example, a silicon nitride film. A second etching stopper layer 122 is formed of, for example, a silicon nitride film on the upper layer of the capacitor portion of the DRAM memory cell. Although not shown, the second etching stopper layer 122 may be formed in the lower layer of the capacitor portion of the DRAM memory cell, or the upper layer and the lower layer of the capacitor portion of the DRAM memory cell. An interlayer insulating film 103 is formed between the layers of the DRAM memory cell and the peripheral MOS transistor.

On the word transistor (not shown) in the DRAM memory cell region, a sidewall forming layer of the peripheral MOS transistor and a first etching stopper layer 121 are laminated. At least one gate electrode 111 of the gate electrode of the peripheral MOS transistor has an electrode layer 131 connected on the boundary between the gate electrode 111 and the sidewall insulating film 115 formed of the sidewall formation layer. The depth dimension t S from the upper surface of the element isolation insulating film 102 at the bottom of the electrode layer 131 formed on the sidewall insulating film 115 is shorter than the depth dimension t L of the bottom of the element isolation insulating film 102. Yes.

  In the semiconductor device described with reference to FIGS. 1 and 2, the contact connecting from the metal wiring layer to the impurity diffusion layer 113 formed on the semiconductor substrate 101, the gate electrode 111, and the like is temporarily stopped by the second etching stopper layer 122, and Since it can be formed by stopping etching with the first etching stopper layer 121 covering the impurity diffusion layer 113, the gate electrode 111, etc., a structure in which over-etching of the semiconductor substrate 101 is suppressed and junction leakage is suppressed. It becomes.

  In each of the semiconductor devices, the thickness of the laminated film of the sidewall formation layer of the peripheral MOS transistor and the first etching stopper layer 121 is ¼ of the minimum distance between the word transistors in the DRAM memory cell region. Above and ½ or less, preferably ¼ or more and 3 or less.

  As described above, since the second etching stopper layer 122 is formed, an impurity diffusion layer formed on the semiconductor substrate and a contact connected to the gate electrode are formed from the metal wiring layer formed on the upper layer of the DRAM cell. In this case, etching temporarily stops at the second etching stopper layer. Thereby, the film thickness variation of the interlayer insulating film can be reset once. Since the thickness of the remaining interlayer insulating film is more uniform and thinner, the first etching stopper layer 121 can be formed thinner than the second etching stopper layer 122. Therefore, in the embedding of the DRAM cell for forming the first etching stopper layer 121, it is possible to prevent the occurrence of voids (cavities) in the buried interlayer insulating film between the word transistors in the DRAM memory cell.

  The etching stopper formed under the DRAM cell can also be used as an etching mask for forming a contact for connecting the capacitor of the DRAM cell and the semiconductor substrate 101. Further, the etching stopper under the DRAM cell can also be used as an etching stopper when forming the cylinder type capacitor.

  Further, an oxide film that can flow by heat treatment is formed as an interlayer insulating film on the first etching stopper layer 121 in the DRAM memory cell region, and in particular, voids (cavities) in the buried interlayer insulating film between word transistors are formed. Occurrence can be prevented.

  Next, an example of an embodiment according to the semiconductor device of the present invention will be described with reference to FIG. The semiconductor device of the present invention has a DRAM memory cell and a peripheral MOS transistor. FIG. 3 shows a main part of a DRAM memory cell bit contact, FIG. 3 (A) shows a schematic sectional view, and FIG. Shows a plane layout diagram.

  As shown in FIG. 3, DRAM memory cells and peripheral MOS transistors are formed in an element formation region separated by an element isolation insulating film 102 on a semiconductor substrate 101. A first etching stopper layer 121 made of an insulating film is formed so as to cover the peripheral MOS transistor. The first etching stopper layer 121 is made of, for example, a silicon nitride film. A bit line 141 is formed in the DRAM memory cell region. Furthermore, a second etching stopper layer 122 is formed of, for example, a silicon nitride film on the upper layer of the capacitor portion of the DRAM memory cell. Although not shown, the second etching stopper layer 122 may be formed in the lower layer of the capacitor portion of the DRAM memory cell, or the upper layer and the lower layer of the capacitor portion of the DRAM memory cell. An interlayer insulating film 103 is formed between the layers of the DRAM memory cell and the peripheral MOS transistor.

Further, an electrode layer 131 that penetrates the second etching stopper layer 122 and is connected to the bit line 141 in the DRAM memory cell region is disposed on the element isolation insulating film 102. If the electrode layer 131 is originally formed as designed, it is formed only on the bit line 141. However, due to misalignment at the time of exposure, processing error, etc., as shown in the figure, the electrode layer 131 may be connected beyond the bit line 141 in some cases. Even in such a configuration, in the configuration in which contact can be made, the electrode layer 131 is disposed on the element isolation insulating film 102 as described above, and the bottom of the electrode layer 131 extends from the upper surface of the element isolation insulating film 102. The depth dimension t S is shorter than the depth dimension t L at the bottom of the element isolation insulating film 102.

  Next, an example of an embodiment according to the semiconductor device of the present invention will be described with reference to FIG. The semiconductor device of the present invention has a DRAM memory cell and a peripheral MOS transistor. FIG. 4 shows a main part of the DRAM memory cell bit contact, FIG. 4A shows a schematic cross-sectional view, and FIG. Shows a plane layout diagram.

As shown in FIG. 4, an impurity diffusion region 105 isolated by an element isolation insulating film 102 is formed in the semiconductor substrate 101. A first etching stopper layer 121 made of an insulating film is formed so as to cover the peripheral MOS transistor. The first etching stopper layer 121 is made of, for example, a silicon nitride film. A bit line 141 is formed in the DRAM memory cell region. Furthermore, a second etching stopper layer 122 is formed of, for example, a silicon nitride film on the upper layer of the capacitor portion of the DRAM memory cell. Although not shown, the second etching stopper layer 122 may be formed in the lower layer of the capacitor portion of the DRAM memory cell, or the upper layer and the lower layer of the capacitor portion of the DRAM memory cell.
An interlayer insulating film 103 is formed between the layers of the DRAM memory cell and the peripheral MOS transistor.

Further, an electrode layer 131 that penetrates the second etching stopper layer 122 and is connected to the bit line 141 in the DRAM memory cell region is disposed on the element isolation insulating film 102. If the electrode layer 131 is originally formed as designed, it is formed only on the bit line 141. However, due to misalignment at the time of exposure, processing error, etc., as shown in the figure, the electrode layer 131 may be connected beyond the bit line 141 in some cases. In order to achieve contact with such a configuration, the electrode layer 131 is disposed on the impurity diffusion region 105 having the same potential as the bit line 141, and the impurity diffusion region at the bottom of the electrode layer 131 is provided. The depth dimension t S from the upper surface 105 is formed shorter than the junction depth dimension t J of the impurity diffusion region 105.

  In the semiconductor device described with reference to FIGS. 3 and 4, even when the bit contact is temporarily stopped by the second etching stopper layer 122 and the bit line 141 is protruded, the first etching stopper layer 121 is used. Since the etching can be stopped, overetching of the semiconductor substrate 101 is suppressed and a junction leak is suppressed.

In the semiconductor device shown in FIG. 3, the electrode layer 131 is disposed on the impurity diffusion region 105 having the same potential as the bit line 141, and the depth dimension t from the upper surface of the impurity diffusion region 105 at the bottom of the electrode layer 131. Since S is formed shorter than the junction depth dimension t J of the impurity diffusion region 105, the bit contact does not penetrate through to the semiconductor substrate 101, and therefore the electrode layer 131 is at least the impurity diffusion region 105. It is formed in a stopped state. Moreover, since the impurity diffusion region 105 has the same potential as that of the bit line 141, even if the bit contact is connected to the impurity diffusion prime 105, there is no electrical influence.

In the semiconductor device shown in FIG. 4, the electrode layer 131 is disposed on the element isolation insulating film 102, and the depth dimension t S from the upper surface of the element isolation insulating film 102 at the bottom of the electrode layer 131 is the element isolation insulation. Since the depth t L at the bottom of the film 102 is formed to be shorter, the bit contact does not penetrate through to the semiconductor substrate 101. Therefore, the electrode layer 131 stops at least in the element isolation insulating film 102. It is formed in the state.

  Next, an example of an embodiment according to a method for manufacturing a semiconductor device of the present invention will be described below. 5 to 33 are sectional views of the apparatus in the middle of the process according to one embodiment of the present invention, and schematically show the sections in the middle of the production from step (1) to step (29) in order from FIG.

  As shown in FIG. 5, after a silicon oxide film 2 of, for example, 50 nm to 200 nm (here, 100 nm as an example) is formed on a P-type silicon substrate 1, a silicon nitride film is formed using a CVD (chemical vapor deposition) method. 3 is formed with a thickness of, for example, 100 nm to 200 nm (here, 150 nm as an example). The silicon oxide film 2 is formed to relieve stress between the silicon nitride film 3 and the silicon substrate 1. A photoresist pattern (not shown) is selectively formed on an element formation region of the silicon nitride film 3 such as a MOS transistor. The silicon nitride film 3, the silicon oxide film 2, and the silicon substrate 1 are sequentially etched to form a groove 4 serving as a semiconductor element isolation region. The depth of the groove part 4 is set to a depth of, for example, 250 nm to 500 nm (here, 350 nm as an example).

  As shown in FIG. 6, a trench 4 is formed to cover the silicon nitride film 3, and a silicon oxide film 5 formed by, for example, HDP (High Density Plasma) CVD (Chemical Vapor Deposition) is, for example, 500 nm to 1000 nm (here, 750 nm as an example). ). Before the silicon oxide film 5 is formed, a silicon oxide film (not shown) with a thickness of, for example, about 50 nm to 200 nm (here, 100 nm as an example) may be formed by thermal oxidation.

  As shown in FIG. 7, CMP (chemical mechanical polishing) is used to polish and planarize the silicon oxide film 5 embedded in the trenches that form the element isolation regions. After polishing, the silicon nitride film 3 and the silicon oxide film 2 are removed by etching. In the present embodiment, the element isolation region is formed by the method of embedding in the trench, but a LOCOS method (selective oxidation method) conventionally used may be used.

  As shown in FIG. 8, a silicon oxide film of, for example, 50 nm to 200 nm (here, 100 nm as an example) is formed by oxidation (not shown). This silicon oxide film is formed as a so-called sacrificial oxide film, and thereafter, all of the silicon oxide film is removed after the ion implantation shown in FIG. 8 is performed. For example, phosphorus is implanted as an N-type impurity at a high energy in the DRAM memory cell formation region of the P-type semiconductor substrate 1 to form an N-well region 6, and boron is ion-implanted inside the N-well region 6 to form a P-well. Region 7 is formed. At the same time, an N well region and a P well region are also formed in a peripheral MOS formation region which is provided around the memory cell and functions as a logic circuit connected to the memory function. Further, ion implantation for determining threshold voltages of the N-channel MOS transistor, the P-channel MOS transistor, and the word transistor of the DRAM memory cell is performed.

As shown in FIG. 9, after removing the silicon oxide film (sacrificial oxide film) of 50 nm to 200 nm (here, 100 nm as an example), a gate oxide film is formed to a thickness of 2 to 10 nm.
At this time, the thickness of the gate oxide film is made according to the use of the transistor. For example, a thin film gate oxide film of 2 nm to 5 nm (here, 3 nm as an example) is formed in a peripheral MOS transistor formation region where high current drive capability and low off current are required. On the other hand, a thick gate oxide film having a thickness of 5 nm to 10 nm (here, 6 nm as an example) is formed in the peripheral MOS transistor formation region requiring high voltage operation. For the word transistor of the DRAM memory cell, a gate oxide film can be set in accordance with the data retention capability of the cell. This gate oxide film can be formed by forming a thicker gate oxide film on the entire surface, then selectively removing the gate oxide film in the region where the thin gate oxide film is to be formed, and oxidizing it again.

  As the gate electrode, a polysilicon layer or an amorphous silicon layer is formed by CVD or sputtering with a film thickness of 50 nm to 150 nm (here, 100 nm as an example). At this time, when adopting a dual gate structure in which both the N channel MOS transistor and the P channel MOS transistor are formed by surface channel MOS, for example, phosphorus is ion-implanted as an N-type impurity in the N channel MOS transistor formation region. Then, for example, boron is ion-implanted into the P channel MOS transistor formation region. For example, a tungsten silicide layer, which is a refractory metal silicide layer, is formed on the polysilicon layer or the amorphous silicon layer with a film thickness of 50 nm to 150 nm (here, 100 nm as an example) by CVD or sputtering.

  Next, for example, a silicon nitride film or a silicon oxide film serving as an offset film when forming a self-aligned contact of the DRAM memory cell is formed by a CVD method with a film thickness of 100 nm to 200 nm (here, 150 nm as an example). After forming the photoresist pattern for forming the gate electrode pattern, the offset film, the refractory metal silicide layer, the polysilicon layer or the amorphous silicon layer are sequentially etched by anisotropic etching to form the gate electrode 8 pattern. .

  As shown in FIG. 10, an LDD (lightly doped drain) impurity diffusion layer 9 is formed in the peripheral MOS transistor formation region. N-type impurities such as arsenic are ion-implanted into the N-channel MOS transistor formation region, and boron (BF2 +) is ion-implanted into the P-channel MOS transistor formation region. By performing pocket ion implantation between the channel region and the LDD impurity diffusion layer 9, the short channel effect can be suppressed. For example, a P-type impurity such as boron is ion-implanted into the N-channel MOS transistor formation region, and arsenic is ion-implanted into the P-channel MOS transistor formation region.

  As shown in FIG. 11, a silicon nitride film is once formed on the entire surface of the substrate to a thickness of, for example, 40 nm to 100 nm (here, 60 nm as an example). Next, a photoresist pattern (not shown) having an opening formed only in the peripheral MOS transistor formation region is formed. Next, anisotropic etching is performed on the entire surface to remove unnecessary silicon nitride film, and a sidewall layer 10 of silicon nitride film is formed on the side wall of the gate electrode in the peripheral MOS transistor formation region.

  As shown in FIG. 12, source / drain impurity diffusion layers 11 are formed in the peripheral MOS transistor formation region. N-type impurities such as arsenic are ion-implanted into the N-channel MOS transistor formation region, and boron is ion-implanted into the p-channel MOS transistor formation region. In order to form, for example, an N-channel MOS transistor as a word transistor in the DRAM memory cell formation region, an N-type impurity such as phosphorus is ion-implanted. Next, a cobalt layer and a titanium nitride film are sequentially formed on the silicon substrate by sputtering, and a cobalt silicide layer 12 is formed in the sidewall silicon nitride film opening in a self-aligning manner by heat treatment. An unreacted cobalt layer (not shown) on the sidewall silicon nitride film and the offset film is removed.

As shown in FIG. 13, a silicon nitride film (not shown) serving as a first etching stopper layer is formed on the entire surface to a thickness of 20 nm to 10 nm to 50 nm (here, 20 nm as an example).
At this time, the total laminated film thickness of the silicon nitride film side wall layer in which the silicon nitride film and the lower side wall are formed is 20 nm to 100 nm (in this example, 80 nm) is 30 nm to 150 nm (in this example, 100 nm). The total laminated film thickness of the silicon nitride film serving as the first etching stopper layer and the silicon nitride film on which the lower side wall is formed is equal to or more than ¼ of the word-transistor distance of 120 nm to 450 nm in the DRAM memory cell formation region. 2 or less, and in order to further increase the effect, it is desirable to set it to ¼ or more and 3 or less. The total laminated film thickness of the silicon nitride film serving as the first etching stopper layer and the silicon nitride film on which the lower side wall is formed is not less than ¼ and not more than ½ of the word-transistor distance in the DRAM memory cell formation region. FIG. 34 shows the effect obtained by setting it to 1/4 or more and 1/3 or less in order to increase the value.

  As shown in FIG. 34, the ratio of the total film thickness of the silicon nitride film serving as the first etching stopper layer and the silicon nitride film forming the lower side wall to the word-transistor distance in the DRAM memory cell formation region is The vertical axis indicates the contact failure rate due to voids generated in the buried planarization film between the words and transistors in the DRAM memory cell formation region, and the failure rate due to junction leakage due to insufficient film thickness of the first etching stopper layer. The defect occurrence rate is determined by the absolute amount of the film thickness of the first etching stopper layer. However, what is defined in the present invention is the total film thickness of the silicon nitride film serving as the first etching stopper layer and the silicon base film formed with the lower side wall, so that the word-transistor distance is 120 nm. For ˜450 nm, there is a correlation indicating that ¼ or more is necessary.

  As shown in FIG. 14, a BPSG (boron phosphorus silicate glass) layer to be a first interlayer insulating film 13 of about 500 nm to 1000 nm (here, 1000 nm as an example) is formed on the first etching stopper layer by a CVD method. The first interlayer insulating film is planarized by applying a heat treatment at 650 ° C. to 800 ° C. (here, 700 ° C. as an example) and reflowing. At this time, the total laminated film thickness of the silicon nitride film serving as the first etching stopper layer formed in the DRAM memory cell formation region and the silicon nitride film forming the lower side wall is set to an optimum film thickness. No voids are generated in the planarization of the BPSG film which is the first interlayer insulating film 13.

  This first interlayer insulating film can be implemented by either an HDP (high density plasma) CVD film or an SOG (spin on glass; coated silicon oxide film). Next, the BPSG layer as the first interlayer insulating film 13 is polished by a thickness of 200 nm to 900 nm (here, 400 nm as an example) by CMP (chemical mechanical polishing), and further planarized. For the planarization at this time, a technique such as full-surface etch back may be used.

  As shown in FIG. 15, a photoresist opening pattern was selectively formed in the first interlayer insulating film 13 in the DRAM memory cell formation region, and a silicon nitride film serving as a first etching stopper layer and a lower side wall were formed. The etching is temporarily stopped by etching that can take a selection ratio with the laminated thickness of the silicon nitride film, and then the laminated film of the silicon nitride film is etched to form contact holes 14 in a self-aligned manner between the word lines of the DRAM memory cell. This process is performed using a self-aligned contact technique that has been generally used.

  A polysilicon layer or an amorphous silicon layer is formed in the contact hole 14, and the first silicon electrode layer 15 is left only in the contact hole by CMP. In the present embodiment, the formation method by CMP is used, but the first silicon electrode layer 15 may be left in the contact hole 14 using a selective growth technique or etch back. The method for introducing impurities into the first silicon electrode layer 15 may be introduced simultaneously with the CVD of the first silicon electrode layer 15 or by ion implantation after CVD. In this embodiment, since the first silicon electrode layer 15 connected to the impurity diffusion layer of the word transistor formed by the N-channel MOS of the DRAM memory cell is formed, phosphorus, which is an N-type impurity, is converted into the first silicon. Introduced into the electrode layer 15.

  As shown in FIG. 16, after the second interlayer insulating film 16 made of a silicon oxide film is formed with a thickness of 50 nm to 200 nm (here, 100 nm as an example), the first silicon formed in the DRAM memory cell formation region is formed. An opening is selectively formed on the first silicon electrode layer corresponding to the bit contact in the electrode layer, and the bit line 17 connected to the first silicon electrode layer through the opening is formed. In this embodiment, a stacked wiring of tungsten having a thickness of 50 nm to 200 nm (here, 150 nm as an example) and a TiN barrier metal having a thickness of 50 nm is used as the bit line 17, but another refractory metal or refractory metal silicide is used. You may use the wiring of the polycide structure which laminated | stacked the layer and the polysilicon. Further, the bit line may be formed with a line width equal to or smaller than the resolution limit of photolithography by using a known trimming technique.

As shown in FIG. 17, after a third interlayer insulating film 18 made of a silicon oxide film is formed with a film thickness of 500 nm to 1500 nm (here, 1000 nm as an example), it is flattened using a technique such as CMP or overall etch back. Turn into. Next, a silicon nitride film to be the second etching stopper layer 19 is formed with a film thickness of 50 nm to 500 nm (here, 300 nm as an example).
At this time, the second etching stopper layer 19 can be formed thicker than the first etching stopper layer formed in the lower layer.

  An opening is selectively formed in the silicon nitride film on the first silicon electrode layer connected to the capacitor electrode in the first silicon electrode layer formed in the DRAM memory cell formation region. Covering the opening, the fourth interlayer insulating film, the second etching stopper layer, and a material having an etching selectivity such as a polysilicon layer or an amorphous silicon layer are formed over the entire surface with a thickness of 50 nm to 200 nm (here, 80 nm as an example). To do. The polysilicon layer or the amorphous silicon layer is anisotropically etched to form a sidewall etching mask layer made of the polysilicon layer or the amorphous silicon layer on the side wall of the opening of the second etching stopper layer.

  As shown in FIG. 18, the third interlayer insulating film 18 is etched using the second etching stopper layer 19 and the sidewall etching mask layer 21 as an etching mask to form a first memory cell formed in the DRAM memory cell formation region. A contact hole 20 is formed in the first silicon electrode 15 connected to the capacitor electrode in the silicon electrode layer 15. The contact hole 20 formed at this time is formed by etching using the second etching stopper layer 19 and the side wall etching mask layer 21 formed in a self-aligned manner in the opening, and this limits the lithography technique. A contact hole having a contact diameter exceeding the limit can be formed. As a result, even if the bit line forming technique using the above-described trimming is used, the contact does not drop from the bit line, and the breakdown voltage between the contact hole 20 and the bit line can be easily secured.

  As shown in FIG. 19, a polysilicon layer or an amorphous silicon layer is formed in the contact hole 20, and the second silicon electrode layer 22 is left only in the contact hole 20 by CMP. In this embodiment, the formation method by CMP is used. However, the second silicon electrode layer 22 may be left in the contact hole 20 by using a selective growth technique or etch back. The method of introducing impurities into the second silicon electrode layer 22 may be introduced simultaneously with the CVD of the second silicon electrode layer 22 or may be introduced by ion implantation after the CVD. In the present embodiment, since the second silicon electrode layer 22 is formed on the first silicon electrode layer 15 connected to the impurity diffusion layer of the word transistor formed by the N channel MOS of the DRAM memory cell, the N type Phosphorus as an impurity is introduced into the second silicon electrode layer 22.

  As shown in FIG. 20, an insulating film 23 such as BPSG having an etching selectivity between the second etching stopper layer 19 and the first silicon electrode layer 22 is formed on the second etching stopper layer 19 to 500 nm to 1500 nm (here, as an example) The opening 25 is formed on the second silicon electrode layer 22.

  As shown in FIG. 21, a polysilicon layer or an amorphous silicon layer is formed in the opening, and the third silicon electrode layer 24 that becomes the capacitor lower electrode is left only in the contact hole (opening) 25 by CMP. In the present embodiment, the formation method by CMP is used, but the third silicon electrode layer 24 may be left only in the contact hole 25 by using etch back such as reactive ion etching (RIE). The method for introducing impurities into the third silicon electrode layer 24 may be introduced simultaneously with the CVD of the third silicon electrode layer 24 or may be introduced by ion implantation after the CVD. In this embodiment mode, phosphorus that is an N-type impurity is introduced into the third silicon electrode layer 24.

  As shown in FIG. 22, the insulating film 23 such as BPSG is removed by wet etching using, for example, hydrofluoric acid, which is an isotropic etching that can take a selective ratio with the second etch back stopper layer 19, and the capacitor lower electrode and The third silicon electrode layer 24 is formed upright.

  As shown in FIG. 23, an ONO film (silicon oxide film-silicon nitride film-silicon oxide film) is formed as the dielectric film 26 to a thickness of 3 nm to 10 nm (here, 5 nm as an example). Further, a polysilicon layer or an amorphous silicon layer is formed to form a fourth silicon electrode layer 27 to be a capacitor upper electrode. As a method for introducing impurities into the fourth silicon electrode layer 27, the impurity may be introduced simultaneously with the CVD of the fourth silicon electrode layer 27 or by ion implantation after the CVD. In this embodiment mode, phosphorus that is an N-type impurity is introduced into the fourth silicon electrode layer 27.

  In this embodiment, a silicon electrode is used as the capacitor electrode, but a metal electrode may be used. Further, in the present embodiment, an ONO film is used as the capacitor dielectric film 26, but a ferroelectric film such as a tantalum oxide film or BST may be used. Further, in the embodiment of the present invention, the capacitor having the cylinder structure is formed, but a simple multilayer capacitor or a capacitor electrode having a fin structure can be applied. When the insulating film 23 such as BPSG under the third silicon electrode layer 24 is removed by isotropic etching having a selection ratio with the second etching stopper layer, and when the pattern of the fourth silicon electrode layer 27 is formed by etching. The second etching stopper layer 19 is etched to reduce the film thickness. If it is difficult to control the amount of film loss at this time, part or all of the total thickness of the second etching stopper layer 19 is removed by etching when the fourth silicon electrode layer 27 pattern is formed by etching. A method for newly forming the third etching stopper layer is another method for manufacturing a semiconductor device according to the present invention.

  As shown in FIG. 24, after a fourth interlayer insulating film 28 made of a silicon oxide film is formed with a film thickness of 500 nm to 2500 nm (here, 1500 nm as an example), a capacitor is used by using a technique such as CMP or etch back. The fourth interlayer insulating film is planarized so as to leave a thickness of 100 nm to 1000 nm (here, 1000 nm as an example).

  As shown in FIG. 25, a photoresist opening pattern 29 is selectively formed on the fourth interlayer insulating film 28.

  In this embodiment, a contact hole 30 is first opened on the gate electrode wiring in the peripheral MOS transistor formation region. Etching the fourth interlayer insulating film 28 At this time, the etching is temporarily stopped on the second etching stopper layer 19 after the removal of the fourth interlayer insulating film 28 under the etching conditions that can be selected with the second etching stopper layer 19. .

As shown in FIG. 26, the second etching stopper layer 19 is etched, and the third interlayer insulating film 18, the second interlayer insulating film 16, and the first interlayer insulating film 13 are sequentially etched.
At this time, the etching is temporarily stopped on the first etching stopper layer after the first interlayer insulating film 13 is removed under the etching conditions that can be selected with the first etching stopper layer.

  As shown in FIG. 27, the first etching stopper layer 13 is etched, and then the offset film (eg, silicon nitride film or silicon oxide film) of the gate electrode 8 in the peripheral MOS transistor formation region is removed by etching. A contact hole 30 is formed on 8.

As shown in FIG. 36, in this figure, in the configuration of the present invention, an electrode layer (not shown) formed in the contact window 30 that penetrates the etching stopper layer is formed on the gate electrode 8 and the side wall of the gate electrode 8. FIG. 6 is a diagram showing the effect of reducing the amount of digging of the element isolation insulating film 5 when connected on the boundary of the formed sidewall insulating film, where t S is the depth of the bottom of the electrode formed on the element isolation insulating film 5 The dimension, t L, is the depth dimension of the bottom of the element isolation insulating film 5.

  As shown in FIG. 28, a photoresist opening pattern 31 is selectively formed in the fourth interlayer insulating film 28.

  In the present embodiment, a contact hole 32 is opened on the impurity diffusion layer in the peripheral MOS transistor formation region following the contact 30 on the gate electrode 8 wiring layer in the peripheral MOS transistor formation region. At this time, the contact hole 30 formed on the gate electrode 8 is filled with the photoresist 31. When the fourth interlayer insulating film 28 is etched, the etching is temporarily stopped on the second etching stopper 19 layer after the fourth interlayer insulating film 28 is removed under an etching condition that can be selected with the second etching stopper layer 19.

As shown in FIG. 29, the second etching stopper layer 19 is etched, and the third interlayer insulating film 18, the second interlayer insulating film 16, and the first interlayer insulating film 13 are sequentially etched.
At this time, the etching is temporarily stopped on the first etching stopper layer after the first interlayer insulating film 13 is removed under the etching conditions that can be selected with the first etching stopper layer.

  As shown in FIG. 30, the first etching stopper layer is etched to form a contact hole 32 on the impurity diffusion layer in the peripheral MOS transistor formation region.

  As shown in FIG. 31, in the contact hole 32, for example, a titanium layer having a thickness of 10 nm to 100 nm (here 20 nm as an example) and a barrier metal having a thickness of 10 nm to 50 nm (here 20 nm as an example) 20 nm, for example. A titanium nitride film is formed by sputtering or CVD. Next, a tungsten layer 33 to be a first metal electrode is formed to a film thickness of, for example, 100 nm to 500 nm (here, 300 nm as an example) by sputtering or CVD. Next, the first metal electrode 33 is removed from other regions so as to leave the first metal electrode 33 only in the contact hole 32 by CMP or overall etch back. If the first metal electrode 33 is selectively formed in the contact hole 32 from the beginning by using a technique such as a selective CVD method, the etch back and CMP processes can be omitted.

  As shown in FIG. 32, a first metal wiring layer 34 that is electrically connected to the first metal electrode 33 is formed. The first metal wiring layer 34 is, for example, a titanium layer with a thickness of 3 nm to 50 nm, a titanium nitride film serving as a barrier metal with a thickness of 10 nm to 50 nm (here 10 nm as an example), 200 nm to 800 nm (here As an example, an aluminum wiring layer containing copper having a thickness of 400 nm, a titanium layer having a thickness of 3 nm to 10 nm (here 5 nm as an example), and a titanium nitride film having a thickness of 10 nm to 100 nm (here 70 nm as an example). The aluminum wiring layer containing copper may be other materials such as aluminum wiring and copper wiring, etc. The fifth interlayer insulating film 35 is formed on the first metal wiring layer 34. After forming a silicon oxide film with a film thickness of 500 nm to 2000 nm (here, 2000 nm as an example), CMP is performed. Planarized using etch-back carried out using.

  FIG. 33 shows a cross section of the device in a step that follows the step corresponding to FIG. As shown in FIG. 33, the second metal electrode 36 and the second layer metal wiring are formed in the same manner as the formation of the first metal electrode 33, the first metal wiring layer 34 and the fifth interlayer insulating film 35. The layer 37, the sixth interlayer insulating film 38, the third metal electrode 39, the third metal wiring layer 40, the seventh interlayer insulating film 41, the fourth metal electrode 42, and the fourth metal wiring layer 43. And an eighth interlayer insulating film 44 are sequentially formed. A silicon nitride film is formed as the overcoat film 45 to a thickness of, for example, 500 nm to 1500 nm (here, 700 nm as an example), and then an opening (not shown) is formed in a portion serving as a pad in the fourth metal wiring layer 43. Selectively form.

  In the present embodiment, the method of separately opening the contact hole on the gate electrode layer and the impurity diffusion layer in the peripheral MOS transistor formation region has been described. However, it is also possible to simultaneously open the contact hole. . In the case of opening separately, the opening order may be such that the impurity diffusion layer is opened first and then the gate electrode wiring is opened.

According to the embodiment of the present invention, as shown in FIG. 35, the opening in which the electrode layer connected to the metal wiring layer is embedded may be formed on the boundary between the impurity diffusion layer and the element isolation insulating film, for example. Since the etching is controlled (temporarily stopped) by the second etching stopper layer and the first etching stopper layer, the digging amount t S of the element isolation insulating film is larger than the junction depth dimension t J of the impurity diffusion layer. There is no. For this reason, junction leakage can be reduced. Further, the film thickness t 1 of the first etching stopper layer is set to a minimum necessary film thickness that can be embedded in the DRAM memory cell, and an element corresponding to the overetching amount at the time of etching the first etching stopper layer. The film thickness dimension t 1 of the first etching stopper layer is larger than the digging amount t S of the isolation insulating film.

As a comparative example, an example in which the structure and method of the present invention are not employed will be described with reference to FIG. As shown in FIG. 37, when the digging amount t S of the element isolation insulating film becomes larger than the junction depth dimension t J of the impurity diffusion layer, the impurity diffusion layer and the well region are connected via the electrode layer connected to the metal wiring layer. Short circuit.

According to the embodiment of the present invention, as shown in FIG. 36, the opening in which the electrode layer connected to the metal wiring layer is embedded may be formed on the boundary between the gate electrode layer and the sidewall insulating film, for example. Since the etching is controlled by the second etching stopper layer and the first etching stopper layer, the digging amount t S of the element isolation insulating film does not become larger than the depth dimension t L of the element isolation insulating film.

As a comparative example, an example in which the structure and method of the present invention are not employed will be described with reference to FIG. As shown in FIG. 38, when the digging amount t S of the element isolation insulating film becomes larger than the depth dimension t L of the element isolation insulating film, the gate electrode and the well region are short-circuited via the electrode layer connected to the metal wiring layer. To do.

  The above is the description of the present invention based on one embodiment. However, the present invention is not limited to this, and various modifications can be made to the present invention. For example, as the peripheral MOS transistor, the MOS transistor constituting the logic circuit provided around the memory cell and connected to the memory function has been described as a layout. However, the peripheral MOS transistor is not limited to this, but the DRAM itself other than the memory cell Unlike a DRAM memory portion, such as a MOS transistor that forms a part of the above functions and a MOS transistor that constitutes an SRAM cell, the same effect can be obtained with any MOS transistor having a relatively low altitude.

  The second etch-back stopper film can be formed by (1) a method provided between an interlayer insulating film provided immediately above the word line and an interlayer insulating film provided on the bit line portion, and (2) before capacitor formation. Any of the three methods may be used (a method provided on the interlayer insulating film provided on the bit line portion) and (3) a method provided on the interlayer insulating film provided on the bit line portion after the capacitor is formed.

  In the above embodiment, the description has been given by exemplifying filling of voids between the gates (word lines) of adjacent memory cell transistors. However, the present invention is applied to gate electrodes other than word lines, wiring layers, and the like. Similarly, it can be preferably used to fill a concave portion formed between various patterns patterned by anisotropic etch back, and applicable ones are not limited to between word lines.

  In addition to using a silicon nitride film, the etch-back stopper material can be appropriately determined by considering the type of interlayer insulating film and the type of etchant gas used at the time of opening. A membrane should be used. When a conductive film is used, removal after use as an etching stopper film is indispensable, but it is not easy to remove, and even if it is to be removed by anisotropic etching or the like, it is under a step or on the side of a side wall. In some cases, the conductive film may remain without being removed, and may cause a short circuit of the remaining conductive film in a later process. In addition, in order to select an insulating film material that can be used as an etching stopper, in order to use it in a recent miniaturized semiconductor device, so as not to impair high-speed performance and to reduce the capacitance between wirings. Selection from a material with a low dielectric constant is preferred.

  Next, in addition to the above-described embodiments, the main embodiments of the present invention are summarized below.

  (1) The semiconductor device has a DRAM memory cell and a peripheral MOS transistor, and an insulating film serving as a first etching stopper layer is formed so as to cover the surface including the gate electrode of the peripheral MOS transistor. A second etching stopper layer is formed on at least one of the upper layer and the lower layer of the capacitor portion of the DRAM memory cell. The impurity diffusion layer and the gate electrode of the peripheral MOS transistor are connected to a metal wiring layer formed on the upper layer of the capacitor portion of the DRAM memory cell by an electrode layer passing through the first etching stopper layer and the second etching stopper layer. Has been. At least one of the impurity diffusion layers is formed by connecting the electrode layer on the boundary between the impurity diffusion layer and the element isolation insulating film, from the surface of the impurity diffusion layer at the bottom of the electrode layer formed on the element isolation insulating film. The depth dimension is characterized by being formed smaller than the junction depth dimension of the impurity diffusion layer.

  (2) The semiconductor device has a DRAM memory cell and a peripheral MOS transistor, and an insulating film serving as a first etching stopper layer is formed so as to cover the surface including the gate electrode of the peripheral MOS transistor. A second etching stopper layer is formed on at least one of the upper layer and the lower layer of the capacitor portion of the DRAM memory cell. The impurity diffusion layer and the gate electrode of the peripheral MOS transistor are connected to a metal wiring layer formed on the upper layer of the capacitor portion of the DRAM memory cell by an electrode layer passing through the first etching stopper layer and the second etching stopper layer. Has been. At least one of the impurity diffusion layers is formed by connecting the electrode layer on the boundary between the impurity diffusion layer and the element isolation insulating film, from the surface of the impurity diffusion layer at the bottom of the electrode layer formed on the element isolation insulating film. The depth dimension is characterized by being formed smaller than the thickness dimension of the first etching stopper layer.

  (3) The semiconductor device has a DRAM memory cell and a peripheral MOS transistor, and an insulating film serving as a first etching stopper layer is formed so as to cover the surface including the gate electrode of the peripheral MOS transistor. A second etching stopper layer is formed on at least one of the upper layer and the lower layer of the capacitor portion of the DRAM memory cell. The impurity diffusion layer and the gate electrode of the peripheral MOS transistor are connected to a metal wiring layer formed on the upper layer of the capacitor portion of the DRAM memory cell by an electrode layer passing through the first etching stopper layer and the second etching stopper layer. Has been. A sidewall formation layer of the peripheral MOS transistor and a first etching stopper layer are laminated on the word transistor in the DRAM memory cell region. Furthermore, the thickness of the laminated film of the sidewall formation layer of the peripheral MOS transistor and the first etching stopper layer is not less than 1/4 and not more than 1/2 of the minimum distance between the word transistors in the DRAM memory cell region. It is characterized by.

  (4) The semiconductor device has a DRAM memory cell and a peripheral MOS transistor, and an insulating film serving as a first etching stopper layer is formed so as to cover the surface including the gate electrode of the peripheral MOS transistor. A second etching stopper layer is formed on at least one of the upper layer and the lower layer of the capacitor portion of the DRAM memory cell. The impurity diffusion layer and the gate electrode of the peripheral MOS transistor are connected to a metal wiring layer formed on the upper layer of the capacitor portion of the DRAM memory cell by an electrode layer passing through the first etching stopper layer and the second etching stopper layer. Has been. A sidewall formation layer of the peripheral MOS transistor and a first etching stopper layer are laminated on the word transistor in the DRAM memory cell region. Furthermore, the thickness of the laminated film of the sidewall formation layer of the peripheral MOS transistor and the first etching stopper layer is not less than 1/4 and not more than 1/3 of the minimum distance between the word transistors in the DRAM memory cell region. It is characterized by.

  (5) In the semiconductor device having the DRAM memory cell and the peripheral MOS transistor described in (3) above, an insulating film serving as a first etching stopper layer is formed so as to cover the surface including the gate electrode of the peripheral MOS transistor. Yes. A second etching stopper layer is formed on at least one of the upper layer and the lower layer of the capacitor portion of the DRAM memory cell. A sidewall formation layer of the peripheral MOS transistor and a first etching stopper layer are laminated on the word transistor in the DRAM memory cell region. Furthermore, the thickness of the laminated film of the sidewall formation layer of the peripheral MOS transistor and the first etching stopper layer is not less than 1/4 and not more than 1/2 of the minimum distance between the word transistors in the DRAM memory cell region. It is characterized by.

  (6) The semiconductor device has a DRAM memory cell and a peripheral MOS transistor, and an insulating film serving as a first etching stopper layer is formed so as to cover the surface including the gate electrode of the peripheral MOS transistor. A second etching stopper layer is formed on at least one of the upper layer and the lower layer of the capacitor portion of the DRAM memory cell. The impurity diffusion layer and the gate electrode of the peripheral MOS transistor are connected to a metal wiring layer formed on the upper layer of the capacitor portion of the DRAM memory cell by an electrode layer passing through the first etching stopper layer and the second etching stopper layer. Has been. At least one of the gate electrodes of the peripheral MOS transistor has an electrode layer penetrating the etching stopper layer formed on the gate electrode and the side wall of the gate electrode and connected to the boundary of the side wall insulating film. Further, the depth dimension from the upper surface of the element isolation insulating film at the bottom of the electrode layer formed on the sidewall insulating film is smaller than the depth dimension of the bottom of the element isolation insulating film. .

  (7) In the semiconductor device having the DRAM memory cell and the peripheral MOS transistor described in (1) above, the film thickness of the second etching stopper layer is formed larger than the film thickness of the first etching stopper layer. Is a feature.

  (8) In the semiconductor device having the DRAM memory cell and the peripheral MOS transistor described in (2) above, the film thickness of the second etching stopper layer is larger than the film thickness of the first etching stopper layer. It is characterized by being.

  (9) In the semiconductor device having the DRAM memory cell and the peripheral MOS transistor described in (3) above, the second etching stopper layer is formed to be thicker than the first etching stopper layer. Is a feature.

  (10) In the semiconductor device having the DRAM memory cell and the peripheral MOS transistor described in (4) above, the second etching stopper layer is formed to be thicker than the first etching stopper layer. Is a feature.

  (11) In the semiconductor device having the DRAM memory cell and the peripheral MOS transistor described in (5) above, the second etching stopper layer is formed to be thicker than the first etching stopper layer. Is a feature.

  (12) In the semiconductor device having the DRAM memory cell and the peripheral MOS transistor described in (6) above, the second etching stopper layer is formed to be thicker than the first etching stopper layer. Is a feature.

  (13) A method of manufacturing a semiconductor device is a method of manufacturing a semiconductor device having a DRAM memory cell and a peripheral MOS transistor, wherein the word of the DRAM memory cell is formed on a semiconductor substrate on which an element isolation insulating film and an element formation region are formed. A step of forming a transistor and the peripheral MOS transistor, a step of forming an insulating film serving as a first etching stopper layer on the impurity diffusion region and the gate electrode of the peripheral MOS transistor forming region, and on the first etching stopper layer Burying and planarizing the space of the word transistor of the DRAM memory cell with an interlayer insulating film different from the first etching stopper layer, forming a second etching stopper layer on the interlayer insulating film, and The DRAM memory cell capacity is formed on the second etching stopper layer. Forming an insulating film on the capacitor, forming an opening on the insulating film, temporarily stopping the etching on the second etching stopper layer, and a second in the opening. Etching and removing the etching stopper layer and the interlayer insulating film, and further stopping the etching on the first etching stopper layer; and etching and removing the first etching stopper layer in the opening; At least one is formed on the boundary between the impurity diffusion layer and the element isolation insulating film, and the depth dimension from the top surface of the element isolation insulating film at the bottom of the removal opening is the junction depth of the impurity diffusion layer. Forming the electrode layer in the opening, and forming a metal wiring layer connected to the electrode layer. Eteiru.

  (14) A method of manufacturing a semiconductor device is a method of manufacturing a semiconductor device having a DRAM memory cell and a peripheral MOS transistor, wherein the word of the DRAM memory cell is formed on a semiconductor substrate on which an element isolation insulating film and an element formation region are formed. A step of forming a transistor and the peripheral MOS transistor, a step of forming an insulating film serving as a first etching stopper layer on the impurity diffusion region and the gate electrode of the peripheral MOS transistor forming region, and on the first etching stopper layer Burying and planarizing the space of the word transistor of the DRAM memory cell with an interlayer insulating film different from the first etching stopper layer, forming a second etching stopper layer on the interlayer insulating film, and The DRAM memory cell capacity is formed on the second etching stopper layer. Forming an insulating film on the capacitor, forming an opening on the insulating film, and temporarily stopping etching on the second etching stopper layer; and (2) etching and removing the etching stopper layer and the interlayer insulating film, and further stopping the etching on the first etching stopper layer; and etching and removing the first etching stopper layer in the opening; Is formed on the boundary between the impurity diffusion layer and the element isolation insulating film, and the depth dimension of the bottom of the opening from the upper surface of the element isolation insulating film is the same as that of the first etching stopper layer. Forming a step smaller than the thickness, forming an electrode layer in the opening, and forming a metal wiring layer connected to the electrode layer The method of manufacturing a semiconductor device that includes a degree.

  (15) A method of manufacturing a semiconductor device is a method of manufacturing a semiconductor device having a DRAM memory cell and a peripheral MOS transistor, wherein the word of the DRAM memory cell is formed on a semiconductor substrate on which an element isolation insulating film and an element formation region are formed. A step of forming a gate electrode of the transistor and the gate electrode of the peripheral MOS transistor, and an insulating film that forms a sidewall forming layer covering the gate electrode of the word transistor of the DRAM memory cell and the gate electrode of the peripheral MOS transistor. Forming a sidewall on the gate sidewall of the peripheral MOS transistor by anisotropically etching the sidewall formation layer only in the peripheral MOS transistor formation region, and forming the sidewall formation layer in the DRAM memory cell formation region. And the peripheral MOS transistor An insulating film serving as a first etching stopper layer is formed on the impurity diffusion region of the star formation region and the gate electrode, and the film thickness of the laminated film of the sidewall formation layer and the first etching stopper layer is the word transistor of the DRAM memory cell. And forming a film having a film thickness of ¼ or more and ½ or less of the minimum interval of the first and second word lines of the DRAM memory cell by an interlayer insulating film different from the first etching stopper layer on the first etching stopper layer. A step of filling and planarizing a space of the transistor, a step of forming a second etching stopper layer on the interlayer insulating film, a step of forming a capacitor of the DRAM memory cell on the second etching stopper layer, and the capacitor Forming an insulating film thereon; forming an opening on the insulating film; and the second etching stopper. A step of once stopping etching, a step of etching and removing the second etching stopper layer and the interlayer insulating film in the opening, and a step of stopping etching once on the first etching stopper layer; and the opening A method of manufacturing a semiconductor device comprising: a step of etching and removing the first etching stopper layer; a step of forming an electrode layer in the opening; and a step of forming a metal wiring layer connected to the electrode layer.

  (16) A method for manufacturing a semiconductor device is the same as the method for manufacturing a semiconductor device having a DRAM memory cell and a peripheral MOS transistor described in (15) above. And the film thickness of the first etching stopper layer is ¼ or more and 1 / or less of the minimum distance between the word transistors of the DRAM memory cell.

  (17) A method of manufacturing a semiconductor device is a method of manufacturing a semiconductor device having a DRAM memory cell and a peripheral MOS transistor, wherein the word of the DRAM memory cell is formed on a semiconductor substrate on which an element isolation insulating film and an element formation region are formed. A step of forming a transistor and the peripheral MOS transistor, a step of forming an insulating film serving as a first etching stopper layer on the impurity diffusion region and the gate electrode of the peripheral MOS transistor formation region, and a step on the first etching stopper layer Burying and planarizing the space of the word transistor of the DRAM memory cell with an interlayer insulating film different from the first etching stopper layer, forming a second etching stopper layer on the interlayer insulating film, and The DRAM memory cell capacity is formed on the second etching stopper layer. Forming an insulating film on the capacitor, forming an opening on the insulating film, and temporarily stopping etching on the second etching stopper layer; and (2) etching and removing the etching stopper layer and the interlayer insulating film, and further stopping the etching on the first etching stopper layer; and etching and removing the first etching stopper layer in the opening; Is formed on the boundary between the gate electrode and the sidewall insulating film, and the depth dimension from the upper surface of the element isolation insulating film at the bottom of the opening formed on the sidewall insulating film is A step of forming the element isolation insulating film smaller than a depth dimension, a step of forming an electrode layer in the opening, and a contact with the electrode layer. And a step of forming a metal interconnection layer to be.

  (18) A method of manufacturing a semiconductor device is a method of manufacturing a semiconductor device having a DRAM memory cell and a peripheral MOS transistor. The word transistor of the DRAM memory cell is formed on a semiconductor substrate on which an element isolation insulating film and an element formation region are formed. Forming the peripheral MOS transistor, forming an insulating film serving as a first etching stopper layer on the impurity diffusion region and the gate electrode of the peripheral MOS transistor forming region, and forming the insulating film on the first etching stopper layer. A step of filling and planarizing the space of the word transistor of the DRAM memory cell with an interlayer insulating film different from the first etching stopper layer; and a second layer thicker than the film thickness of the first etching stopper layer on the interlayer insulating film. A step of forming an etching stopper layer, and the second etching step Forming a capacitor of the DRAM memory cell on the upper layer, forming an insulating film on the capacitor, forming an opening on the insulating film, and etching the second etching stopper layer once; , A step of etching away the second etching stopper layer and the interlayer insulating film in the opening, and a step of temporarily stopping etching on the first etching stopper layer, and the first in the opening. A step of etching away the etching stopper layer; a step of forming an electrode layer in the opening; and a step of forming a metal wiring layer connected to the electrode layer.

  (19) A method of manufacturing a semiconductor device is a method of manufacturing a semiconductor device having a DRAM memory cell and a peripheral MOS transistor, wherein the word of the DRAM memory cell is formed on a semiconductor substrate on which an element isolation insulating film and an element formation region are formed. A step of forming a transistor and the peripheral MOS transistor, a step of forming an insulating film serving as a first etching stopper layer on the impurity diffusion region and the gate electrode of the peripheral MOS transistor formation region, and a step on the first etching stopper layer Burying and planarizing the space of the word transistor of the DRAM memory cell with an interlayer insulating film different from the first etching stopper layer, forming a second etching stopper layer on the interlayer insulating film, and The DRAM memory cell capacity is formed on the second etching stopper layer. Forming an insulating film on the capacitor, forming a first opening on the insulating film and on the gate electrode of the peripheral MOS transistor, and on the second etching stopper layer A step of temporarily stopping etching, a step of etching and removing the second etching stopper layer and the interlayer insulating film in the first opening, and a step of stopping etching once on the first etching stopper layer; and the opening Etching the first etching stopper layer in the portion, removing the first etching stopper layer in the first opening, and forming the insulating film formed on the capacitor on the insulating film and on the insulating film. A second opening is formed on the impurity diffusion region of the peripheral MOS transistor, and the second etching stopper layer is formed. The step of temporarily stopping etching, the step of etching away the second etching stopper layer and the interlayer insulating film in the second opening, and the step of temporarily stopping etching on the first etching stopper layer; A step of etching and removing the first etching stopper layer in the second opening; a step of forming an electrode layer in the second opening; and a step of forming a metal wiring layer connected to the electrode layer. ing.

  (20) A method of manufacturing a semiconductor device is a method of manufacturing a semiconductor device having a DRAM memory cell and a peripheral MOS transistor, wherein the word of the DRAM memory cell is formed on a semiconductor substrate on which an element isolation insulating film and an element formation region are formed. A step of forming a transistor and the peripheral MOS transistor, a step of forming an insulating film serving as a first etching stopper layer on the impurity diffusion region and the gate electrode of the peripheral MOS transistor formation region, and a step on the first etching stopper layer Burying and planarizing the space of the word transistor of the DRAM memory cell with an interlayer insulating film different from the first etching stopper layer, and forming the second etching stopper layer on the interlayer insulating film; Can be removed by isotropic etching on the second etching stopper layer Forming an insulating film, forming an opening selectively in the insulating film removable by isotropic etching, and forming a capacitor lower electrode of the DRAM memory cell in the opening; Etching the insulating film that can be removed by isotropic etching using the second etching stopper layer as a stopper for isotropic etching; forming a capacitor dielectric film and a capacitor upper electrode on the capacitor lower electrode; A step of forming an insulating film on the capacitor upper electrode, a step of forming an opening on the insulating film and temporarily stopping etching on the second etching stopper layer, and a second etching stopper in the opening. And the interlayer insulating film are removed by etching, and the etching is temporarily stopped on the first etching stopper layer. A step of etching and removing the first etching stopper layer in the opening, a step of forming an electrode layer in the opening, and a step of forming a metal wiring layer connected to the electrode layer. ing.

  (21) A method of manufacturing a semiconductor device is a method of manufacturing a semiconductor device having a DRAM memory cell and a peripheral MOS transistor, wherein the word of the DRAM memory cell is formed on a semiconductor substrate on which an element isolation insulating film and an element formation region are formed. A step of forming a transistor and the peripheral MOS transistor, a step of forming an insulating film serving as a first etching stopper layer on the impurity diffusion layer and the gate electrode in the peripheral MOS transistor formation region, and the top of the first etching stopper layer A step of filling and planarizing the space of the word transistor of the DRAM memory cell with an interlayer insulating film different from the first etching stopper layer, and forming an opening in the interlayer insulating film formed on the DRAM memory cell. Forming an electrode layer connected to the impurity diffusion region of the DRAM memory cell. A step of forming an interlayer insulating film on the electrode layer, a step of forming a second etching stopper layer on the interlayer insulating film, and an electrode layer connected to the impurity diffusion region of the DRAM memory cell. Forming an opening in the second etching stopper layer; forming a sidewall on the side wall of the opening; forming an etching mask having a smaller contact hole diameter than the opening; and etching using the etching mask Forming an opening on the electrode layer connected to the impurity diffusion region of the DRAM memory cell, and forming a DRAM capacitor connected to the impurity diffusion region of the DRAM memory cell through the opening; Forming an insulating film on the capacitor; forming an opening on the insulating film; and temporarily forming an opening on the second etching stopper layer. A step of stopping the chucking, a step of etching and removing the second etching stopper layer and the interlayer insulating film in the opening, and a step of stopping the etching once on the first etching stopper layer, and the step of (1) A step of etching and removing the etching stopper layer, a step of forming an electrode layer in the opening, and a step of forming a metal wiring layer connected to the electrode layer.

  (22) A method of manufacturing a semiconductor device is a method of manufacturing a semiconductor device having a DRAM memory cell and a peripheral MOS transistor, wherein the word of the DRAM memory cell is formed on a semiconductor substrate on which an element isolation insulating film and an element formation region are formed. A step of forming a transistor and the peripheral MOS transistor, a step of forming an insulating film serving as a first etching stopper layer on the impurity diffusion layer and the gate electrode in the peripheral MOS transistor formation region, and the top of the first etching stopper layer A step of filling and planarizing the word transistor space of the DRAM memory cell with an interlayer insulating film different from the first etching stopper layer, and forming an opening in the interlayer insulating film formed on the DRAM memory cell. Forming an electrode layer connected to the impurity diffusion region of the DRAM memory cell. A step of forming an interlayer insulating film covering the electrode layer, a step of forming a second etching stopper layer on the interlayer insulating film, and an electrode layer connected to the impurity diffusion region of the DRAM memory cell. Forming an opening in the second etching stopper layer; forming a sidewall on the side wall of the opening; forming an etching mask having a smaller contact hole diameter than the opening; and etching using the etching mask Forming an opening on the electrode layer connected to the impurity diffusion region of the DRAM memory cell, and forming a DRAM capacitor lower electrode connected to the impurity diffusion region of the DRAM memory cell through the opening. And forming a capacitor dielectric film and a capacitor upper electrode on the DRAM capacitor lower electrode, A step of removing at least a part of the second etching stopper layer during etching of the pole, a step of forming a third etching stopper layer on the DRAM capacitor lower electrode, and an insulating film on the third etching stopper layer Forming the opening, forming an opening on the insulating film and temporarily stopping the etching on the third etching stopper layer; etching removing the third etching stopper layer and the interlayer insulating film in the opening; Furthermore, a step of temporarily stopping etching on the first etching stopper layer, a step of etching and removing the first etching stopper layer in the opening, a step of forming an electrode layer in the opening, and the electrode Forming a metal wiring layer connected to the layer.

  (23) A method of manufacturing a semiconductor device is a method of manufacturing a semiconductor device having a DRAM memory cell and a peripheral MOS transistor, wherein the word of the DRAM memory cell is formed on a semiconductor substrate on which an element isolation insulating film and an element formation region are formed. A step of forming a transistor and the peripheral MOS transistor, a step of forming an insulating film serving as a first etching stopper layer on the impurity diffusion layer and the gate electrode in the peripheral MOS transistor formation region, and the top of the first etching stopper layer Burying and planarizing the space of the word transistor of the DRAM memory cell with an interlayer insulating film different from the first etching stopper layer, forming a second etching stopper layer on the interlayer insulating film, and A capacitor of the DRAM memory cell on the second etching stopper layer A step of forming an insulating film on the capacitor, a step of forming an opening on the insulating film and temporarily stopping etching on the second etching stopper layer, and a second step in the opening. Etching and removing the etching stopper layer and the interlayer insulating film, and further stopping the etching on the first etching stopper layer; and etching and removing the first etching stopper layer in the opening; At least one is formed on the boundary between the impurity diffusion layer and the element isolation insulating film, and the depth from the upper surface of the element isolation insulating film at the bottom of the opening is the junction depth of the impurity diffusion layer. A step of forming smaller than the size, a step of forming an electrode layer in the opening, and a step of forming a metal wiring layer connected to the electrode layer. To have.

  As described above, according to the semiconductor device and the manufacturing method thereof of the present invention, the overetching of the semiconductor substrate is suppressed by stopping the etching with the multilayer etching stopper layer in which each film thickness is optimized. Can be suppressed.

  By embedding a DRAM cell using an etching stopper layer with an optimized film thickness, it is possible to prevent the generation of voids (cavities) in the buried interlayer insulating film between word transistors, which is a feature of DRAM cells. The self-aligned contact in the DRAM cell can be stably formed without short-circuiting through the void.

  The etching stopper formed under the DRAM cell can also be used as an etching mask for forming a contact for connecting the capacitor of the DRAM cell and the substrate, so that the process can be greatly reduced.

  Furthermore, since the obtained stopper under the DRAM cell can also be used as an etching stopper when forming the cylinder type capacitor, the process can be further greatly reduced.

  Since the etching stopper formed under the DRAM cell can suppress the intrusion of moisture from the interlayer insulating film on the DRAM cell, the trench characteristic under the DRAM cell can be stabilized.

102 ... device isolation insulating film, 111 ... gate electrode, 113 ... impurity diffusion layer, 121 ... first etching stopper layer, 122 ... second etching stopper layer, 131 ... electrode layer, t J ... junction depth of the impurity diffusion layer , T S ... depth from the impurity diffusion layer surface at the bottom of the electrode layer

Claims (3)

  1. In a semiconductor device having a DRAM memory cell and a peripheral MOS transistor,
    An insulating film serving as a first etching stopper layer is formed so as to cover the surface including the gate electrode of the peripheral MOS transistor,
    A second etching stopper layer is formed as an upper layer or a lower layer of the capacitor portion of the DRAM memory cell;
    The impurity diffusion layer and the gate electrode of the peripheral MOS transistor are connected to a metal wiring layer formed on the capacitor layer of the DRAM memory cell by an electrode layer that penetrates the first etching stopper layer and the second etching stopper layer. And
    The electrode layer is connected to at least one of the impurity diffusion layers on a boundary between at least one of the impurity diffusion layers and the element isolation insulating film;
    The depth dimension from the surface of the impurity diffusion layer at the bottom of the electrode layer formed on the element isolation insulating film is either the junction depth dimension of the impurity diffusion layer or the thickness of the first etching stopper layer. Shorter than one,
    The impurity diffusion layer and the gate electrode of the peripheral MOS transistor are metal wirings formed on the capacitor part upper layer of the DRAM memory cell by a second electrode layer penetrating the first etching stopper layer and the second etching stopper layer, respectively. Connected with the layer,
    The second electrode layer is connected to the gate electrode on a boundary between the gate electrode and a sidewall insulating film formed on a side wall of the gate electrode,
    The depth dimension from the upper surface of the element isolation insulating film at the bottom of the second electrode layer formed on the sidewall insulating film is shorter than the depth dimension of the bottom of the element isolation insulating film. Semiconductor device.
  2. A sidewall forming layer of the peripheral MOS transistor and the first etching stopper layer are stacked on the word transistor in the DRAM memory cell region,
    The film thickness of the laminated film of the sidewall formation layer of the peripheral MOS transistor and the first etching stopper layer is set to ¼ or more and ½ or less of the minimum distance between the word transistors in the DRAM memory cell region. The semiconductor device according to claim 1.
  3. In a semiconductor device having a DRAM memory cell and a peripheral MOS transistor,
    An insulating film serving as a first etching stopper layer is formed on the impurity diffusion region and the gate electrode in the peripheral MOS transistor region,
    A second etching stopper layer is formed on the upper layer or the lower layer of the capacitor portion of the DRAM memory cell, or on the upper layer and the lower layer of the capacitor portion of the DRAM memory cell;
    The impurity diffusion layer and the gate electrode of the peripheral MOS transistor are formed of an electrode layer penetrating the first etching stopper layer and the second etching stopper layer, respectively, and a metal wiring layer formed on the capacitor layer of the DRAM memory cell. Connected,
    2. The semiconductor device according to claim 1, wherein the film thickness of the second etching stopper layer is formed larger than the film thickness of the first etching stopper layer.
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