JPH1079491A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stably realize a DRAM having a high degree of integration, without deteriorating the reliability by forming a plug for connecting a storage electrode after forming a word line and by forming a storage electrode between bit lines in a self-aligned contact manner. SOLUTION: An oxide film 11 is etched to thereby expose the surface of a substrate. A word line structure is left, a doped silicon layer is embedded in a contact hole 15, and a plug 16 for connecting a storage electrode is formed. A contact part HB of a bit line is formed, a bit line 22 is formed, and a BPSG film 26, an Si3 N4 film 25, and an SiO2 film 24 are sequentially selectively removed, thereby forming a contact hole HC for the storage electrode. In a manner similar to the case for forming the contact hole 15 for the plug 16, a self alignment by the SiO2 film 24 and the Si3 N4 film 25 covering the bit line structure is performed. Subsequently, a doped silicon layer is formed on the entire face, and a storage electrode layer 27 is formed in the contact hole HC.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a DRAM (Dynamic).
The present invention relates to a semiconductor device that contributes to high integration and high reliability of Random Access Memory and a method of manufacturing the same.

[0002]

2. Description of the Related Art In order to achieve high integration and low cost of a DRAM, it is necessary to miniaturize a cell which is a basic component thereof. A general DRAM cell is composed of one MOSFET and one capacitor.

A major problem in miniaturizing a cell is how to secure a large capacitor capacity with a small cell size.

In recent years, as a method for securing the capacitance of a capacitor, a trench type capacitor in which a groove is formed in a substrate and a capacitor is formed therein, and a stack type capacitor in which a capacitor is formed three-dimensionally above a MOSFET have been proposed. , And are also used in actual DRAMs. Further, a stacked capacitor is formed by forming a plurality of storage electrodes arranged in a direction substantially parallel to the substrate, and using a FIN type capacitor using upper and lower surfaces of each storage electrode as a capacitor or a cylinder type using a cylindrical storage electrode. Improved cell structures such as capacitors have been proposed.

[0005] By applying these cell structures and their manufacturing processes, a DR having a degree of integration of about 64 MBIT can be obtained.
It has become possible to realize AM.

However, in a trench capacitor, a voltage applied to a capacitor electrode greatly expands a charge storage region formed of a depletion layer formed around the trench, so that adjacent capacitor trenches are provided close to each other. In this case, a phenomenon occurs that information is lost due to leakage of accumulated charges. For this reason, it is necessary to increase the width of the isolation region between the cells, that is, the width of the region where the field oxide film is provided, which hinders an improvement in the degree of integration.

Therefore, a stacked capacitor is promising as a device contributing to high integration and high reliability of DRAM.

As a miniaturized stack type capacitor, “A 0.29-μm 2 MIM-CROWN Cell”
and Process Technologies
for1-Gigabit DRAMs "1994, 9th
Pages 27 to 929 have been reported.

FIG. 29 is a sectional view of the memory cell.
In the figure, reference numeral 100 is a WSi ₂ / polySi word line, 101 is a first polysilicon plug, 102 is a WSi ₂ / polySi bit line formed on the poly Si plug, 103 is a second polysilicon plug, 104 cylindrical storage electrode of W, 105Ta ₂ O ₅ dielectric layer, 106 denotes an opposing electrode of the CVD-TiN.

By using the above-mentioned cylinder type capacitor, a DRAM with a high degree of integration can be provided.

However, when the above-mentioned cylinder type capacitor is employed, the height of the capacitor portion needs to be further increased in order to secure a sufficient capacitor capacity with a smaller cell area as well as miniaturization. Therefore, a height difference between the cell portion and the peripheral circuit portion, that is, a step difference is a serious problem. For example, when patterning a metal wiring on a cell portion and a peripheral circuit portion, the depth of focus of photolithography is insufficient due to a step, so that dimensional accuracy is reduced.

It is conceivable to eliminate the step between the cell portion and the peripheral circuit portion by embedding an insulating film in the peripheral circuit portion. However, the aspect ratio of the contact in the peripheral circuit portion becomes large, and the control of etching becomes difficult. Another problem arises:

Further, as the miniaturization progresses, the interval between the wirings becomes smaller and the parasitic capacitance of the wiring tends to increase.

[0014] The object of the present invention is [for example, 256MDRA
It is an object of the present invention to provide a semiconductor device capable of stably realizing a highly integrated DRAM (M or more) without deteriorating its reliability and a method of manufacturing the same.

According to one aspect of the present invention, in a semiconductor device having a memory cell region and a peripheral circuit region on a semiconductor substrate, a pair of impurity diffusion regions formed in the substrate, and a pair of impurity diffusion regions formed on the substrate surface. A transfer transistor including a gate electrode, a first insulating film covering an upper surface and side surfaces of the gate electrode, a second insulating film formed on the substrate so as to cover the first insulating film, Penetrating the second insulating film,
A pair of contact holes reaching the pair of impurity diffusion regions, a conductive plug filled in one of the pair of contact holes, and connected to one of the pair of impurity diffusion regions; A third insulating film formed on the second insulating film and having a first opening on the other of the pair of contact holes; and a third insulating film formed on the third insulating film and A bit line connected to the other of the pair of impurity diffusion regions via the other of the pair of contact holes, a fourth insulating film covering an upper surface and a side surface of the bit line, and a fourth insulating film covering a side surface of the bit line. A second opening formed in the third insulating film in alignment with the third insulating film, and electrically connected to the conductive plug through the second opening, the third and fourth insulating films Is isolated from the bit line by A storage electrode formed to extend in Tsu preparative line above, a dielectric film formed on the storage electrode surface,
A semiconductor device having a counter electrode formed on the surface of the dielectric film is provided.

According to another aspect of the present invention, in a method of manufacturing a semiconductor device having a memory cell region and a peripheral circuit region on a semiconductor substrate, a pair of impurity diffusion regions and a gate electrode are formed on the substrate. Forming a transfer transistor including the transfer transistor, forming a first insulating film covering an upper surface and side surfaces of the gate electrode, and forming a second insulating film covering the first insulating film and the transfer transistor. When,
Forming a contact hole penetrating through the second insulating film and reaching at least one of the pair of impurity diffusion regions; filling the contact hole with a conductive layer to form a conductive plug for connecting a storage electrode; Forming a third insulating film on the second insulating film, covering the conductive plug, forming a bit line on the third insulating film, and forming an upper surface of the bit line. Forming an opening in the third insulating film on the conductive plug in alignment with the fourth insulating film; and forming an electrical connection with the conductive plug. A method of manufacturing a semiconductor device, comprising: a step of forming a storage electrode connected to a substrate, a step of forming a dielectric film on the surface of the storage electrode, and a step of forming a counter electrode on the surface of the dielectric film.

A structure is used in which a single plug made of a conductive layer raises once. That is, after the word line is formed, a plug for connection of the storage electrode for raising is formed, and the SAC (Self Aligned Contact) is formed.
Since the storage electrode is formed between the bit lines by t),
The height of the capacitor from the substrate surface can be reduced.

Therefore, the height difference between the cell portion and the peripheral circuit portion can be suppressed as compared with the related art, and the contact hole can be easily formed in the peripheral circuit portion.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] A first embodiment of the present invention is shown in FIGS. 1A to 2H.

In the figure, reference numeral 1 denotes a p-type silicon substrate, 2
Is the field SiO_TwoFilm, 3 is a gate oxide film, 4 is a silicon oxide film.
5 is a tungsten silicide (WSi) layer;
Is SiO_Two7 is a SiON film, 8 is a gate electrode (workpiece).
9 is n.^-Type impurity diffusion layer, 1
0 is sidewall, 11 is SiO_TwoFilm, 12 is Si _Three
N_FourFilm 13 is borophosphosilicate glass (BPS)
G) film, 14 is Si_ThreeN _FourMembrane, 15 is contact hole
, 16 is a conductive plug, 17 is SiO_TwoMembrane, 18
Recon layer, 19 is WSi, 20 is SiO_TwoMembrane, 21 is S
iON film, 22 is a bit line (second layer wiring), 23 is a size
Wall, 24 is SiO_TwoFilm, 25 is Si _ThreeN_Fourfilm,
27 is a storage electrode, and 29 is a Ta serving as a capacitor dielectric film.
_TwoO_FiveFilm, 30 is TiN to be a counter electrode, 31 is interlayer insulation
The BPSG film serving as an edge film is shown. N1, P1, P2
Indicates an n-well, a p-well, and a p-well, respectively. Less than
Below, illustration of these wells is omitted.

FIG. 1A is a plan view of a memory cell portion of the semiconductor device according to the present embodiment. In the figure, word lines 8 are arranged vertically, and bit lines 22 are arranged horizontally thereon.
The capacitor C is disposed thereon.

FIG. 1B is a cross-sectional view of the memory cell portion corresponding to FIG. 1A, and shows a cross section taken along line AA 'and BB' in FIG. 1A). The AA ′ section intersects both the word line and the bit line, and the BB ′ section intersects the bit line and is parallel to the word line. For convenience, AA 'part and BB'
And parts are shown continuously.

2A to 6 are sectional views of the semiconductor substrate for explaining the method for fabricating the semiconductor device according to the present embodiment.
The left side of the drawing is the memory cell section MC, and the right side is the peripheral circuit section P
C. The memory cell unit MC corresponds to FIG. 1B. An n-well N2 is also formed in the peripheral circuit section PC. Hereinafter, a method for manufacturing the semiconductor device of the first embodiment will be described with reference to the drawings.

Referring to FIG. 2A, LOCOS isolation (selective oxidation) is performed on the p-type silicon substrate 1 by using a known technique, and a field SiO ₂ film 2 having a thickness of 250 nm is formed. An SiO ₂ film 3 serving as a gate oxide film having a thickness of 5 to 10 nm is formed.

Next, a doped silicon layer 4 having a thickness of 50 nm containing a high concentration of n-type or p-type impurities, a WSi layer 5 having a thickness of 120 nm, and a thickness of 80
An SiO ₂ film 6 having a thickness of nm is sequentially formed. Note that the doped silicon layer 4 can use any of single crystal silicon, polycrystalline silicon, and amorphous silicon.

Next, a film having an appropriate absorption for the exposure wavelength used for phytolithography, for example, a SiON film 7 having a thickness of about 30 nm is formed thereon by a plasma CVD method as an antireflection film.

Further, using a patterned resist mask (not shown), the SiON film 7 and the SiO ₂ film 6 are made of an etchant gas containing, for example, F, and the WSi layer 5 and the polycrystalline silicon layer 4 are made of, for example, Cl. The gate electrode 8 is formed by selectively removing each with an etchant gas. Note that the gate electrode 8 becomes a word line.

Referring to FIG. 2B, using gate electrode 8 as a mask, P (phosphorus) ions are implanted into silicon substrate 1 to form n ⁻ -type impurity diffusion layer 9. The n ⁻ -type impurity diffusion layer 9 serves as a source and a drain of the transfer transistor in the cell portion, and serves as an LDD diffusion layer of the n-channel transistor in the peripheral circuit portion. Then, low pressure CVD
The SiO ₂ film having a thickness of 60nm was formed on the entire surface by law, by anisotropic etching to form a side wall 10 made of SiO _2.

An n ⁺ diffusion layer 55 is formed by implanting arsenic ions into the n channel transistor region of the peripheral circuit portion, and p ⁺ ions are implanted by implanting boron ions into the p channel transistor region in the peripheral n well N2. The diffusion layer 57 is formed. Hereinafter, illustration of the diffusion layer is omitted as appropriate.

Referring to FIG. 2C, an SiO ₂ film 11 having a thickness of 20 nm and a thickness of 50 to 10
A Si ₃ N ₄ film 12 having a thickness of 0 nm, preferably 80 nm is formed.

Next, as a flattening film, a thickness of 300
A BPSG film 13 having a thickness of about 400 nm is formed, and the BPSG film 13 is reflowed by a heat treatment at about 800 ° C. in a nitrogen atmosphere. In addition, in order to completely planarize, CMP
(Chemical Mechanical Poli
Preferably, the surface is polished by shing to planarize the surface.

Further, instead of the BPSG film, phosphosilicate glass (PSG), spin-on glass (SOG),
An insulating resin or the like can also be used.

SiO_TwoThe film 11 is made of Si_ThreeN_FourRemove film 12
Becomes a stopper film when_ThreeN_FourThe membrane 12 is BPS
It becomes a stopper film when the G film 13 is removed. At this time,
Si _ThreeN_FourIf the thickness of the film 12 is increased, Si_ThreeN
_FourThe dielectric constant of the film is SiO_TwoBecause it is higher than the film,
Will increase in capacity. As an etching stopper
If the function can be secured, Si_ThreeN_FourThinner film 12
Is preferred.

Referring to FIG. 2D, an Si ₃ N ₄ film 14 having a thickness of 50 nm is formed on the entire surface by a low-pressure CVD method, and S ₃ N ₄ is formed using a patterned resist mask (not shown).
The i ₃ N ₄ film 14 is selectively removed. Next, BPSG
The film 13 is selectively etched to stop when the Si ₃ N ₄ film 12 is partially removed, and subsequently the Si ₃ N ₄ film 12
The O ₂ film 11 is selectively removed. The opening subordinates Si ₃ Si by selective etching of the N ₄ film 12 ₃ N ₄ film 14 holes leaving the SiO ₂ film 11 is formed. Then, S
The substrate surface is exposed by performing selective etching of iO ₂ . The sidewall 10 remains almost without being etched.

The area between adjacent word lines will be considered in more detail. In the state of FIG. 2C, the upper surface of the word line is covered with an oxide film 6 and a SiON film 7. The side surface of the word line is covered with a silicon oxide sidewall 10.
An oxide film 11 and a nitride film 12 are formed on the entire surface of the substrate so as to cover the word line structure. In addition, BPSG
A film 13 is formed. When a region between adjacent word line structures is viewed from above, a BPSG film 13, a nitride film 12, and an oxide film 11 are present in a downward convex shape in this order. These films can be selectively etched one by one from above. BPSG film 13 using photoresist mask
Is selectively etched anisotropically, the etching ends with the nitride film 12 exposed at the bottom surface. Since the nitride film 12 and the oxide film 11 are formed conformally along the side wall of the word line and the surface of the substrate, the etching is finished according to the shapes. Next, when the selective etching of the nitride film 12 is performed, the etching is completed with the oxide film 11 exposed. In this state, the region between the word line structures is
Is occupied by the etched openings leaving behind. Thin oxide film 11
Etching exposes the substrate surface. The word line structure remains almost completely.

Thus, the contact hole 15 is formed by SAC. Next, by the low pressure CVD method,
A doped silicon layer having a thickness of 300 nm is embedded in the contact hole 15, and the doped silicon layer on the Si ₃ N ₄ film 14 is removed by a CMP method.
b is formed. The plug 16b is for a bit line contact, and the plug 16a is for a storage electrode contact.
Hereinafter, the plug 16 indicates both the plugs 16a and 16b.

In addition to doped silicon, W, TiN
The plug 16 can also be formed by using the method described above. The W or TiN layer can be deposited by CVD.

Referring to FIG. 2E, the entirety is formed by a low pressure CVD method.
On the surface, a 20 to 60 nm thick SiO _TwoForm the film 17
You. The oxide film 17 is preferably formed of a dense high-temperature oxide film.
Good. Such films have conformal properties
You. A flat film is formed because the base surface is flattened
Is done. This SiO_TwoThe membrane 17 is placed where necessary.
The lug 16 is insulated from the bit line serving as the second layer wiring. Next
Then, a patterned resist mask (not shown)
By the SiO_TwoThe film 17 is selectively removed to form a bit line
Is formed. Peripheral circuit on the right in the figure
Also, the contact between the plug 16 and the upper wiring is opened.
Mouth. Next, a thickness of 40 is formed on the entire surface by a low pressure CVD method.
nm doped silicon layer 18, WS 120 nm thick
i-layer 19, 120 nm thick SiO_TwoMembrane 20, plasma
An SiON film 21 to be an antireflection film is sequentially formed by a CVD method.
Form. Next, the patterned resist mask
(Not shown) to selectively remove each layer
A bit line 22 is formed. Necessary for peripheral circuits
Accordingly, a wiring connected to the lower plug is formed.

Further, a thickness of 6
Forming a SiO ₂ film of 0 nm, to form a side wall 23 made of SiO ₂ by anisotropic etching.

Referring to FIG. 2F, the entirety is formed by a low pressure CVD method.
On the surface, a 10-30 nm thick SiO _TwoFilm 24, thickness 60
~ 100nm Si_ThreeN_FourA film 25 is formed.

Referring to FIG. 2G, a BPSG film 26 having a thickness of 1000 to 1500 nm is formed on the entire surface as a flattening film, and the BPSG film 26 is reflowed by a heat treatment at 800 ° C. in a nitrogen atmosphere. Note that, in order to perform planarization completely, it is preferable to planarize the surface by polishing it by a CMP method.

SiO_TwoThe film 24 is made of Si_ThreeN_FourRemove membrane 25
It is a stopper film when removing
To achieve. In addition, Si_ThreeN_FourThe film 25 is a BPSG film 26
It becomes a stopper film at the time of removal. At this time, Si_ThreeN_Four
If the thickness of the film 25 is increased, Si_ThreeN_FourFilm dielectric
Rate is SiO_TwoBecause of the higher than that of the film,
The amount increases. Function as an etching stopper
As long as _ThreeN_FourThe thinner the film 25, the better
Good.

Next, the BPSG film 26, the Si ₃ N ₄ film 25, and the SiO ₂ film 24 are selectively removed sequentially using a patterned resist mask (not shown) to form contact holes HC for forming storage electrodes. To form As in the case of forming the contact hole 15 for the plug 16, self-alignment by the SiO ₂ film 24 and the Si ₃ N ₄ film 25 covering the bit line structure is performed.

Next, a thickness of 6
A 0 nm doped silicon layer is formed, and a storage electrode layer is formed in a contact hole for forming a storage electrode. After applying a resist 28 so as to fill the remaining holes, CMP
The silicon layer on the BPSG film 26 is removed by polishing the surface by the method, and the storage electrode 27 is formed.

The resist 28 in the storage electrode 27 is removed. Next, a Si ₃ N ₄ film 25 and a silicon storage electrode 2
The BPSG film 26 is removed by HF wet etching using 7 as an etching stopper, and the outer surface of the storage electrode 27 is also exposed.

Referring to FIG. 2H, high-speed nitriding (RTN:
Rapid Thermal Nitridatio
According to n), the surface of the storage electrode 27 is nitrided. Then
A Ta ₂ O ₅ film 29 having a thickness of 5 to 15 nm is formed by a low pressure CVD method, and an oxidizing heat treatment at about 800 to 850 ° C. or oxygen plasma annealing is performed. Thus, the dielectric film 29 of the capacitor is formed.

Further, a counter electrode 30 is formed by forming a 50 nm-thick TiN serving as a counter electrode on the entire surface by a low-pressure CVD method, and performing etching using a patterned resist mask (not shown) as a mask. .

Thereafter, through the steps of forming an interlayer insulating film and opening a contact hole, the structure of FIG. 1B is obtained. Further, a stacked capacitor is manufactured through steps such as wiring layer formation.

In this embodiment, the plug 1 made of a conductive layer
6, the structure is raised once. In other words, the connection plug 1 for raising after the word line is formed.
6, and the storage electrode 27 is formed between the bit lines by SAC. Therefore, the capacitor height can be reduced by the wiring structure of the bit line.

Therefore, the height difference between the cell portion and the peripheral circuit portion can be suppressed, and the contact hole can be easily formed in the peripheral circuit portion.

In this embodiment, as shown in FIG. 1A, the contact hole of the storage electrode is opened in a grid-like region surrounded by word lines and bit lines.

FIG. 3 is a plan view showing a step of forming plugs 16b and 16a in the bit line contact portion and the storage electrode contact portion, and corresponds to FIG. 2D.

For example, when the design rule is 0.2 μm, an insulating film such as a sidewall is formed with a thickness of 0.06 μm on one side in a region surrounded by 0.2 μm, that is, in a 0.2 μm square contact hole. If so,
It becomes a contact hole of 0.08 μm square. The problem at this time is etching, and it is extremely difficult to etch such a fine and deep contact hole.

In particular, highly integrated devices of 256 MDRAM or more (design rule is about 0.22 μm or less)
In order to increase the resolution, it is necessary to use an excimer stepper with a short wavelength, but that alone is not enough in terms of resolution and manufacturing margin,
Some sort of super-resolution technique is needed. Among them, the most influential is a method called a phase shift method, and a Levenson type phase shift method in which the phases of adjacent patterns are inverted by 180 ° is a method that is expected to be most effective.

However, the effect cannot be exerted unless the pattern conforms to the principle of inverting the phase of the adjacent pattern. Plug 16 shown in FIG.
In this layout, two storage electrode contacts 16b are adjacent to one bit line contact 16b in a triangular shape. The three contacts adjacent to each other cannot be out of phase with each other. Therefore, FIG.
It is difficult to apply the phase shift of the mold.

Also, the bit line needs to be in contact with the n-type diffusion layer in the peripheral circuit section (especially the sense amplifier). In that case, as shown in FIG.
Is also provided in the peripheral circuit section. That is, the contacts in the peripheral circuit portion have a contact structure of bit line / plug / n-type diffusion layer, and have two contact surfaces. Therefore, as compared with the case where the bit line directly contacts the diffusion layer, the value of the contact resistance increases,
There is a problem that contact resistance varies.

Further, in the peripheral circuit portion, the contact portions are scattered as compared with the memory cell portion, and have an isolated pattern. At this time, Le 16 is used for patterning the plug 16.
Even if a venson type phase shift is to be used, this method is not effective for an isolated pattern, but
If the exposure conditions (numerical aperture, σ value, exposure time) are optimized in order to obtain the effect of the nson-type phase shift, there is a problem that the contact hole cannot be opened unless the contact hole has a larger diameter.

[Second Embodiment] In the second embodiment, the plug 16 is formed only in the contact portion of the storage electrode, and
The effect of the venson type phase shift is obtained to form a contact hole in the storage electrode portion.

Further, the bit line is directly contacted with the peripheral circuit portion to suppress the variation in the contact resistance.

Hereinafter, the second embodiment will be specifically described with reference to the drawings. A second embodiment is shown in FIGS. 4A to 9I. In the drawings, the same reference numerals denote the same components, and a description of the steps corresponding to FIGS. 1A to 3 will be omitted.

8A are plan views of a memory cell according to the present embodiment. In the figure, a word line 8 extends in the vertical direction. 4B, 5B,... 8B are plan views of two MOS transistors of the peripheral circuit in the present embodiment.

9A to 9I are cross-sectional views of the chip for explaining the steps of manufacturing the semiconductor device according to the present embodiment. FIGS. 4A, 5A,...
4B, 5B,... 8B of the peripheral circuit PC in FIG.
-C 'section.

Referring to FIGS. 4A, 4B and 9A, a field oxide film 2 is formed on a p-type silicon substrate 1 by using the same technique as that described with reference to FIG. The gate electrode 8 is formed. Note that the gate electrode becomes a word line. Although the well structure is omitted, it is the same as FIG. 1B.

Referring to FIG. 9B, the description of FIG.
Using the same technique, the gate electrode 8 is used as a mask and n^-
Form impurity diffusion layer 9 is formed. Note that n^-Type impurity diffusion
The layer 9 becomes a source and a drain of the transfer transistor. Next
No, 60nm thick SiO _TwoForm film and anisotropic etch
By coating, SiO_TwoSidewall consisting of
Form 10.

Referring to FIG. 9C, the SiO ₂ film 11 and the Si ₃ N ₄ film 1 are formed by using the same technique as that described with reference to FIG. 2C.
Form 2

Next, a BPSG film 13 is formed as a flattening film, and the BPSG film 13 is reflowed by heat treatment.
Note that, in order to perform planarization completely, it is preferable to planarize the surface by polishing it by a CMP method.

Referring to FIGS. 5A, 5B and 9D, the decompression CV
A 50 nm thick Si ₃ N ₄ film 14 is formed on the entire surface by the D method. Next, a Si ₃ N ₄ film 14, a BPSG film 13, and a Si ₃ N ₄ film 14 are formed using a resist mask (not shown) patterned by applying a Levenson-type phase shift method.
_{The 3} N ₄ film 12 and the SiO ₂ film 11 are selectively removed to form only a contact hole 15 a for bringing the storage electrode into contact with the n ⁻ -type impurity diffusion layer 9. No contact hole for contacting the bit line with the n ⁻ -type diffusion layer 9 or a contact hole for a peripheral circuit is formed at this stage.

Further, a thickness of 300
A doped silicon layer of nm is buried in the contact hole 15a, and the doped silicon layer on the Si ₃ N ₄ film 14 is removed by a CMP method to form a conductive plug 16a.

Referring to FIGS. 6A, 6B and 9E, the decompression CV
The SiO ₂ film 1 having a thickness of 20 to 60 nm is entirely formed by the D method.
7 is formed. The SiO ₂ film 17 covers the surface of the plug 16a and insulates the plug 16a from the bit line serving as the second layer wiring.

Then, the SiO ₂ film 17, Si ₃ N ₄ film 14, BPSG film 13, Si ₃ N ₄ film 12, and SiO ₂ film 11 are selectively removed by using a patterned resist mask (not shown). Then, the contact hole 15b of the bit line 22 and the contact hole 15b of the peripheral circuit are simultaneously formed.

Referring to FIGS. 7A, 7B and 9E, the decompression CV
40 nm-thick doped silicon layer 1 over the entire surface by D method
8. A WSi layer 19 having a thickness of 120 nm, a SiO ₂ film 20 having a thickness of 120 nm, and a SiON film 21 serving as an antireflection film are sequentially formed by a plasma CVD method. Next, using a patterned resist mask (not shown), each layer is selectively removed to form a bit line 22.

Further, an SiO ₂ film having a thickness of 60 nm is formed on the entire surface of the substrate so as to cover the bit line structure by a low pressure CVD method, and a sidewall 23 made of SiO ₂ is formed by anisotropic etching.

[0074] Referring to FIG. 9F, using technology similar to that described in FIG. 2F, SiO ₂ film 24 on the entire surface of the substrate, Si
_{A 3} N ₄ film 25 is sequentially formed.

Referring to FIG. 9G, BPSG film 26 is formed using the same technique as that described with reference to FIG. 2G, and BPSG film 26 is reflowed by heat treatment. Note that, in order to perform planarization completely, it is preferable to planarize the surface by polishing it by a CMP method.

Referring to FIGS. 8A, 8B and 9G, BPSG
Film 26, Si_ThreeN_FourFilm 25, SiO _TwoFilm 24
To remove the contact hole for forming the storage electrode.
Form.

Further, after a doped silicon layer is formed and a resist 28 is applied so as to fill the contact hole for forming the storage electrode, the surface is polished by a CMP method to remove the silicon layer on the BPSG film 26. Then, the storage electrode 27 is formed.

Referring to FIG. 9H, the resist 28 in the storage electrode is removed using the same technique as that described with reference to FIG. 2H. Next, the BPSG film 26 is removed by wet etching using the Si ₃ N ₄ film 25 as an etching stopper, and the outer surface of the storage electrode is also exposed. The surface of the storage electrode 27 is nitrided by the RTN method. Next, the Ta ₂ O ₅ film 2
Then, an oxidation heat treatment or oxygen plasma annealing is performed.

Further, a TiN film to be a counter electrode is formed and patterned to form a counter electrode 30. Further, an interlayer insulating film 31 is formed of BPSG or the like, and the surface is flattened by performing reflow or CMP. A contact hole CH of a peripheral circuit is opened using a resist pattern.

Referring to FIG. 9I, barrier metal layer 32,
A DRAM device having a stacked capacitor is manufactured through a process such as forming a wiring composed of the main conductive layer 33 and the like.

In some cases, after the bit line 22 is formed, a plug for raising the height may be further formed. In this case, the height of the cell portion is higher than in the first embodiment. However, since the formation of the contact hole 15a of the storage electrode connection plug 16 is performed using a Levenson-type phase shift method, the contact can be easily formed. Holes can be formed.

According to the present embodiment, the contact hole 15b in the peripheral circuit portion is
Apart from a, the opening is formed at the same time as the contact hole 15b of the bit line, so that the Levenson-type phase shift method becomes unnecessary, and the contact diameter of the peripheral circuit can be reduced, so that the layout area can be reduced.

Further, since the contact hole 15b with the n-type diffusion layer in the peripheral circuit portion is opened directly on the substrate, the contact resistance of the peripheral circuit portion can be stabilized and the variation can be suppressed.

[Third Embodiment] Next, a third embodiment will be described with reference to the drawings.

In the second embodiment, the silicon layer and the WSi are used for the bit line material. Therefore, when the n-type doped silicon is used for the contact in the peripheral circuit portion,
Only the n-type diffusion layer could be contacted.

Therefore, in the peripheral circuit portion, the only way to make contact with the p-type diffusion layer is to make contact using the upper metal wiring. Further, since a deep contact hole from the upper wiring to the surface of the substrate must be formed, there is a problem that the layout area becomes large in order to provide a margin for alignment. Further, there is a problem that it is difficult to control the etching in forming such a deep contact hole.

According to the present embodiment, in the bit line structure formed under the capacitor, the material is metal wiring. Therefore, it is possible to make contact with the n-type diffusion layer and the p-type diffusion layer of the peripheral circuit portion via the shallow contact hole, and the layout area can be reduced.

FIG. 10 is a cross-sectional view of the semiconductor device according to the third embodiment, and corresponds to the cross-sectional view of FIG. 9I described in the second embodiment. In the figure, 9a indicates an n-type diffusion layer, and 9b indicates a p-type diffusion layer. The bit line 22 as the second conductive layer is connected to the two-layer metal wiring 18a,
19a. Other symbols are the same as those described in the second embodiment. The illustration of the well structure is partially omitted.

According to the present embodiment, when forming the contact hole 15b of the bit line, the contact hole 15b can be formed simultaneously in the n-channel transistor region and the p-channel transistor region of the peripheral circuit portion.

Therefore, as shown in FIG. 9I, there is no need to make direct contact with the substrate using the upper metal wiring, so that the layout area of the peripheral circuit portion can be reduced.

[Fourth Embodiment] A fourth embodiment according to the present invention will be specifically described with reference to FIGS.

The present embodiment will be described below focusing on a technique for contacting the first conductive layer and the second conductive layer in the peripheral circuit portion.

FIG. 11 is a cross-sectional view of a semiconductor device corresponding to FIG. 9I in the second embodiment, in which the first conductive layers 4, 5 and the second conductive layers 18, 1
9 shows a case where they are in contact with each other.

FIG. 12 is a sectional view of the semiconductor device according to the fourth embodiment, which is an improvement of the semiconductor device shown in FIG. The cell part is shown in FIG.
This corresponds to the cell section of I, and the peripheral circuit section is similar to the peripheral circuit section of FIG. 9I. In the drawings, the same reference numerals indicate the same components.

In this embodiment, the Si ₃ N used for the SAC is
After the formation of the ₄ film 12, the Si ₃ N ₄ film 12 in the peripheral circuit region is removed. That is, for example, in the steps of FIG. 2C and FIG. 9C, the Si ₃ N ₄ film 12 in a region including a portion where a contact between the first conductive layer and the second conductive layer is desired to be made.
Is selectively removed. In the cell portion, the n-type diffusion layer 9
A single layer of Si ₃ N ₄ film 12 exists between the first conductive layers 4 and 5 and the interlayer insulating film 13 in the peripheral circuit portion. 7 are present.
The SiON film 7 and the SiN film 12 can be selectively etched by the same etching.

Thus, the contact between the first conductive layer and the second conductive layer can be formed simultaneously when the contact hole between the bit line and the substrate is opened. In contrast to the method of FIG. 11 in which a fine contact hole to the first conductive layer must be opened separately from the contact hole with the substrate, in FIG. 12, the SiON film in the region where the contact hole is to be opened is removed. For this purpose, a separate fine pattern is not required, and the yield and reliability can be improved.

[Fifth Embodiment] A fifth embodiment of the present invention will be described with reference to FIG.

This embodiment is a combination of the third and fourth embodiments, and is a method for making contact between the first conductive layer and the second conductive layer. The case where a metal is applied to the conductive layer of the eye is shown.

FIG. 13 is a cross-sectional view of the semiconductor device according to the present embodiment, which is an improvement of FIG. 12 described in the fourth embodiment. In the drawings, the same reference numerals indicate the same components.

According to the present embodiment, when forming a contact of a bit line, a contact hole can be simultaneously formed in the n-channel transistor region and the p-channel transistor region of the peripheral circuit portion, and can be directly formed by the upper wiring. Since the necessity of making contact with the substrate is reduced, the layout area of the peripheral circuit portion can be reduced.

[0102] Also, after an Si ₃ N ₄ film 12 to be used in the SAC, since the removal of the Si ₃ N ₄ film 12 in the peripheral circuit region, when the contact hole for the bit line and the substrate, at the same time A contact between the first conductive layer and the second conductive layer can be formed, so that the number of steps can be reduced.

[Sixth Embodiment] A sixth embodiment of the present invention will be described with reference to FIG.

The present embodiment relates to a method for forming a contact hole in a peripheral circuit portion. When a contact hole is formed in an impurity diffusion layer or a wiring layer by etching an interlayer insulating film, if the interlayer insulating film is composed of a plurality of oxide films or a plurality of nitride films, the contact hole in forming the contact hole is reduced. Etching becomes complicated.

Therefore, the present embodiment is characterized in that the step of forming a contact hole in the peripheral circuit portion is performed stably.

FIG. 14 is a sectional view of a semiconductor device according to the present embodiment, which is an improvement of the semiconductor device described in the second embodiment. In the drawings, the same reference numerals indicate the same components.

Referring to FIG. 14, the manufacturing process of the semiconductor device according to the present embodiment is the same as that of the second embodiment shown in FIGS.
The manufacturing process is almost the same as that described with reference to 9I, and different points will be described below.

First, after patterning the gate electrode serving as the first layer wiring, in the peripheral circuit portion, the SiON film 7 on the gate electrode 8 is removed by, for example, boiling phosphoric acid.
Also, after patterning the bit line serving as the second layer wiring, the SiON film 21 on the bit line is removed in the peripheral circuit portion. Further, following the patterning of the counter electrode 30, in the peripheral circuit portion, the Si ₃ N ₄ film 25 of SAC is removed. The SiON films 7 and 21 are used as anti-reflection films when patterning wiring, and
If the wiring is patterned without using the ON films 7 and 21, there is no need to remove the wiring.

According to the present embodiment, there is no SiON film on the first layer wiring and bit line in the peripheral circuit portion, and a single layer SiN film is formed. At the same time as removing the nitride film used for the SAC necessary for forming the memory cell portion, the SiN film in the peripheral circuit portion can be removed, and the oxide film thereunder can be removed at the same time. In particular, since the contact holes are selectively removed in the peripheral circuit portion without increasing the number of steps, formation of contact holes in the peripheral circuit portion is facilitated.

[Seventh Embodiment] A seventh embodiment of the present invention will be described with reference to FIG.

In the sixth embodiment, the SiON film 7 on the first layer wiring (gate electrode) and the S
The iON film 21 is removed, and the S
By removing the i ₃ N ₄ film 25 using the counter electrode as a mask, the formation of the contact hole in the peripheral circuit portion is facilitated. In the present embodiment, a method for further facilitating the formation of the contact hole is provided. .

FIG. 15 is a sectional view of the semiconductor device according to the present embodiment, which is an improvement of the semiconductor device described in the sixth embodiment. In the drawings, the same reference numerals indicate the same components.

Referring to FIG. 15, the manufacturing process of the semiconductor device according to the present embodiment is substantially the same as the manufacturing process described with reference to FIGS. 9A to 9I in the second embodiment, similarly to the sixth embodiment. Hereinafter, different points will be described.

First, after patterning the gate electrode serving as the first-layer wiring, the SiON film 7 on the gate electrode 8 in the peripheral circuit portion is removed by, for example, boiling phosphoric acid.

[0114] Then, after an Si ₃ N ₄ film 12 used in the SAC, selectively remove the Si ₃ N ₄ film 12 in the peripheral circuit region. Next, the SiON film 21 on the bit line is removed even after the bit line serving as the second-layer wiring is patterned. Further, following the patterning of the counter electrode 30, the SAC Si ₃ N ₄ film 25, the interlayer insulating film SiO ₂ film 24, and the SAC Si ₃ N ₄ film 14 in the peripheral circuit portion are sequentially removed.

The SiON films 7 and 21 are used as an antireflection film when patterning the wiring. If the wiring is patterned without using the SiON films 7 and 21, the SiON films 7 and 21 need not be removed. Absent.

According to the present embodiment, all the SiON films 7, 21 and the Si ₃ N ₄ films 12, 25,
The removal of 14 further facilitates the formation of contact holes in the peripheral circuit section.

[Eighth Embodiment] An eighth embodiment of the present invention is shown in FIGS. 16A to 16I.

The present embodiment provides a method for contacting the first conductive layer and the second conductive layer in the peripheral circuit portion by using means different from the fourth embodiment.

16A to 16I are cross-sectional views of the chip showing the steps for fabricating the semiconductor device according to the present embodiment. In the drawings, the same reference numerals denote the same components.

Referring to FIG. 16A, p-type silicon substrate 1
After performing LOCOS isolation (selective oxidation) using a known technique above, forming a field SiO ₂ film 2 having a thickness of 250 nm, the SiO ₂ film 3 serving as a gate oxide film having a thickness of 5 to 10 nm is formed by thermal oxidation. To form Then, low pressure CVD
A 50 nm thick silicon layer 4 containing a high concentration of P (phosphorus), a 120 nm thick WSi layer 5, and a 20 nm thick
SiO ₂ film 6 and an 80 nm thick Si ₃ N ₄ film 7 ′ are sequentially formed.

Further, the patterned resist mass
(Not shown), the first conductive layer and the second conductive layer
For the region containing the part that you want to contact with the layer,
Si _ThreeN_FourThe film 7 'is selectively removed.

Referring to FIG. 16B, the Si ₃ N ₄ film 7 ′, the SiO ₂ film 6, the WSi layer 5 and the silicon layer 4 are selectively removed by using a patterned resist mask (not shown). Then, a gate electrode 8 (first layer wiring) is formed. Note that the gate electrode becomes a word line.

Referring to FIG. 16C, using the gate electrode 8 as a mask, P (phosphorus) ions are implanted into the silicon substrate 1 to form an n ⁻ -type impurity diffusion layer 9. The n ⁻ -type impurity diffusion layer 9 serves as a source and a drain of the transfer transistor in the cell portion, and serves as an LDD low concentration diffusion layer of the n-channel transistor in the peripheral circuit portion. Then, a reduced pressure CVD method by to form a Si ₃ N ₄ film having a thickness of 60nm on the entire surface by anisotropic etching to form sidewall 10 'made of Si ₃ N _4.

Referring to FIG. 16D, an n ⁺ -type diffusion layer is formed by implanting arsenic ions into the n-channel transistor region of the peripheral circuit portion. A p ⁺ diffusion layer is formed by implanting boron ions into the peripheral p-channel transistor region.

Next, a SiO ₂ film 11 having a thickness of 20 nm and a BPSG film 13 having a thickness of 300 to 400 nm are formed on the entire surface by low pressure CVD, and the BPSG film 13 is reflowed by a heat treatment at about 800 ° C. in a nitrogen atmosphere. . In addition,
In order to completely planarize, it is preferable to planarize the surface by polishing by a CMP method.

[0126] Then, on the entire surface by low pressure CVD method, an Si ₃ N ₄ film 14 having a thickness of 50 nm, a patterned resist mask (not shown), the Si ₃ N ₄ film in the region where the storage electrode is a contact 14 is selectively removed. Next, the BPSG film 13 is removed by self-alignment using the nitride films 7 'and 10' to form a contact hole 15a by SAC.

Further, a thickness of 300
A doped silicon layer of nm is embedded in the contact hole 15a, and the doped silicon layer on the Si ₃ N ₄ film 14 is removed by a CMP method to form a plug 16.

Referring to FIG. 16E, a 20 to 60 nm-thick Si
An O ₂ film 17 is formed. This SiO ₂ film 17 insulates the plug 16 from the bit line serving as the second layer wiring. Next, the SiO ₂ film 17, the Si ₃ N ₄ film 14, the BPSG film 13, and the SiO ₂ film 11 are selectively removed by a patterned resist mask (not shown), and the bit line 2 is removed.
The second contact hole 15b and the contact hole 15b of the peripheral circuit are simultaneously formed. Contact hole 15
As in the case of forming a, contact holes 15b are formed in a self-aligned manner using nitride films 7 'and 10'.

Referring to FIG. 16F, a 40 nm-thick doped silicon layer 18 containing a high concentration of P, a 120 nm-thick WSi layer 19, and a 20
A SiO ₂ film 20 of nm and a Si ₃ N ₄ film 21 ′ of 120 nm in thickness are sequentially formed. Next, using a patterned resist mask (not shown), each layer is selectively removed to form a bit line 22.

Further, a thickness of 6
And an Si ₃ N ₄ film of 0 nm, to form a side wall 23 made of Si ₃ N ₄ 'by anisotropic etching.

Referring to FIG. 16G, an SiO ₂ film 24 having a thickness of 10 to 30 nm is formed on the entire surface by low pressure CVD. Next, a thickness of 1000 to 15 is formed on the entire surface as a flattening film.
A BPSG film 26 having a thickness of 00 nm is formed and
The BPSG film 26 is reflowed by a heat treatment at 50 ° C.
In addition, in order to completely planarize, it is preferable to planarize the surface by polishing by a CMP method.

Next, the BPSG film 26 and the SiO ₂ film 2 are formed using a patterned resist mask (not shown).
4 are sequentially and selectively removed by self-alignment using the nitride films 21 and 23 'to form contact holes H for forming storage electrodes.
Form C.

Next, a 60 nm-thick doped silicon layer containing phosphorus at a high concentration is formed by a low pressure CVD method, and a resist 2 is formed in a contact hole for forming a storage electrode.
After embedding No.8, the surface is polished by CMP and BP
The silicon layer on the SG film 26 is removed, and a storage electrode 27 is formed.

Referring to FIG. 16H, the resist 28 in the storage electrode is removed. Next, the BPSG film 26 is removed by HF wet etching to expose the outer surface of the storage electrode. The figure shows a case where a part of the BPSG film 26 is left. Next, the surface of the storage electrode 27 is nitrided by the RTN method. Next, a film thickness of 5
To form a Ta ₂ O ₅ film 29 having a thickness of 800 to 85 nm.
Oxidation heat treatment or oxygen plasma annealing at about 0 ° C. is performed.

Further, 50 nm-thick TiN serving as a counter electrode is formed on the entire surface by a low-pressure CVD method, and etching is performed using a patterned resist mask (not shown) as a mask to form a counter electrode 30. .

Referring to FIG. 16I, a stacked capacitor is manufactured through the steps of forming interlayer insulating film 31, wiring layers 32 and 33, and the like.

[0137] In this embodiment, in the step of FIG. 16A, 'after forming, Si ₃ N ₄ film 7 of the peripheral circuit region' Si ₃ N ₄ film 7 used in the SAC by the selective removal of, FIG. 16E When the contact hole between the bit line and the substrate is opened in the step of, the contact between the first conductive layer and the second conductive layer can be formed at the same time, and the number of steps can be reduced. be able to.

Further, according to the present embodiment, a Si ₃ N ₄ film is formed so as to surround a gate electrode (first-layer wiring) and a bit line (second-layer wiring), and a self-align contact is performed. Since there is no unnecessary Si ₃ N ₄ film in the peripheral circuit portion, it is easy to form a contact hole in the peripheral circuit portion.

[Ninth Embodiment] In the fourth to eighth embodiments, the formation of contact holes in the peripheral circuit section is facilitated by selectively removing the Si ₃ N ₄ film in the peripheral circuit section. Explained what can be done.

The present embodiment provides a semiconductor device capable of reducing the number of steps in a memory cell portion and facilitating formation of a contact hole in a peripheral circuit portion, and a method of manufacturing the same.

Hereinafter, the ninth embodiment will be described in detail with reference to the drawings. This embodiment is shown in FIGS.
B, 18A-18L. In the drawings, the same reference numerals indicate the same components.

FIG. 17A is a plan view of the memory cell portion in the present embodiment. FIG. 17B is a cross-sectional view of the memory cell portion and the peripheral circuit portion in the present embodiment. The memory cell portion corresponds to a cross section along line XX ′ and YY ′ in FIG. 17A.

FIGS. 18A to 18L are sectional views showing the steps of manufacturing the semiconductor device according to the present embodiment. This embodiment is a modification of the second embodiment, and the same reference numerals as those in the second embodiment denote the same components in the drawings.

Referring to FIG. 18A, p-type silicon substrate 1
The LOCOS isolation (selective oxidation) is performed by using the above-described known technique to form the field SiO ₂ film 2 having a thickness of 250 nm. Next, a well diffusion layer, an element isolation diffusion layer, and a channel diffusion layer are formed by ion implantation (not shown). Next, an SiO ₂ film 3 serving as a gate oxide film having a thickness of 5 to 10 nm is formed by thermal oxidation.

Referring to FIG. 18B, a 50 nm-thick doped silicon layer 4 containing a high concentration of phosphorus, a 120 nm-thick WSi layer 5 and an 80 nm-thick SiO ₂ film 6 are sequentially formed on the entire surface by the CVD method. Form. Next, a film having an appropriate absorption for an exposure wavelength used for phytolithography, for example, a SiON film 7 having a thickness of about 30 nm is formed thereon by a plasma CVD method as an antireflection film.

Further, by using a patterned resist mask (not shown), the SiON film 7 and the SiO ₂ film 6 are selectively removed by, for example, F system, and the WSi layer 5 and the silicon layer 4 are selectively removed by, for example, Cl system. Thus, a gate electrode 8 is formed. Note that the gate electrode 8 becomes a word line. Less than,
For simplification, the illustration of the SiON film 7 is omitted.

Referring to FIG. 18C, using the gate electrode 8 as a mask, P ions are implanted into the substrate 1 to form an n ⁻ -type impurity diffusion layer (not shown). Note that the n ⁻ -type impurity diffusion layer serves as a source and a drain of the transfer transistor in the cell portion, and the L-type of the n-channel transistor in the peripheral circuit portion.
It becomes a low concentration diffusion layer for DD (not shown). Next, an SiO ₂ film having a thickness of 70 nm is formed on the entire surface by a low pressure CVD method, and the sidewalls 10 are formed by anisotropic etching.

Next, an n ⁺ diffusion layer is formed by implanting arsenic ions into the n-channel transistor region of the peripheral circuit portion. In addition, a p ⁺ diffusion layer is formed by implanting boron ions into the peripheral p-channel transistor region (not shown).

Next, a 50 to 100 nm-thick, preferably 60 to 80 nm-thick Si ₃
An N ₄ film 12 is formed. The Si ₃ N ₄ film 12 serves as a stopper film when forming a contact hole.

Next, as a flattening film, a thickness of 300
A BPSG film 13 having a thickness of about 400 nm is formed, and the BPSG film 13 is reflowed by heat treatment. Thereafter, the BPSG film 13 is polished by the CMP method so as to have a thickness of about 100 nm above the gate electrode 8, and the surface is flattened.

[0151] With reference to FIG. 18D, the patterned resist mask (not shown), stopping at the shaved part of the Si ₃ N ₄ film 12 by selectively etching the BPSG film 13, followed by Si ₃ The N ₄ film 12 is selectively removed and SA using the oxide films 10 and 6 as an etching stopper
A contact hole 15a is formed by C. Note that the resist mask in this case is preferably formed by a phase shift method. Also, to lower the contact resistance,
After forming the contact hole 15a, the substrate 1 may be ion-implanted with phosphorus.

Next, a 200-300 nm-thick doped silicon layer containing high-concentration phosphorus is buried in the contact hole 15a by low-pressure CVD, and the doped silicon layer on the BPSG film 13 is removed by CMP. ,
The plug 16 is formed.

Referring to FIG. 18E, a 20 to 50 nm thick Si
An O ₂ film 17 is formed. This SiO ₂ film 17 insulates the plug 16 from the bit line 22 serving as the second-layer wiring. Next, a patterned resist mask (not shown)
As a result, the SiO ₂ film 17 and the BPSG film 13 are selectively etched to stop where the Si ₃ N ₄ film 12 is partially removed, and then the Si ₃ N ₄ film 12 is selectively removed to remove the oxide film. A contact hole 15b is formed by SAC as an etching stopper.

Referring to FIG. 18F, a 40 nm-thick doped silicon layer 18 containing a high concentration of phosphorus, a 120 nm-thick WSi layer 19, and a 160
A SiO ₂ film 20 of nm is formed in order. Next, a thickness of 30 n on which an anti-reflection film is to be formed by a plasma CVD method.
About m m of SiON films 21 are sequentially formed.

Further, using a patterned resist mask (not shown), each layer is selectively removed to form a bit line 22. Also, if necessary, RT
The contact annealing may be performed by the method A. Since then
For simplification, the illustration of the SiON film 21 is omitted.

Referring to FIG. 18G, a SiO ₂ film having a thickness of about 60 to 70 nm is formed by low pressure CVD, and sidewalls 23 made of SiO ₂ are formed by anisotropic etching.
To form

[0157] Here, by setting the etching amount in the thickness portion of the SiO ₂ film 17 and the SiO ₂ film for the sidewall, leaving the SiO ₂ film 17 under the bit line 22 and side wall 23 only. As a result, the surface of the plug 16 filled in the contact hole 15a is exposed.

Referring to FIG. 18H, a thickness of 50 to 1 serving as an SAC etching stopper film is obtained by a low pressure CVD method.
A 00 nm Si ₃ N ₄ film 25 is formed. Next, a BPS having a thickness of 1000 to 1200 nm is formed on the entire surface as a planarizing film.
After the G film 26 is formed and the BPSG film 26 is reflowed by a heat treatment, the surface is polished to a thickness of about 800 nm by a CMP method to be planarized.

[0159] Referring to FIG. 18I, (not shown) by patterned resist mask, stopping at shaved part of the Si ₃ N ₄ film 25 by selectively etching the BPSG film 26, followed by Si ₃ The N ₄ film 25 is selectively etched to form a contact hole HC for forming a storage electrode by SAC using an oxide film and a silicon film as etching stoppers.

Referring to FIG. 18J, a 60-nm-thick doped silicon layer containing high-concentration phosphorus is formed by low-pressure CVD, and the silicon layer on BPSG film 26 is further removed by CMP to accumulate. The portion in contact with the inner wall surface of the contact hole for electrode formation is left as the storage electrode 27.

In this case, if necessary, a resist is buried in the concave portion of the silicon layer before performing the CMP, and the resist is removed after the CMP, so that abrasive particles at the time of CMP enter the concave portion, making removal difficult. Can also be prevented.

Referring to FIG. 18K, BPSG film 26 is removed by HF wet etching using Si ₃ N ₄ film 25 as an etching stopper film, and the outer surface of the storage electrode is also exposed. Next, the film thickness is 5 to 15 n by the CVD method.
The Ta ₂ O ₅ film 29 having a thickness of m is formed, and the Ta ₂ O ₅ film 29 is densified by performing oxidation heat treatment or oxygen plasma annealing.

Further, a 100 nm-thick TiN film serving as a counter electrode is formed by a low-pressure CVD method, and ClN is formed using a patterned resist mask (not shown) as a mask.
The opposite electrode 30 is formed by performing dry etching with a system gas.

At this time, it is also preferable to etch the Ta ₂ O ₅ film subsequent to the etching of the TiN film.
It is also preferable that the surface of the storage electrode 27 is nitrided by RTN before forming the Ta ₂ O ₅ film.

Referring to FIG. 18L, HDP (High Densit
y Plasma) The thickness of the interlayer insulating film is 10 by CVD.
A SiO ₂ film 31 having a thickness of 00 nm is formed, and the surface is polished and flattened by a CMP method. Next, a contact hole is formed in the peripheral circuit portion.

Next, a 60 nm-thick Ti film was formed as a contact metal by a collimator sputtering method.
A TiN film having a thickness of 30 nm is formed by the CVD method to form the barrier medal layer 32. On top of this, a thickness of 150 nm
Is formed.

Thereafter, a semiconductor device having a stacked capacitor is manufactured by further performing steps such as an interlayer insulating film and a wiring layer.

In this embodiment, as compared with the first to eighth embodiments, the Si ₃ N ₄ film 14 serving as the stopper film when forming the contact hole of the storage electrode is not formed, so that it is formed in the peripheral circuit portion. Contact holes can be easily formed.

Further, the side wall 2 is connected to the bit line 22.
In the etching step for forming 3, the SiO ₂ film 17 that insulates the bit line 22 from the plug 16 is continuously removed by etching, whereby the number of etching steps can be reduced.

In the ninth embodiment, it has been described that mainly the number of manufacturing steps can be reduced. However, in the ninth embodiment, when the bit line contact hole 15b and the bit line 22 are misaligned, the bit line contact portion is exposed in the storage electrode contact, and the storage electrode comes into contact with the bit line. The problem arises.

FIG. 19 shows the case where the above-mentioned displacement has occurred, and FIG. 20 shows the case where the bit line 22 and the storage electrode contact each other when the storage electrode 27 is formed in a subsequent step. 19 and 20 correspond to the state of FIG. 18F of the ninth embodiment and the state in which the BPSG film is removed after FIG. 18J.

In the ninth embodiment, when the hole diameter of the bit line contact is considerably larger than the width of the bit line 22, or when a displacement occurs even though the hole diameter is almost the same,
The pattern of the bit line contact hole 15b protrudes from the pattern of the bit line 22. In particular, it has been found that the following problem occurs when the protrusion protrudes more than the thickness of the sidewall 23 formed on the bit line 22.

FIG. 19 shows a case where the shift amount is about 1.5 times the thickness of the side wall 23.
This shows a state immediately after formation. Assuming that the etching amount of the bit line 22 is equivalent to the thickness of the formed WSi 19 / silicon layer 18, the upper surface of the conductive film is visible at the portion where the contact hole 15b of the bit line protrudes as shown in the figure. .

FIG. 20 shows a state in which the storage electrode 27 has been formed through the steps described in the ninth embodiment. In this figure,
Similarly, the storage electrode contact hole pattern for forming the storage electrode also shows a shifted state. The upper surface of the conductor of the bit line 22 is located at a portion where the contact hole of the storage electrode protrudes. For this reason, the bit line 22 and the storage electrode 27 are short-circuited.

Although the yield is reduced by such a design and misalignment, it is disadvantageous to design with a misalignment margin in order to reduce the cell area and improve the degree of integration.

[Tenth Embodiment] The present embodiment provides a semiconductor device in which the bit line 22 and the storage electrode 27 do not come into contact with each other even if the above-described displacement occurs, and a method of manufacturing the same.

Hereinafter, the tenth embodiment will be described in detail with reference to the drawings. This embodiment is shown in FIGS.
Shown in 1D. FIG. 21A is a continuation of FIG. 18E described in the ninth embodiment. In the drawings, the same reference numerals indicate the same components.

Referring to FIG. 21A, the process is the same as that of the ninth embodiment up to the point where contact hole 15b for the bit line is opened.

Next, a 40 nm-thick doped silicon layer 18 containing a high concentration of phosphorus and a 120
nm WSi layer 19, 160 nm thick SiO ₂ film 20
Are sequentially formed. Thereafter, a SiON film 21 having a thickness of about 30 nm is formed as an anti-reflection film by a plasma CVD method.

Further, a mask (not shown) is formed by a lithography method using a normal or phase-shifted reticle, and the SiON film 21 and the SiO ₂ film 20 are formed using the F system.
The bit line 22 is formed by dry-etching the WSi layer 19 and the silicon layer 18 with Cl. If necessary, contact annealing may be performed at this stage by the RTA method. Hereinafter, the illustration of the SiON film 21 is omitted for simplification.

Referring to FIG. 21B, an SiO ₂ film having a thickness of 70 nm is formed by a CVD method, and side walls 23 are formed by anisotropic etching. Here, the etching amount SiO ₂ film 17 and the sidewall SiO ₂
The SiO ₂ film 17 is left only under the bit lines 22 and the sidewalls 23 by the thickness of the film. As a result, the surface of plug 16 filled in contact hole 15a is exposed.

The feature of this embodiment is that the bit line 22 is formed by over-etching.
This means that the bit line conductor film inside the bit line contact hole 15b is recessed.

The amount recessed by this etching is determined as follows. The amount by which the contact hole 15b of the bit line protrudes from the pattern of the bit line 22 due to displacement or the like is defined as d. The thickness of the SiO ₂ film for forming the sidewalls 23 in the next step is represented by t. For simplicity of explanation, it is assumed that this SiO ₂ film has a coverage of 100%, that is, is completely conformal.

In the case of d ≦ t, the amount of depression may be an amount necessary for ensuring insulation. For example, the same value as t can be selected. As a result, the distance between the conductor forming the bit line and the conductor forming the storage electrode becomes t or more in any part. In addition, w is necessary for ensuring insulation, and d <tw.
Then, there is no need to dent.

Referring to FIG. 21B, when 2t>d> t, an insulator integrated with sidewall 23 is formed due to rounding of sidewall 23 formed from the right side wall of bit line contact hole 15b. A dent occurs in the part. This amount, t-- a ^{(t 2 (d-t)} 2) 1/2. The conductor constituting the bit line may be recessed by an amount obtained by adding an amount necessary for securing insulation.

When d ≧ 2t, a short circuit cannot be avoided by this embodiment. However, this means that d is 0.14 μm or more when t = 0.07 μm as in the present embodiment. If the displacement is 0.1 μm at the maximum, the contact hole 15
b is larger than the bit line width by (0.14-0.1) × 2 =
This corresponds to a case where the size is larger by 0.08 μm. 0.25μ
It is considered that there is no merit in designing a device of a generation of about m or less even with such a large difference.

When the coverage is not 100%, d, t, and the amount of dent are set in consideration of the decrease in the film thickness in the lateral direction and the generation of voids. Also, the contact hole 15b of the bit line is formed by over-etching the bit line.
If the inside is made to have a forward taper, it can be embedded well even when coverage is poor.
It is also effective to form a forward taper above the bit line contact hole 15b.

Further, the bit line conductor film is over-etched to be recessed in the bit line contact hole 15b, and the amount thereof will be described in detail using specific numerical values.

A description will be given of an example of a 0.2 μm device. The bit line and the interval between the bit lines are 0.2 μm, but the diameter of the bit line contact hole 15b is preferably about 0.24 μm for photolithography. A typical value of the maximum displacement is 0.1 μm. The numerical value of the displacement includes a variation in the size of the bit line contact hole 15b and the size of the bit line 22. In other words, it is assumed that the bit line contact hole 15b is large and the bit line 22 is made thin (10% is half on each side since each side is 10%).

Then, d = (0.24-0.2) / 2 +
0.1 = 0.12 μm. The limit of the thickness of the sidewall insulating film is 70 nm. This is because the interval between the bit lines 22 was 0.2 μm, so that when 0.07 μm sidewalls were formed on both sides, the contact width already remained only 0.06 μm.

In actual production, not only displacement but also
The film thickness and the amount of etching also vary. It is typical to assume a width of 7% for film formation and 7% for etching. Therefore, to consider the worst case, it is appropriate to set t = 0.065 μm.

Then, Δ = t− (t ² − (dt) ² )
^1/2 = 0.03 μm. Here, considering the variation in the film thickness of the sidewall insulating film and the etching amount, it is considered that 0.
It is necessary to assume that it is cut away by 01 μm. Since it is considered preferable to leave at least about 0.02 μm in order to ensure the withstand voltage, it is preferable to make the recess more than 0.06 μm in total.

On the other hand, in etching such as bit line formation, over-etching has conventionally been performed in order to absorb variations in film thickness and etching amount. The amount is at least about 20%. Note that because the structure is planarized, no further overetching is required in the prior art. In the film thickness of the present embodiment, the silicon layer 4
0 nm and the WSi film was 120 nm.
% Is 0.032 μm. Therefore, in the conventional bit line formation, the dent at the bit line contact hole 15b is typically about 0.032 μm.

On the other hand, in this embodiment, 0.06 μm
Since a recess of not less than m is formed, a short circuit between the bit line conductor and the storage electrode conductor at the bit line contact portion can be prevented.

In the prior art, by making the bit line thicker in the bit line contact hole portion, a pattern is designed so that the bit line is not exposed from the bit line contact hole even if a positional shift occurs. Was typical.

In this case, no matter how much over-etching was performed, no dent could occur at the contact hole 15b, and at the same time, no short-circuit, which was the subject of this embodiment, occurred. In other words, there is no longer enough room for miniaturization and the above-described device structure has caused the problem of the present embodiment.

As another numerical example, if the diameter of the bit line contact hole 15b is designed to be 0.22 μm and the displacement is 0.09 μm, the same calculation is performed.
0.1 μm, t = 0.065 μm, and Δ = 0.01
μm.

Again, shaving in the formation of the sidewalls 0.0
When 1 μm and 0.02 μm for ensuring withstand voltage are added, the minimum value of the dent becomes 0.04 μm.

As still another numerical example, based on the present embodiment, a case where the sidewall width is 60 nm at the contact hole 15b because the coverage is not 100% is calculated in the same manner, and d = 0.1 μm , T = 0.05
6 μm, and Δ = 0.024 μm. Again shaving due to sidewall formation 0.01 μm, withstand voltage 0.02
When μm is added, the minimum value of the depression becomes 0.054 μm.

Referring to FIG. 21C, a storage electrode 27 is formed in the same manner as in FIGS. 18H to 18J described in the ninth embodiment.

Referring to FIG. 21D, further, similarly to FIGS. 18K and 18L described in the ninth embodiment, a capacitor insulating film 29 (not shown), a counter electrode 30, an interlayer insulating film 31, and a wiring layer 32 , 33 are formed.

Thereafter, a semiconductor device having a stacked capacitor is manufactured by further performing steps such as an interlayer insulating film and a wiring layer.

In this embodiment, the bit line contact portion is exposed in the storage electrode contact, and the bit line 22 and the storage electrode 27 come into contact with each other. It is characterized in that a predetermined overetch is performed.

That is, the conductor constituting the bit line is recessed in the contact hole 15b of the bit line protruding from the bit line pattern, and when forming the sidewall 23 on the bit line 22, this recess is formed. By filling with a sidewall insulating film, the contact can be prevented without increasing the number of steps.

[Eleventh Embodiment] The eleventh embodiment of the present invention will be described.
An embodiment will be described with reference to the drawings.

FIG. 22 is a sectional view of a semiconductor device according to the eleventh embodiment. In the figure, the same reference numerals as those in the ninth embodiment denote the same parts.

The difference from the ninth embodiment will be described below with reference to FIG. In the ninth embodiment, as shown in FIG. 18G, SiO 2 insulating the bit line 22 from the plug 16 is used.
_{The second} film 17 was removed at the same time as the formation of the sidewall 23 so that only the bit line 22 and the sidewall of the sidewall remained immediately below the sidewall 23. In the present embodiment, the side wall 2
3 during the etching for forming the SiO ₂ film 3.
In the step of opening a contact hole for forming a storage electrode, a stopper film Si ₃ N
Following the removal of the _fourth film 25, the SiO ₂ film 17 is removed so that the surface of the plug 16 is exposed.

The advantage of this embodiment is that when the Si ₃ N ₄ film 25 serving as the etching stopper film is removed, all the bases are made of the SiO ₂ films 17 and 23, so that the selectivity with respect to silicon (plug 16) can be secured. It can be manufactured even by a method of removing the Si ₃ N ₄ film 25 that does not exist.

The short-circuit problem described in detail in the tenth embodiment also occurs in the manufacturing method according to the present embodiment. FIG. 23 shows a contact hole 15 of the bit line.
This shows a case where b protrudes greatly from the bit line 22. The conductor forming the bit line 22 is exposed when opening the contact hole forming the storage electrode, and the bit line 22 and the storage electrode 27 are short-circuited.

However, this problem can be dealt with by recessing the bit lines as in the tenth embodiment (see FIG. 22).

[Twelfth Embodiment] In the tenth embodiment,
When the bit line contact hole 15b and the bit line 22 are misaligned, the bit line 22 and the storage electrode 2
The method of preventing a short circuit with No. 7 has been described. In the present embodiment, another embodiment will be specifically described with reference to the drawings as a countermeasure against the same problem.

This embodiment is shown in FIGS. 24, 25A and 25B. FIG. 24 is a plan view of the memory cell portion in the present embodiment, and FIGS. 25A and 25B are cross-sectional views of the semiconductor device in the present embodiment. 25A and 25
B is a continuation of FIG. 19 described in the tenth embodiment. In the figure, the same reference numerals as in the tenth embodiment denote the same components.

Referring to FIG. 25A, up to the point where bit line 22 is patterned, it is the same as the tenth embodiment.

Next, a 70 nm-thick Si
An O ₂ film is formed, and a sidewall 23 is formed by anisotropic etching. At this time, following the anisotropic etching of the sidewall 23, the SiO ₂ film 17 may be etched so as to expose the surface of the plug 16.

Next, an SiO ₂ film 24 having a thickness of about 30 nm is formed by the CVD method. Thereafter, the SiO ₂ films 17 and 2 on the plug 16 of the storage electrode contact are formed by a lithography method using a reticle of a normal or phase shift.
4 is selectively etched to expose the surface of the plug 16 (see FIG. 24).

Referring to FIG. 25B, a storage electrode 27 is formed in the same manner as in FIG. 21C described in the tenth embodiment. Here, in the step of opening a contact hole for forming a storage electrode, Si ₃ N serving as an etching stopper is used.
_{When the 4} film 25 is etched, the SiO ₂ film 24 is used as an etching stopper, so that even if the bit line contact hole 15b and the bit line 22 are displaced, the bit line contact portion is not exposed.

As described above, S serving as an etching stopper
Under the i ₃ N ₄ film 25, to form a SiO ₂ film 24, by leaving open only the top of the plug 16 of the storage electrode contact the SiO ₂ film 24, the bit line contact hole 15b and the bit line 22 Can cause a short circuit between the bit line and the storage electrode.

Further, by using the over-etching described in the tenth embodiment together, it is possible to further improve the breakdown voltage.

[Thirteenth Embodiment] In the first to twelfth embodiments, the description has been given of the cylindrical capacitor in which the storage electrode is left on the inner wall of the contact hole forming the storage electrode 27 to obtain a crown shape. The present invention is not limited to the cylinder type capacitor, but can be applied to a simple stacked capacitor type or FIN type capacitor.

Hereinafter, an embodiment using a simple stacked capacitor will be described with reference to the drawings.

FIG. 26 is a sectional view of a semiconductor device having a simple stacked capacitor. In particular, the semiconductor device described in the tenth embodiment is modified to a simple stacked capacitor type. In the figure, the same reference numerals as those described in the first to twelfth embodiments denote the same components.

Referring to FIG. 26, after the step shown in FIG. 19, sidewalls 23 are formed, and at that time, SiO ₂ film 17 insulating bit line 22 and plug 16 is removed. The steps up to here are the same as in the tenth embodiment.

Next, a doped silicon layer having a thickness of about 1 μm containing phosphorus at a high concentration is formed by a CVD method. At this time, it is also preferable that the surface is polished and planarized by a CMP method as necessary.

Further, the storage electrode 27 is formed by dry etching with a Br-based gas using a patterned resist mask (not shown). Here, if necessary, irregularities can be formed on the surface of the storage electrode by using a known method to increase the capacitance of the capacitor.

The contact hole 1 of the bit line 22
If the position of the bit line 22 is displaced from the position of the bit line 22, a short circuit between the bit line 22 and the storage electrode 27 may be a problem as before. This can be prevented.

Thereafter, the wafer process of the DRAM is completed as in the tenth embodiment.

According to the present embodiment, the number of steps can be greatly reduced. Note that the present invention can be implemented by combining some of the first to thirteenth embodiments.

For example, the eighth and tenth embodiments can be combined and will be described below.

In this embodiment, when the gate electrode 8 (word line) and the bit line 22 are formed, the SiO ₂ films 6 and 20 formed simultaneously on each of them are replaced with SiN films, and the respective side surfaces are formed. Walls 10, 23
Is changed from a SiO ₂ film to a SiN film. SAC etching stopper film 1 for forming bit line contact hole 15b and contact hole for forming storage electrode
2 and 25 are thin SiN films of about 20 nm so as to leave gaps. In the etching for forming the SAC, the BPSG films 13 and 26 embedded in the gap are removed, and then the thin SiN film is removed by anisotropic etching.

In such a case, the same technology as in the tenth embodiment can be applied. That is, by performing over-etching at the time of etching for forming the bit line, the WS in the bit line contact hole is removed.
The i / silicon layer is recessed. Then, when forming the SiN film side wall, the recess can be filled.

The relationship between the amount of the bit line contact hole 15b protruding from the bit line 22 due to the displacement, the thickness of the sidewall SiN film, and the necessary amount of dent is as follows.
It is substantially the same as the zeroth embodiment.

In the anisotropic etching for forming the sidewall of the SiN film on the side surface, the contact hole for forming the storage electrode can be formed without removing the SiO ₂ film 17 for insulating the bit line 22 from the plug 16 continuously. After SAC etching for forming a stopper film, a stopper film Si ₃ N
Subsequent to the removal of the _fourth film 25, the SiO ₂ film 17 can be removed.

Further, in forming the word lines 8 or the bit lines 22, there is a method in which an organic material film is applied as a reflection preventing film instead of the SiON films 7 and 21 below or above the resist. In this case, the anti-reflection film does not remain on the device.

Further, the material of the word line 8 or the bit line 22 is not limited to the WSi layers 5 and 19 and the silicon films 4 and 18, but a metal film such as a W / TiN film can be used.
In the case of a bit line, it is preferable to use a W / TiN / Ti film to which Ti is added as a contact metal.

[Fourteenth Embodiment] The fourteenth embodiment is different from the first to the first embodiment.
As described in the third embodiment, the SAC process is extremely important for manufacturing a highly integrated semiconductor device.

The key technology in the SAC process is the selectivity between the insulating film to be etched and the stopper film for stopping the etching. At present, when an oxide film is used as an interlayer insulating film, a nitride film is effective as a stopper film, but its selectivity in dry etching is not sufficient.

FIG. 27A is a sectional view of the semiconductor device showing the SAC process. In the drawings, the same reference numerals as those used in the first to thirteenth embodiments denote the same components.

FIG. 27A shows a state in which the SiO ₂ films 6 and 10 covering the gate electrode 8 are shaved at the shoulder of the gate electrode 8. That is, BP which is an interlayer insulating film
When the SG 13 is formed thick, the Si ₃ N ₄ film 12
Need to be formed thick so as to function as a stopper film. However, when the Si ₃ N ₄ film 12 is etched, if the Si ₃ N ₄ film 12 is thick, the SiO ₂ film 6 thereunder,
10 is scraped, and there is a problem that the breakdown voltage between the gate electrode and the contact is reduced.

Therefore, it is difficult to use the SAC process with the current selection ratio. Therefore, in the present embodiment, a stable SAC process is provided by forming the stopper Si ₃ N ₄ film into a double structure.

Hereinafter, the fourteenth embodiment will be described in detail with reference to the drawings. This embodiment is similar to that shown in FIGS.
7C. In the drawings, the same reference numerals indicate the same components.

FIG. 27B is a sectional view of the semiconductor device of this embodiment. Referring to FIG. 27B, after gate electrode 8 is formed, Si ₃ N ₄ film 12a, oxide film 13a, Si ₃ N ₄ film 12b, and oxide film 13b are each formed to a thickness of 10 n by a CVD method.
m, 50 nm, 70 nm, and 300 nm are formed.

Next, a method of forming a contact hole between gate electrodes 8 will be described. First, the oxide film 13b
Is etched using, for example, a high density plasma using a mixed gas of C ₄ F ₈ and Ar. Next, the Si ₃ N ₄ film 12b can be selected from the oxide film 13a under conditions that allow a selective ratio, such as wet etching with phosphoric acid, SF ₆ , O ₂ or SF ₆ ,
It is removed by dry etching using a mixed gas of Br. Similarly, oxide film 13a, Si ₃ N ₄ film 12a
Is etched.

[0243] In the case of performing the above-described dry etching in the etching of the Si ₃ N ₄ film 12a, depending on the application it is necessary to deposit an oxide film 11 under the Si ₃ N ₄ film 12a. The etching of the oxide film 11 is C
It is removed by RIE etching using F ₄ , CHF ₃ and Ar gas. Further, the nitride film may be etched by RIE using CF ₄ , CHF ₃ or Ar gas.

Further, in the embodiment shown in FIG. 27B, the upper layer S
Since the i ₃ N ₄ film 12b is used as a stopper film when the thick oxide film 13b is etched, the lower Si ₃ N ₄ film 12a is significantly different from the upper Si ₃ N ₄ film 12b. Can be made thinner.

Next, a description will be given of a SAC process capable of forming the upper Si ₃ N ₄ film 12b as thin as possible.

Referring to FIG. 27C, after formation of gate electrode 8, a Si ₃ N ₄ film 12a and an oxide film 13a (not shown) are formed by CVD at 20 nm and 50 nm, respectively, and SOG 13c is coated at 100 nm and flattened. Become At this time, SOG may be applied directly without forming an insulating film. In addition, an insulating film is formed to a thickness of 600 nm, and 50
It may be polished and flattened to 0 nm.

Next, the Si ₃ N ₄ film 12b and the oxide film 13b
Are formed to a thickness of 50 nm and 300 nm, respectively, by the CVD method.

Note that the same technique as that described with reference to FIG. 27B may be used for an etching method for forming a contact hole.

In the embodiment shown in FIG. 27C, the underlying Si ₃ N
After the formation of the _four films 12a, the oxide film 13c thereon is flattened. The thick oxide film 13b becomes flat, the load on the upper Si ₃ N ₄ film 12b during etching can be reduced, and the upper Si ₃ N ₄ film 12b can be made thinner.

In this embodiment, the case where the Si ₃ N ₄ film is used as the stopper film has been described. However, as the stopper film, polysilicon or a metal oxide such as alumina can be used. At this time, the etching of the alumina serving as the stopper is performed by RIE using Cl ₂ or BCl ₃ gas or Ar sputter etching. The polysilicon is etched using Cl ₂ , BCl ₃ gas, or HBr gas. Further, when etching alumina or polysilicon using chlorine-based or bromine-based gas, it is preferable to form an oxide film under the film.

According to this embodiment, the thickness of the stopper film can be made sufficiently thin by adopting the double stopper structure. As a result, the amount of over-etching for removing the stopper can be reduced, and the withstand voltage can be secured.

[Fifteenth Embodiment] FIG. 28 is a sectional view of a semiconductor substrate according to a fifteenth embodiment of the present invention. In the surface layer of the p-type silicon substrate 1, in the memory cell region,
An n-type well N1, and further a p-type well P1 is formed therein, and an n-type well N2 is formed in the peripheral circuit portion. In the memory cell region, the p-type well P1
An n-channel transfer transistor is formed therein;
In the peripheral circuit region, a p-channel transistor is formed in n-type well N2. Note that a double well can be formed also in the peripheral circuit region, and an n-channel transistor can be formed in the p-type well in the n-type well.

On the surface of the substrate, a field oxide film 2 is formed, and an active region surrounded by the field oxide film 2 is defined. In the memory cell region, a polycrystalline silicon layer 4 and a tungsten silicide layer 5 are formed on a gate insulating film 3 to form a gate electrode 8. On the gate electrode 8, a silicon oxide film 6 and an SiON film 7 functioning as an anti-reflection film are formed. The SiON film 7, the silicon oxide film 6, and the gate electrode 8 are patterned by photolithography, and a sidewall insulating film 10 of SiN is formed on a side wall thereof. Source / drain regions 9 into which n-type impurities are implanted are formed on both sides of the gate electrode.

An SiN film 12 is formed on the entire surface of the substrate on which such a gate electrode (word line) is formed. S
A BPSG film 13 is formed on the iN film 12 to form an interlayer insulating film. A contact hole for a storage electrode contact is formed through the BPSG film 13 and the SiN film 12, and is buried with a polycrystalline silicon region 16. The polycrystalline silicon region 16 is etched back or polished to form the same surface as the BPSG film 13, and an HTO (high temperature oxidation) silicon oxide film 17 is formed on the surface by CVD.

In the bit line contact region, HT
A contact hole is formed through the O film 17, the BPSG film 13, and the SiN film 12, and a polycrystalline silicon film 18 and a tungsten silicide film 19 are laminated on the surface of the HTO film 17 so as to fill the inner surface of the contact hole. Wiring is formed. This wiring forms a bit line. The bit line is insulated from the polycrystalline silicon region 16 buried by the HTO film 17. A stack of a silicon oxide film 21 and a SiN film 22 is formed on the bit line surface, and is patterned simultaneously with the bit lines. On the side wall of the bit line structure, a sidewall spacer of the SiN film 23a is formed.

Using the SiN film 22 and the SiN sidewall spacers 23a as etching stoppers, contact holes for storage electrodes are formed, and the surface of the polycrystalline silicon region 16 is exposed.

On such a structure, a polycrystalline silicon layer 27 serving as a storage electrode and Ta ₂ O ₅ formed on the surface thereof are formed.
The capacitor dielectric layer 29 and the TiN layer 30 formed on the surface thereof form a storage capacitor.

A BPSG film 31 serving as an interlayer insulating film is formed so as to bury the storage capacitor, and its surface is flattened by etch back, polishing, or the like.

In the peripheral circuit area, the BPSG film 31
, A bit line and a wiring layer formed by the same structure as the bit line, a word line and a wiring layer formed by the same process as the word line, and a contact hole reaching the conductive region on the substrate surface are formed. A wiring is formed by stacking the barrier layer 32 and the W layer 33 by Ti stacking.

In this structure, Si is directly formed on the side wall of the gate electrode of the transfer transistor and on the side wall of the bit line.
An N film is formed and functions as an etching stopper.
No SiN film is formed on the surface of the BPSG film 13,
A direct CVD oxide film 17 is formed. Even in such a configuration, a contact hole can be opened at a desired position by using the SiN film covering the top and side surfaces of the bit line as an etching stopper.

The present invention has been described in connection with the preferred embodiments.
The present invention is not limited to these. For example,
It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0262]

As described above, the production yield can be maintained while reducing the number of steps, and this greatly contributes to higher performance and higher density of the semiconductor device.

[Brief description of the drawings]

FIG. 1A is a plan view of a semiconductor device according to a first embodiment of the present invention.

FIG. 1B is a sectional view of the semiconductor device according to the first embodiment of the present invention;

FIG. 2A is a sectional view illustrating a manufacturing step of the semiconductor device according to the first embodiment of the present invention;

FIG. 2B is a sectional view showing a manufacturing step of the semiconductor device according to the first embodiment of the present invention;

FIG. 2C is a sectional view illustrating the manufacturing step of the semiconductor device according to the first embodiment of the present invention;

FIG. 2D is a sectional view illustrating the manufacturing step of the semiconductor device according to the first embodiment of the present invention;

FIG. 2E is a sectional view showing a step of manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 2F is a sectional view illustrating the manufacturing step of the semiconductor device according to the first embodiment of the present invention;

FIG. 2G is a sectional view illustrating the manufacturing step of the semiconductor device according to the first embodiment of the present invention;

FIG. 2H is a sectional view illustrating the manufacturing step of the semiconductor device according to the first embodiment of the present invention;

FIG. 3 is a plan view corresponding to the cross-sectional view of FIG. 2D.

FIG. 4A is a plan view of a memory cell of a semiconductor device according to a second embodiment of the present invention.

FIG. 4B is a plan view of a peripheral circuit of the semiconductor device according to the second embodiment of the present invention. Hereinafter, the figure with the letter A shows a memory cell, and the figure with the letter B shows a peripheral circuit.

FIG. 5A is a plan view of a memory cell of a semiconductor device according to a second embodiment of the present invention.

FIG. 5B is a plan view of a peripheral circuit of the semiconductor device according to the second embodiment of the present invention.

FIG. 6A is a plan view of a memory cell of a semiconductor device according to a second embodiment of the present invention.

FIG. 6B is a plan view of a peripheral circuit of the semiconductor device according to the second embodiment of the present invention.

FIG. 7A is a plan view of a memory cell of a semiconductor device according to a second embodiment of the present invention.

FIG. 7B is a plan view of a peripheral circuit of the semiconductor device according to the second embodiment of the present invention.

FIG. 8A is a plan view of a memory cell of a semiconductor device according to a second embodiment of the present invention.

FIG. 8B is a plan view of a peripheral circuit of the semiconductor device according to the second embodiment of the present invention.

FIG. 9A is a cross-sectional view showing a manufacturing step of the semiconductor device according to the second embodiment of the present invention;

FIG. 9B is a sectional view illustrating the manufacturing step of the semiconductor device according to the second embodiment of the present invention;

FIG. 9C is a sectional view illustrating the manufacturing step of the semiconductor device according to the second embodiment of the present invention;

FIG. 9D is a sectional view illustrating the step of manufacturing the semiconductor device according to the second embodiment of the present invention;

FIG. 9E is a sectional view showing a step of manufacturing the semiconductor device according to the second embodiment of the present invention;

FIG. 9F is a sectional view illustrating the manufacturing step of the semiconductor device according to the second embodiment of the present invention;

FIG. 9G is a sectional view illustrating the manufacturing step of the semiconductor device according to the second embodiment of the present invention;

FIG. 9H is a sectional view illustrating the manufacturing step of the semiconductor device according to the second embodiment of the present invention;

FIG. 9I is a sectional view illustrating the manufacturing step of the semiconductor device according to the second embodiment of the present invention;

FIG. 10 is a sectional view of a semiconductor device according to a third embodiment of the present invention.

FIG. 11 is a cross-sectional view of the semiconductor device corresponding to FIG. 9I;

FIG. 12 is a sectional view of a semiconductor device according to a fourth embodiment;

FIG. 13 is a sectional view of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 14 is a sectional view of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 15 is a sectional view of a semiconductor device according to a seventh embodiment of the present invention.

FIG. 16A is a sectional view showing a step of manufacturing the semiconductor device according to the eighth embodiment of the present invention;

FIG. 16B is a sectional view illustrating the manufacturing step of the semiconductor device according to the eighth embodiment of the present invention;

FIG. 16C is a sectional view illustrating the manufacturing step of the semiconductor device according to the eighth embodiment of the present invention;

FIG. 16D is a sectional view illustrating the step of manufacturing the semiconductor device according to the eighth embodiment of the present invention;

FIG. 16E is a sectional view showing a step of manufacturing the semiconductor device according to the eighth embodiment of the present invention;

FIG. 16F is a sectional view illustrating the step of manufacturing the semiconductor device according to the eighth embodiment of the present invention;

FIG. 16G is a sectional view illustrating the step of manufacturing the semiconductor device according to the eighth embodiment of the present invention;

FIG. 16H is a sectional view illustrating the step of manufacturing the semiconductor device according to the eighth embodiment of the present invention;

FIG. 16I is a sectional view illustrating the manufacturing step of the semiconductor device according to the eighth embodiment of the present invention;

FIG. 17A is a plan view of a messy cell portion according to a ninth embodiment of the present invention.

FIG. 17B is a sectional view of a memory cell and peripheral circuits according to the ninth embodiment of the present invention.

FIG. 18A is a sectional view illustrating the manufacturing step of the semiconductor device according to the ninth embodiment of the present invention;

FIG. 18B is a sectional view illustrating the manufacturing step of the semiconductor device according to the ninth embodiment of the present invention;

FIG. 18C is a sectional view illustrating the manufacturing step of the semiconductor device according to the ninth embodiment of the present invention;

FIG. 18D is a sectional view illustrating the step of manufacturing the semiconductor device according to the ninth embodiment of the present invention;

FIG. 18E is a sectional view illustrating the manufacturing step of the semiconductor device according to the ninth embodiment of the present invention;

FIG. 18F is a sectional view illustrating the step of manufacturing the semiconductor device according to the ninth embodiment of the present invention;

FIG. 18G is a sectional view illustrating the manufacturing step of the semiconductor device according to the ninth embodiment of the present invention;

FIG. 18H is a sectional view illustrating the manufacturing step of the semiconductor device according to the ninth embodiment of the present invention;

FIG. 18I is a sectional view illustrating the manufacturing step of the semiconductor device according to the ninth embodiment of the present invention;

FIG. 18J is a sectional view illustrating the manufacturing step of the semiconductor device according to the ninth embodiment of the present invention;

FIG. 18K is a sectional view illustrating the manufacturing step of the semiconductor device according to the ninth embodiment of the present invention;

FIG. 18L is a sectional view illustrating the manufacturing step of the semiconductor device according to the ninth embodiment of the present invention;

FIG. 19 is a cross-sectional view of a semiconductor device illustrating a problem of the ninth embodiment.

FIG. 20 is a sectional view of a semiconductor device illustrating a problem of the ninth embodiment;

FIG. 21A is a sectional view illustrating the manufacturing step of the semiconductor device according to the tenth embodiment of the present invention;

FIG. 21B is a sectional view illustrating the manufacturing step of the semiconductor device according to the tenth embodiment of the present invention;

FIG. 21C is a sectional view illustrating the manufacturing step of the semiconductor device according to the tenth embodiment of the present invention;

FIG. 21D is a sectional view illustrating the step of manufacturing the semiconductor device according to the tenth embodiment of the present invention;

FIG. 22 is a sectional view of the semiconductor device according to the eleventh embodiment of the present invention;

FIG. 23 is a cross-sectional view of a semiconductor device illustrating a problem of the eleventh embodiment.

FIG. 24 is a plan view of a memory cell part of a semiconductor device according to a twelfth embodiment of the present invention;

FIG. 25A is a sectional view of a semiconductor device according to a twelfth embodiment of the present invention;

FIG. 25B is a sectional view of the semiconductor device according to the twelfth embodiment of the present invention;

FIG. 26 is a sectional view of a semiconductor device according to a thirteenth embodiment of the present invention;

FIG. 27A is a substrate sectional view for explaining the semiconductor device according to the fourteenth embodiment of the present invention;

FIG. 27B is a substrate sectional view for explaining the semiconductor device according to the fourteenth embodiment of the present invention;

FIG. 27C is a sectional view of the substrate for explaining the semiconductor device according to the fourteenth embodiment of the present invention;

FIG. 28 is a substrate sectional view for explaining the semiconductor device according to the fifteenth embodiment of the present invention;

FIG. 29 is a sectional view of a conventional semiconductor device.

[Explanation of symbols]

Reference Signs List 4 silicon layer 5 WSi 6 SiO ₂ film 7 SiON film 8 gate electrode (word line, first layer wiring) 9 n ⁻ -type impurity diffusion layer 10 sidewall 11 SiO ₂ film 12 Si ₃ N ₄ film 13 BPSG 14 Si ₃ N ₄ film 15 contact hole 15a contact hole for storage electrode connection 15b bit line contact hole 16 plug 17 SiO ₂ film 18 silicon layer 19 WSi 20 SiO ₂ film 21 SiON film 22 bit line 23 side wall 24 SiO ₂ film 25 Si ₃ N ₄ film 27 Storage electrode 29 Dielectric film 30 Counter electrode

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yuji Yokoyama 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Kenichi Inoue 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture No. 1 Inside Fujitsu Limited (72) Koichi Hashimoto 4-1-1 Kamikadanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture 1-1 Inside Fujitsu Limited (72) Wataru Fudo 4-chome Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture No. 1 in Fujitsu Limited

Claims (48)

[Claims] 1. A semiconductor device having a memory cell region and a peripheral circuit region on a semiconductor substrate, wherein the transfer includes a pair of impurity diffusion regions formed in the substrate and a gate electrode formed on the surface of the substrate. A transistor; a first insulating film covering the top and side surfaces of the gate electrode; a second insulating film formed on the substrate so as to cover the first insulating film; and penetrating the second insulating film. A pair of contact holes reaching the pair of impurity diffusion regions; a conductive plug filled in one of the pair of contact holes and connected to one of the pair of impurity diffusion regions; Formed on the second insulating film,
A third insulating film having a first opening on the other of the pair of contact holes; and a third insulating film formed on the third insulating film, via the first opening and the other of the pair of contact holes. A bit line connected to the other of the pair of impurity diffusion regions, a fourth insulating film covering an upper surface and a side surface of the bit line, and a fourth insulating film covering a side surface of the bit line. A second opening formed in the insulating film of No. 3, and electrically connected to the conductive plug through the second opening, insulated from the bit line by the third and fourth insulating films, A semiconductor device comprising: a storage electrode extending above a line; a dielectric film formed on the surface of the storage electrode; and a counter electrode formed on the surface of the dielectric film. 2. The semiconductor device according to claim 1, wherein the second insulating film includes a lower layer composed of a stack of two or more insulating films having different etching characteristics and an upper layer formed thereon. 3. The semiconductor device according to claim 2, wherein said insulating film stack includes an oxide film and a nitride film formed thereon. 4. The semiconductor device according to claim 2, wherein the upper layer of the second insulating film includes a stack of two or more insulating films having different etching characteristics. 5. The semiconductor device according to claim 4, wherein said upper insulating film stack includes a BPSG layer and a conformal layer formed thereon. 6. The semiconductor device according to claim 5, wherein said conformal layer is a nitride film. 7. The semiconductor device according to claim 5, wherein said conformal layer is a high-temperature oxide film. 8. The semiconductor device according to claim 1, wherein said first insulating film includes a lower layer covering an upper surface of said gate electrode and an upper layer covering a side surface of said gate electrode. 9. The semiconductor device according to claim 8, wherein a lower layer of said first insulating film is a stack of an oxide film and an oxynitride film, and an upper layer of said first insulating film is an oxide film. 10. The semiconductor device according to claim 1, wherein said fourth insulating film includes a lower layer covering an upper surface of said bit line and an upper layer covering a side surface of said bit line. 11. The semiconductor device according to claim 10, wherein a lower layer of said fourth insulating film is a stack of an oxide film and an oxynitride film, and an upper layer of said fourth insulating film is an oxide film. 12. The semiconductor device according to claim 1, wherein an upper surface of said second insulating film is substantially flat. 13. The semiconductor device according to claim 1, wherein a contact hole similar to the contact hole in said memory cell region is also formed in said peripheral circuit region. 14. The semiconductor device according to claim 1, comprising a plurality of said bit lines, wherein an interval between said bit lines is smaller than a diameter of one of said pair of contact holes. 15. The semiconductor device according to claim 1, wherein the bit line includes another conductive plug filled in the other contact hole, and a wiring layer formed on the third insulating film and the other conductive plug. Semiconductor device. 16. The semiconductor device according to claim 1, wherein said bit line includes a conductive layer which covers an inner surface of said another contact hole and extends on said third insulating film. 17. The semiconductor device according to claim 1, further comprising a fifth insulating film formed on the substrate and covering the bit line and the fourth insulating film and having a substantially flat surface. 18. The semiconductor device according to claim 17, wherein said fifth insulating film includes a lower layer having two or more insulating film stacks having different etching characteristics and an upper layer formed thereon. 19. The semiconductor device according to claim 18, wherein the insulating film stack of the fifth insulating film includes a conformal oxide film and a nitride film. 20. The semiconductor device according to claim 18, wherein the fourth insulating film is formed on the bit line and has a stack of two or more insulating layers having different etching characteristics. 21. A semiconductor device having a memory cell region and a peripheral circuit region on a semiconductor substrate, wherein the transfer includes a pair of impurity diffusion regions formed in the substrate and a gate electrode formed on the substrate surface. A transistor; a first insulating film formed on the substrate so as to cover the transfer transistor; and a first contact hole penetrating through the first insulating film and reaching one of the pair of impurity diffusion regions. A conductive plug filled in the first contact hole; a second insulating film covering the conductive plug and formed on the first insulating film; and the first and second insulating films. A second contact hole penetrating a film and reaching the other of the pair of impurity diffusion regions; and a second contact hole extending over the second insulating film and via the second contact hole. To connect to And a third insulating film covering the top and side surfaces of the bit line, and a third insulating film covering the side surface of the bit line, and formed on the second insulating film on the conductive plug. A storage electrode insulated from the bit line by the second and third insulating films, and electrically connected to the conductive plug through the opening; and a dielectric formed on the surface of the storage electrode. A semiconductor device comprising: a film; and a counter electrode formed on a surface of the dielectric film. 22. The semiconductor device according to claim 21, wherein an upper surface of said first insulating film is substantially flat. 23. The semiconductor device according to claim 21, wherein said bit line comprises a metal layer. 24. The semiconductor device according to claim 21, wherein a contact hole similar to a second contact hole in said memory cell region is also formed in said peripheral circuit region. 25. A first etching stopper film formed on a conductive layer, a first insulating film formed on the stopper film, and a second etching stopper film formed on the first insulating film. A second insulating film formed on the second stopper film, wherein the thickness of the second stopper film is larger than the thickness of the first stopper film; A semiconductor device in which the thickness is formed to be larger than the thickness of the first insulating film. 26. The semiconductor device according to claim 25, wherein a surface of said first insulating film is substantially flat. 27. A method for manufacturing a semiconductor device having a memory cell region and a peripheral circuit region on a semiconductor substrate, comprising: forming a transfer transistor including a pair of impurity diffusion regions and a gate electrode on the substrate; Forming a first insulating film covering the top and side surfaces of the gate electrode; and forming a second insulating film covering the first insulating film and the transfer transistor.
Forming a contact hole penetrating the second insulating film and reaching at least one of the pair of impurity diffusion regions; filling a conductive layer in the contact hole; A step of forming a conductive plug for connection of a storage electrode; a step of covering the conductive plug to form a third insulating film on the second insulating film; and forming a bit line on the third insulating film. Forming a fourth insulating film covering the top and side surfaces of the bit line; and forming an opening in the third insulating film on the conductive plug in alignment with the fourth insulating film. A semiconductor comprising: a step of forming a storage electrode electrically connected to the conductive plug; a step of forming a dielectric film on the surface of the storage electrode; and a step of forming a counter electrode on the surface of the dielectric film Device manufacturing method. 28. The method according to claim 27, wherein the second insulating film includes a lower insulating film formed on the substrate surface so as to cover the first insulating film and an upper insulating film thereon. . 29. The method according to claim 28, wherein the lower insulating film includes a silicon nitride film. 30. The method according to claim 28, wherein the step of forming the contact hole includes a step of using the lower insulating film as an etching stopper. 31. The method according to claim 28, wherein the step of forming the second insulating film includes a step of flattening the upper insulating film. 32. The method according to claim 31, wherein the lower insulating film includes a silicon nitride film, and the upper insulating film includes an impurity-doped silicon oxide film. 33. The method of manufacturing a semiconductor device according to claim 27, wherein said step of forming a contact hole includes simultaneously forming a contact hole in said memory cell region and said peripheral circuit region. 34. The semiconductor device according to claim 28, further comprising, after forming the lower insulating film of the second insulating film, selectively removing the lower insulating film of the second insulating film in the peripheral circuit region. Manufacturing method. 35. The step of forming the transfer transistor, comprising the steps of: forming an anti-reflection film on a conductive layer; thereafter, patterning the conductive layer; and then removing the anti-reflection film. The method for manufacturing a semiconductor device according to claim 27, comprising: 36. The method according to claim 35, wherein the step of removing the anti-reflection film includes a step of selectively removing the anti-reflection film in a peripheral circuit region. 37. A method of manufacturing a semiconductor device having a memory cell region and a peripheral circuit region on a semiconductor substrate, wherein a transfer transistor including a pair of impurity diffusion regions and a gate electrode is formed on the substrate. Forming a first insulating film on the substrate so as to cover the transfer transistor; and forming a first contact hole penetrating through the first insulating film and reaching one of the pair of impurity diffusion regions. Forming a conductive layer in the first contact hole and forming a connection plug for the storage electrode; and covering the connection plug with a second plug on the first insulating film.
Forming a second contact hole penetrating the second and first insulating films and reaching the other of the pair of impurity diffusion regions; and forming the second insulating film. Forming a bit line extending upward and connected to the other impurity diffusion region via the second contact hole; forming a storage electrode electrically connected to the plug; A method for manufacturing a semiconductor device, comprising: a step of forming a dielectric film on an electrode surface; and a step of forming a counter electrode on the surface of the dielectric film. 38. The method of manufacturing a semiconductor device according to claim 37, further comprising a step of, after forming the first insulating film, substantially flattening a surface of the first insulating film. 39. The method of manufacturing a semiconductor device according to claim 37, wherein the step of forming the second contact hole forms a contact hole in the memory cell region and the peripheral circuit region simultaneously. 40. The step of forming the first insulating film includes: forming a lower insulating film on a region including the transfer transistor; and then selectively removing the lower insulating film in the peripheral region. 38. The method for manufacturing a semiconductor device according to claim 37, further comprising a step of forming an upper insulating film. 41. The step of forming the first insulating film,
Forming an uppermost insulating film on the upper insulating film, further comprising, after the step of forming the counter electrode, a step of selectively removing the uppermost insulating film using the counter electrode as a mask. The method for manufacturing a semiconductor device according to claim 37, further comprising: 42. A step of forming the transfer transistor, comprising the steps of: forming an anti-reflection film on a conductive layer; thereafter, patterning the conductive layer; and then removing the anti-reflection film. The method for manufacturing a semiconductor device according to claim 37, comprising: 43. The method according to claim 42, wherein the step of removing the anti-reflection film includes a step of selectively removing the anti-reflection film in a peripheral circuit region. 44. A method of manufacturing a semiconductor device having a memory cell region and a peripheral circuit region on a semiconductor substrate, wherein a transfer transistor including a pair of impurity diffusion regions and a gate electrode is formed on the substrate. Forming a first insulating film on the substrate so as to cover the transfer transistor; and forming a first contact hole penetrating the first insulating film and reaching one of the pair of impurity diffusion regions. Forming a conductive layer in the first contact hole and forming a plug for connecting a storage electrode; forming a second insulating film on the first insulating film to cover the plug; Forming a second contact hole penetrating the second insulating film and the first insulating film and reaching the other of the pair of impurity diffusion regions; and forming a second contact hole on the second insulating film. Extending the second Forming a bit line connected to the other impurity diffusion region via the contact hole; forming a third insulating film covering the bit line; anisotropically etching the third insulating film Forming a side wall made of the third insulating film on a side wall of the bit line; etching the second insulating film using the bit line and the side wall as a mask; Exposing, forming a storage electrode electrically connected to the connection plug, forming a dielectric film on the surface of the storage electrode, and forming a counter electrode on the surface of the dielectric film. Of manufacturing a semiconductor device having the same. 45. A step of forming a recess in the first insulating film, and a film thickness T filling the recess and extending over the first insulating film.
Forming a stack of a conductive film and a second insulating film; and etching the second insulating film and the conductive film to form a first conductive film.
Forming a third insulating film on the first wiring pattern; anisotropically etching the third insulating film to form a third insulating film on a side wall of the wiring pattern; And a step of forming a second wiring pattern on the concave portion. When the conductive film is etched, the etching amount is set to T.
+0.06 μm or more. 46. A method of manufacturing a semiconductor device having a memory cell region and a peripheral circuit region on a semiconductor substrate, comprising: forming a transfer transistor including a pair of impurity diffusion regions and a gate electrode on the substrate; Forming a first insulating film on the substrate to cover the transfer transistor; a first contact hole penetrating the first insulating film and reaching one of the pair of impurity diffusion regions; Forming a second contact hole reaching the other of the impurity diffusion regions of the above, and extending over the first insulating film and connecting to the other impurity diffusion region via the second contact hole. Forming a conductive layer; selectively etching the conductive layer to form a bit line having a recess in the second contact hole; and forming a second insulating layer covering the bit line. Forming an edge film; anisotropically etching the second insulating film to leave the second insulating film on the bit line sidewalls and on the recesses; Electrically connected to the area,
And forming a storage electrode extending over the concave portion, forming a dielectric film on the surface of the storage electrode, and forming a counter electrode on the surface of the dielectric film. . 47. A method of manufacturing a semiconductor device having a memory cell region and a peripheral circuit region on a semiconductor substrate, comprising: forming a transfer transistor including a pair of impurity diffusion regions and a gate electrode on the substrate; Forming a first insulating film on the substrate so as to cover the transfer transistor; and forming a first contact hole penetrating through the first insulating film and reaching one of the pair of impurity diffusion regions. Filling a conductive layer in the first contact hole to form a plug for connecting a storage electrode; and forming a second insulating film on the first insulating film to cover the plug. Forming a second contact hole penetrating through the second insulating film and the first insulating film and reaching the other impurity diffusion region; and extending over the second insulating film; The second contact Forming a bit line connected to the other of the pair of impurity diffusion regions via a tool, forming a third insulating film covering the bit line, and forming the third insulating film anisotropically. Etching to leave the third insulating film on the bit line sidewalls, forming a storage electrode electrically connected to the plug, and forming a dielectric film on the storage electrode surface And a step of forming a counter electrode on the surface of the dielectric film. In the step of forming the bit line, the etching is performed more than a total thickness of the conductive layer and the second insulating film. A method for manufacturing a semiconductor device in which a large amount of a conductive layer can be removed. 48. A step of forming a first etching stopper film on a conductive layer, a step of forming a first insulating film on the first stopper film, and a step of forming a first insulating film on the first insulating film. Forming a second etching stopper film thicker than the first stopper film; and forming a second insulating film thicker than the first insulating film on the second stopper film. Forming, using the second stopper film as an etching stopper, etching the second insulating film, then, etching the second stopper film, and then applying the first stopper film Manufacturing a semiconductor device, comprising: a step of etching the first insulating film by using as an etching stopper; and a step of forming an opening exposing the conductive layer by etching the first stopper film. Method.