JP2003031690A - Method for manufacturing semiconductor device and semiconductor device manufactured by using the method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a method for manufacturing a semiconductor device which can reduce process margin necessary for control adjustment of CMP polishing by preventing exposure of a capacitor and short circuit of wiring which become a problem in a surface flattening process of a multilayer wiring type semiconductor device having a DRAM region and a logic region. SOLUTION: In the method for manufacturing a semiconductor device having the DRAM region provided with a stacked capacitor and the logic region on a semiconductor substrate, etching is performed when a cell plate pattern is formed in such a manner that an upper capacitor electrode layer 124 is left at least partly in the logic region. As a result, a step-difference between the DRAM region and the logic region in the case of the CMP polishing can be resolved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device including a step of planarizing a surface by using a CMP method, and more particularly, a multi-layer wiring type semiconductor device having a DRAM region and a logic region. A method of manufacturing a semiconductor device and a method of manufacturing the same, which can effectively prevent the exposure of the capacitor and the short circuit of the wiring, which are problems in the surface flattening process of the above, and can reduce the process margin required for the control adjustment of the CMP polishing. The present invention relates to a semiconductor device.

[0002]

2. Description of the Related Art DRAM is a memory device composed of a transistor and a capacitor, and has a higher density than before.
Various structures and manufacturing methods for manufacturing highly integrated semiconductor devices have been studied. The competition for DRAM type semiconductor devices is intensifying, and it is an important issue how to manufacture highly integrated and high performance semiconductor devices at low cost. Therefore, a simpler structure is desired for the capacitor, and a structure that can secure a sufficient capacity with a simple structure has been studied. As one of such capacitor structures, a stack capacitor electrode having a cylindrical shape is mainstream.

Electrical equipment control and video / audio signal processing are carried out by exchanging data between a memory, a microcomputer and a logic. Due to advances in both process / design technologies, eRAM (embedded RAM) is a single chip of these LSIs. ) Has received great attention as a new device (system LSI). Compared to general-purpose memory and microcomputer combination, eRAM that integrates ASIC and microcomputer and large-capacity memory can not only make the equipment compact, but also speed up data transfer and reduce power consumption by expanding the bus width. Can be realized.

As the semiconductor device is further miniaturized and the element structure is complicated as described above, and the number of layers of the multi-layer wiring of the logic system is increased, the unevenness of the IC surface is further increased and the steps are increased. Flattening technology is becoming increasingly important.

FIG. 15 shows a DR formed by a DRAM having a typical stack capacitor which has been conventionally used.
It is sectional drawing of AM mixed logic. First Al wiring layer 12
Structures up to 9 are shown. The DRAM embedded logic is composed of a DRAM area and a logic area.
(A) is the central portion of the M / C (memory cell) in the DRAM area,
(B) is the M / C peripheral portion of the DRAM area, and (c) is the logic area.

In this type of mixed device of DRAM and logic, a cylindrical stack capacitor (concave) having a certain height is formed in the DRAM part, but the logic part does not have such a stack capacitor. It is difficult to form highly reliable wiring that extends over The stack capacitor includes the lower capacitor electrode layer 122 and the dielectric film 1.
23 and the upper capacitor electrode layer 124.

Until now, after forming an interlayer insulating film (TEOS film) 120 on the upper capacitor electrode (cell plate) 124 and polishing by CMP method (chemical mechanical polishing method), protective insulation of 50 nm to 100 nm is performed. Membrane (TEOS
Film) 133 is formed, and after contact holes are opened, barrier metal (TiN / Ti) 127, tungsten (W) 1
A flow for forming a W plug by depositing 28 and etching back the entire surface by dry etching has been taken.

In the above process flow, W128
In order to reduce the short circuit between the first Al wiring layers 129 due to the remaining of the
27, tungsten (W) 128 is deposited, and then CMP is performed instead of dry-etching the entire surface.
A flow including W-CMP for polishing W128 by the method is often used.

[0009]

However, in the prior art, as described above, the cell plate 124 exists in the DRAM area but the cell plate 12 exists in the logic area.
4 does not exist, there is a difference in height from the substrate between the DRAM region and the logic region during CMP or W-CMP of the inter-layer TEOS film 120, so that the following problem occurs.

(A) CM after the inter-layer TEOS film 120 is formed
During P polishing and W-CMP polishing, a protective insulating film (TEOS
Film 133 and the inter-layer TEOS film 120 are over-polished, and the TEOS film 12 on the cell plate 124 is formed at the center and end (peripheral) of the M / C in the DRAM region.
Since there is a difference in the thickness of 0, there is a problem that it is difficult to control the CMP polishing (FIG. 16 (1)).

(B) When over-polishing during W-CMP polishing becomes severe, the protective insulating film 133 on the cell plate 124 and the interlayer TEOS film 120 are formed at the center and the end of the M / C of the DRAM region on the device. This causes a fatal problem that the cell plate 124 is completely removed by polishing and is exposed. At this time, when the first Al wiring layer 129 is formed on the exposed cell plate 124, there is a problem that the first Al wiring layer 129 is short-circuited via the exposed cell plate 124 (FIG. 16 ( 2)).

(C) When the TEOS film 133 on the cell plate 124 is removed by overpolishing during W-CMP polishing, the swell of the capacitor normally insulated by the TEOS film 133 and the first Al wiring layer 129 are short-circuited. There was also the problem that it would end up (Fig. 16 (3)).

The present invention has been made in view of the above circumstances, and effectively exposes the capacitor and shorts the wiring, which are problems in the surface flattening process of the multi-layer wiring type semiconductor device having the DRAM region and the logic region. To prevent and CM
An object of the present invention is to obtain a semiconductor device manufacturing method capable of reducing a process margin required for P polishing control adjustment, and a semiconductor device manufactured using the method.

[0014]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises a DRAM region having a stack capacitor on a semiconductor substrate,
In a method of manufacturing a semiconductor device having a logic region, a lower capacitor electrode layer of the stack capacitor and a dielectric film are provided in an insulating film on a semiconductor substrate, and then an upper capacitor electrode layer is deposited in the DRAM region and the logic region. And forming a cell plate pattern in the DRAM region and the logic region by etching the upper capacitor electrode layer so that the upper capacitor electrode layer at least partially remains in the logic region. The method is characterized by including the step 2 and a third step of depositing an interlayer film on the cell plate pattern and then polishing and planarizing the surface of the interlayer film by a CMP method.

According to the present invention, the DRA is formed by forming the cell plate pattern not only in the DRAM area requiring the upper capacitor electrode but also in the logic area.
The step difference between the M region and the logic region can be eliminated.

In the method of manufacturing a semiconductor device according to the next invention, in the above invention, in the second step, a dummy cell plate pattern is formed on the entire surface of the logic region except a portion corresponding to a contact hole portion. It is characterized by doing.

According to the present invention, in the second step, the dummy cell plate pattern is formed on the entire surface of the logic region except the portion corresponding to the contact hole portion. As a result, the step difference between the DRAM area and the logic area can be eliminated.

In the method of manufacturing a semiconductor device according to the next invention, in the above-mentioned invention, in the second step, dummy cell plate patterns are dispersedly provided in portions other than a portion corresponding to a contact hole portion in the logic region. It is characterized by forming.

According to the present invention, in the second step, dummy cell plate patterns are dispersively formed in the logic region except for the portion corresponding to the contact hole portion. As a result, the step difference between the DRAM area and the logic area can be eliminated.

A semiconductor device manufacturing method according to the next invention is a DRA having a stack capacitor on a semiconductor substrate.
In a method of manufacturing a semiconductor device having an M region and a logic region, a lower capacitor electrode layer of the stack capacitor and a dielectric film are provided in an insulating film on a semiconductor substrate, and then an upper capacitor is provided in the DRAM region and the logic region. A first step of depositing an electrode layer, a second step of depositing an insulating film on the upper capacitor electrode layer, a step of removing the upper capacitor electrode layer and the insulating film deposited in the logic region, and the DRAM A third step of forming a cell plate pattern having the insulating film deposited in the DRAM area by etching the upper capacitor electrode layer and the insulating film so that a cell plate pattern is formed in the area; Fourth, after depositing an interlayer film thereon, polishing the surface of the interlayer film by CMP to planarize the surface. Characterized in that it comprises a step.

According to the present invention, by providing the cell plate pattern on which the insulating film is deposited, the insulating film on the cell plate pattern is exposed and the cell plate itself is not exposed even if it is slightly overpolished. , The fine adjustment of the CMP polishing amount becomes unnecessary, and the process margin required for the control adjustment of the CMP polishing can be reduced.

A semiconductor device manufacturing method according to the next invention is a DRA having a stack capacitor on a semiconductor substrate.
In a method of manufacturing a semiconductor device having an M region and a logic region, a lower capacitor electrode layer of the stack capacitor and a dielectric film are provided in an insulating film on a semiconductor substrate, and then an upper capacitor is provided in the DRAM region and the logic region. A first step of depositing an electrode layer, a second step of depositing an insulating film on the upper capacitor electrode layer, and the upper portion so that the upper capacitor electrode layer remains at least partially in the logic region. The DRAM by etching the capacitor electrode layer and the insulating film
A third step of forming a cell plate pattern in which the insulating film is deposited on the region and the logic region, and after depositing an interlayer film on the cell plate pattern, polishing the surface of the interlayer film using a CMP method. And a fourth step of flattening.

According to the present invention, the DRA is formed by forming the cell plate pattern not only in the DRAM region requiring the upper capacitor electrode but also in the logic region.
The step difference between the M region and the logic region can be eliminated. Further, by providing the cell plate pattern on which the insulating film is deposited, the insulating film on the cell plate pattern is only exposed and the cell plate itself is not exposed even if it is slightly over-polished. Therefore, the CMP polishing amount is finely adjusted. Becomes unnecessary and CMP
The process margin required for polishing control adjustment can be reduced.

In the method of manufacturing a semiconductor device according to the next invention, in the above invention, the insulating film is made of a material having a CMP polishing rate lower than that of the upper capacitor electrode layer.

According to the present invention, by using the insulating film having a CMP polishing rate lower than that of the upper capacitor electrode layer, the capacitor is not easily exposed even if it is over-polished.

In the method of manufacturing a semiconductor device according to the next invention, a DRAM region having a stack capacitor and a logic region are formed on the same semiconductor substrate, and a capacitor for an electric circuit of the logic region is formed in the logic region. A method of manufacturing a semiconductor device, comprising: forming a lower capacitor electrode of the stack capacitor and a lower capacitor electrode of the electric circuit capacitor in an insulating film of the DRAM region and an insulating film of the logic region, respectively. A second step of forming a dielectric film on the lower capacitor electrode of the stack capacitor and on the lower capacitor electrode of the capacitor for electric circuit, respectively.
A third step of depositing an upper capacitor electrode layer on the DRAM region and the logic region, and etching the upper capacitor electrode to form a cell plate pattern of the stack capacitor and a cell plate pattern of the capacitor for the electric circuit. And a fifth step of forming an interlayer film on the cell plate pattern and then polishing and planarizing the surface of the interlayer film by using a CMP method. To do.

According to the present invention, the cell plate pattern formed in the logic region is used as the upper capacitor electrode of the capacitor.

A semiconductor device manufacturing method according to the next invention is a DRA having a stack capacitor on a semiconductor substrate.
In a method of manufacturing a semiconductor device having an M region and a non-DRAM region, a lower capacitor electrode layer of the stack capacitor and a dielectric film are provided in an insulating film on a semiconductor substrate, and then the DRAM region and the non-DRAM region are formed. A first step of depositing an upper capacitor electrode layer;
The DRAM region and the non-DR are etched by etching the upper capacitor electrode layer so that the upper capacitor electrode layer also remains at least partially in the RAM region.
A second step of forming a cell plate pattern in the AM region, and a third step of depositing an interlayer film on the cell plate pattern and then polishing and planarizing the surface of the interlayer film using a CMP method. And are included.

According to the present invention, not only the DRAM region requiring the upper capacitor electrode but also the non-DRAM region (for example, the region between the cell blocks,
By forming the cell plate pattern also in a vacant area around the dicing line), the step difference between the DRAM area and the non-DRAM area can be eliminated.

A semiconductor device according to the next invention is manufactured by using the manufacturing method according to any one of claims 1 to 8.

According to the present invention, since the step difference between the DRAM region and other regions is eliminated, it is effective to expose the capacitor and short the wiring, which are problems in the surface flattening process of the multi-layer wiring type semiconductor device. And the process margin required for control adjustment of CMP polishing can be reduced.

[0032]

BEST MODE FOR CARRYING OUT THE INVENTION Referring to the accompanying drawings,
A preferred embodiment of a method of manufacturing a semiconductor device according to the present invention and a semiconductor device manufactured by using the method will be described in detail.

Embodiment 1. FIG. 1 is a sectional view showing the structure of a semiconductor device obtained by the manufacturing method according to the first embodiment.

The semiconductor device of the first embodiment comprises a DRAM region and a logic region. FIG. 1A shows the M / C (memory cell) central portion of the DRAM region, and FIG. 1B shows the M / C of the DRAM region. The peripheral area, (c), is a logic area. Although only the first metal wiring 129 is shown in a simplified manner in this drawing, generally, metal wiring of about 3 to 6 layers is used.

100 is a semiconductor substrate made of P-type Si or the like,
101 is a bottom N well region, 102 is a P-type well region
Region, 103 is an N-type LDD region, and 104 is an N + high concentration source.
Source / drain, and 105 is a silicide layer on the active region.
Yes, titanium silicide (Ti _xSi_y) And cobalt siri
Side (Co_xSi_y) Consists of. 106 is an isolation oxide film,
107 is a gate oxide film formed of a silicon oxide film, 1
08 is a policy formed of phosphorus-doped polysilicon or the like.
Recon film, 109 is tungsten silicide (WS
i₂) Is a silicide layer formed of, for example. Polysilico
The film 108 and the silicide layer 109 are transistors
Of the gate electrode (word line). Also, 110,
111 is an insulating film that covers the gate electrode of the transistor
Yes, 112, 113 are sidewalls, 110
And 112 are silicon oxide films, and 111 and 113 are
A silicon nitride film is used.

Further, 114 is a plug made of a polysilicon film such as phosphorus-doped polysilicon, and 115 is BPSG.
An interlayer insulating film made of (Boro-Phospho-Silicate-Glass) or the like, and a nitride film 116. Reference numerals 117 to 119 are insulating films made of an oxide film or the like. An interlayer insulating film 120 is made of TEOS (Tetraethoxysilane) or the like. 12
Reference numeral 1 is a plug made of phosphorus-doped polysilicon or the like.

In the memory cell portion shown in FIGS. 1A and 1B, 125 is a barrier metal made of TiN / Ti or the like,
Reference numeral 126 is a bit line for taking out data from the memory cell, which is composed of W or the like. 122 is a lower capacitor electrode formed of phosphorus-doped polysilicon or the like, 123 is a capacitor dielectric film formed of a silicon oxide film, a silicon oxynitride film, or the like, and 124 is a cell plate (upper capacitor) formed of phosphorus-doped polysilicon or the like. Electrodes). The lower capacitor electrode 122 and the cell plate 124 are electrically insulated by the capacitor dielectric film 123, and the lower capacitor electrode layer 122 and the capacitor dielectric film 1 are electrically insulated.
23 and the cell plate 124 form a cylindrical stack capacitor.

In this DRAM, a memory cell is composed of a MOS transistor including a gate electrode, a source and a drain, and the above-mentioned stack capacitor.

In the logic area shown in FIG. 1C,
127 is a barrier metal made of TiN / Ti or the like, 129
Is a first metal wiring made of AlCu or the like, and 128 is a metal plug (here, W plug) connecting the first metal wiring 129 and the bit line 126 or the bit line 126 and the diffusion region 104. The metal plug 128 may also be used in the memory cell section. Plugs 114, 121
The diffusion region 104 and the lower capacitor electrode 122 of the stack capacitor are connected via the.

Next, a method of manufacturing the semiconductor device including the DRAM region and the logic region according to the first embodiment of the present invention will be described. 2A to 2D are process cross-sectional views showing the method of manufacturing the semiconductor device of the first embodiment. Also in FIG. 2, the left drawing is the DRA.
M / C center of M area, central drawing is M / C of DRAM area
The peripheral area of C and the right drawing correspond to the logic area. In addition,
Here, a manufacturing method after forming the insulating film 119 will be described, and description up to the formation of the insulating film 119 will be omitted.

First, a cylindrical capacitor hole is formed in the insulating film 119 in the DRAM region (FIG. 2).
(A)).

After forming a lower capacitor electrode 122 made of doped polysilicon such as phosphorus-doped polysilicon or doped amorphous silicon on the inner wall of the capacitor hole formed in the insulating film 119, this lower capacitor electrode 122 is formed. A capacitor dielectric film 123 is formed of a silicon oxide film or a silicon oxynitride film so as to cover it. Next, the upper capacitor electrode layer 124 made of polysilicon or the like is deposited on the entire surface including the DRAM region and the logic region (FIG. 2B).

Next, photolithography is performed using the photoresist 132 and the upper capacitor electrode layer 124 is etched to form a cell plate pattern (FIG. 2C).
(D)). That is, the cell plate pattern 124 is formed by uniformly applying the photoresist 132 to the upper capacitor electrode 124 and then performing photolithography. Plan views of the mask pattern for photolithography at this time are shown in FIGS. 4 and 5, (a) is a plan view of the entire DRAM embedded logic, and (b) is an M of the DRAM embedded logic.
/ C (memory cell) is an enlarged view showing the boundary between the block and the logic portion, (c) is an enlarged view of M / C. 201
Indicates a position with a contact hole opening, and 202 indicates a position with a cell plate pattern.

FIG. 4 shows the first pattern. In the first pattern, dummy cell plate patterns 202 are dispersedly arranged in the region other than the insulating portion around the portion 201 where the contact hole is opened in the logic region (FIG. 4B). Further, in the M / C (memory cell) area, a dummy pattern of the cell plate is also provided in an area (for example, the sense amplifier band 205) between the cell blocks which does not normally require the cell plate (eg, the sense amplifier band 205) (see FIG. )).

FIG. 5 shows the second pattern. In the second pattern, the electrically insulating portion 20
4 and thereafter, the upper capacitor electrode is removed only in the portion 201 where the contact is opened and the peripheral portion 203 thereof, and the cell plate 202 is formed on the entire surface of the other logic region (FIG. 5B).

Here, conventionally, as shown in FIG. 6, the cell plate 202 is formed only on the M / C of the DRAM region which requires the cell plate, but in the first embodiment, as shown in FIG. As shown in FIG. 5, not only on the M / C of the DRAM area that requires the cell plate 202, but also in the area that does not normally require the cell plate 202 (logic area,
The cell plate 2 is also used in the area between the cell blocks and the empty area around the dicing line 206.
By leaving 02, DRA during CMP
The height of the M region from the semiconductor substrate is the same as the height of the logic region from the semiconductor substrate.

Next, TEOS is deposited on the entire surface of the semiconductor substrate to form an interlayer insulating film 120 (FIG. 2E), and CMP is performed.
The surface of the interlayer insulating film 120 is polished and planarized by using the method. At this time, while flowing a liquid slurry (polishing liquid) containing silica particles, the surface of the semiconductor device attached to the spindle is brought into contact with the polishing pad on the surface of the rotary table for polishing (FIG. 2 (f)).

At this time, conventionally, since the cell plate is patterned by leaving only the M / C portion of the DRAM region requiring the upper capacitor electrode, a step is formed between the DRAM region and the logic region as shown in FIG. 3A. Occurs, and due to this step difference, after CMP polishing, as shown in FIG.
There was a difference in film thickness of the interlayer insulating film 120 between the DRAM area and the logic area. Therefore, the first Al wiring layer 129 is short-circuited via the exposed cell plate 124, or the swelling of the capacitor normally insulated by the protective insulating film 133 and the first Al wiring layer 129 are short-circuited (FIG. 16). (2) (3)) There is a problem that it is difficult to control CMP polishing.

On the other hand, in the present invention, since the cell plate 124 is arranged not only in the M / C portion of the DRAM region which requires the upper capacitor electrode but also in the logic region, the arrow K in FIG. The step between the DRAM area and the logic area indicated by is eliminated, and even after CMP polishing, FIG.
As shown in (f), the interlayer insulating film 120 on the M / C block in the DRAM region has a uniform thickness, and the above-mentioned problems can be solved.

After CMP polishing, the flattened interlayer insulating film 1
A protective insulating film (TEOS film) 133 is formed on the film 20. Next, a contact hole is opened, a barrier metal (TiN / Ti) 127 and W128 are formed, and CM is performed again.
W128 and barrier metal 12 on the semiconductor surface using the P method
7. The protective insulating film 133 is polished and removed to form a W plug (FIGS. 2G and 2H). Then, a first Al wiring layer 129 and a barrier metal 130 are formed on this W plug (FIG. 2 (i)).

As described above, according to the first embodiment, D
The M of the DRAM region that requires the upper capacitor electrode so that the height of the RAM region from the semiconductor substrate and the height of the logic region from the semiconductor substrate are substantially the same.
Cell plate 1 not only in the / C part but also in the logic area
24 are arranged. As a result, the step difference between the DRAM region and the logic region is eliminated, so that the thickness of the interlayer insulating film 120 on the DRAM region M / C can be made uniform as shown in FIG. 2F even after CMP polishing. Therefore, DRA
It is possible to effectively prevent the exposure of the capacitor and the short circuit of the wiring caused by the step of the M region / logic region, and reduce the process margin required for the control adjustment of the CMP polishing.

Embodiment 2. Next, the second embodiment will be described. FIG. 7 is a cross-sectional view showing the structure of a semiconductor device obtained by using the manufacturing method of the second embodiment. Since the reference numerals common to the first and second embodiments show the same configurations, only different parts will be described in detail here.

In the second embodiment, the upper capacitor electrode layer 1
Insulating film 1 which functions as a CMP stopper on 24
31 is provided. The second embodiment is DR
To solve the problem that a difference in film thickness of the interlayer insulating film 120 occurs after CMP polishing due to a step difference between the AM region and the logic region, and this causes a short path between the cell plate 124 and the first Al wiring layer 129 or the first Al wiring layer 129. Therefore, the film structure of the cell plate 124 is changed.

In the second embodiment, the insulating film 131 is
A material having a smaller CMP polishing rate than the upper capacitor electrode 124 is used. As the insulating film 131, for example,
It is preferable to use a nitride film such as SiN having a thickness of about 500Å.

Next, a method of manufacturing a semiconductor device having a DRAM area and a logic area according to the second embodiment of the present invention will be described. Note that here, a manufacturing method after the insulating film 119 is formed is described, and description up to the formation of the insulating film 119 is omitted. 8A to 8D are process cross-sectional views showing the method of manufacturing the semiconductor device of the second embodiment. Also in FIG. 8, the left drawing is the DRA.
M / C center of M area, central drawing is M / C of DRAM area
The peripheral area of C and the right drawing correspond to the logic area.

First, a cylindrical capacitor hole is formed in the insulating film 119 in the DRAM area (FIG. 8).
(A)).

After the lower capacitor electrode 122 made of doped polysilicon such as phosphorus-doped polysilicon or doped amorphous silicon is provided on the inner peripheral wall of the capacitor hole formed in the insulating film 119, a silicon oxide film or a silicon film is formed. Capacitor dielectric film such as oxynitride film 1
23 is formed. Next, the upper capacitor electrode layer 124 is formed of polysilicon or the like on the entire surface of the semiconductor device including the DRAM region and the logic region (FIG. 8B), and the insulating layer 131 is further deposited thereon (FIG. 8C). ). As the insulating film 131, the CMP from the upper capacitor electrode 124 is performed.
An insulating film having a low polishing rate, for example, a nitride film such as SiN is used.

Next, photolithography is performed using the photoresist 132, and the upper capacitor electrode 124 and the insulating layer 13 are formed.
1 is etched to leave the cell plate 12 only on the M / C of the DRAM area which requires the cell plate 124.
4 and the insulating layer 131 are removed (FIG. 8D).
(E)). Thus, the upper capacitor electrode 124 and the insulating film 131 are removed from the logic region,
A cell plate pattern in which an insulating film 131 is deposited is formed in the AM region.

Next, after forming an interlayer insulating film 120 made of TEOS or the like on the entire surface of the semiconductor substrate (FIG. 8 (f)),
The semiconductor surface is polished and planarized by using the CMP method. At this time, while flowing a liquid slurry (polishing liquid) containing silica particles, the surface of the semiconductor device attached to the spindle is brought into contact with the polishing pad on the surface of the rotary table for polishing.

In the second embodiment, since the cell plate pattern is formed only in the M / C block portion of the DRAM area, the interlayer insulating film 120 as shown in FIG. And a difference in film thickness occurs in the interlayer insulating film 120 on the M / C in the DRAM region after CMP polishing due to this step (FIG. 8G).

Conventionally, it was necessary to finely adjust the polishing amount at the time of CMP polishing in order to prevent the upper capacitor electrode 124 at the end of the M / C from being exposed. The insulating layer 131
By functioning as a stopper for CMP polishing,
Fine adjustment of the P polishing amount becomes unnecessary, and the process margin required for control adjustment of CMP can be reduced.

After CMP polishing, a protective insulating film (TEOS film) 133 is formed on the interlayer insulating film 120. Next, a contact hole is opened and a barrier metal (TiN / T
i) 127 is formed into a film, and the W128, the barrier metal 127, and the TEOS film 133 on the semiconductor surface are polished and removed again using the CMP method to form a W plug (FIG. 8H).
(I)), a first Al wiring layer 129 and a barrier metal 130 are formed on this W plug (FIG. 8).
(J)).

According to the second embodiment, by providing the insulating layer 131 on the upper capacitor electrode layer 124, even if the insulating film 131 on the cell plate 124 is exposed by slightly overpolishing, the cell plate 124 itself is Not exposed,
Fine adjustment of the CMP polishing amount becomes unnecessary.

Third Embodiment Next, a third embodiment will be described. FIG. 9 is a cross-sectional view showing the structure of a semiconductor device obtained by using the manufacturing method of the third embodiment. Since common reference numerals in the first and third embodiments indicate the same configuration, only different parts will be described in detail here.

The third embodiment is an application example of the first embodiment, in which the cell plate pattern formed in the logic region is used to form the capacitor 300 also in the logic region. The capacitor 300 provided in the logic region can be used as the capacitance of an electric circuit, for example. Conventionally, when the capacitor is provided in the logic region, the capacitance of the gate oxide film 107 was used, but in the third embodiment, the cell plate pattern formed in the logic region is used as the upper capacitor electrode of the capacitor 300. By doing so, a capacitor is formed.

Next, a method of manufacturing a semiconductor device according to the third embodiment of the invention will be described. 10 and 11 are process cross-sectional views showing the method of manufacturing the semiconductor device of the third embodiment. 10 and 1
Also in FIG. 1, the left drawing corresponds to the M / C central portion of the DRAM area, the central drawing corresponds to the M / C peripheral portion of the DRAM area, and the right drawing corresponds to the logic area. In this case, the insulating film 1
A manufacturing method after forming the insulating film 119 will be described, and description up to the formation of the insulating film 119 will be omitted.

First, a cylindrical capacitor hole is formed in the M / C insulating film 119. In addition, a contact hole for the connection pattern of the capacitor is formed in the logic region (FIG. 10A).

Next, the lower capacitor electrode 122 made of doped amorphous silicon is deposited on the insulating film 119 (FIG. 10B), and the photoresist 132 is further deposited.
Patterning is performed by photolithography using
(C)). The thickness of the lower capacitor electrode 122 is 250
It is preferably about Å. In the DRAM area,
After photoengraving, the lower capacitor electrode 122 left on the inner peripheral wall and bottom surface of the capacitor hole becomes the lower capacitor electrode of the stack capacitor. Further, in the logic region, the lower capacitor electrode 122 left on the insulating film 119 becomes the lower capacitor electrode of the flat plate-shaped capacitor (FIG. 10D).

Subsequently, an insulating film (SiON) 123 for a capacitor in the DRAM region and a flat plate-like capacitor is formed, and further an upper capacitor electrode layer made of doped polysilicon such as phosphorus-doped polysilicon or doped amorphous silicon. 124 is deposited (FIG. 10)
(E)).

Next, photolithography is performed using the photoresist 132, and the upper capacitor electrode layer 124 is etched to form a cell plate pattern. Especially for the logic area, the cell plate pattern 1 of the logic area
A cell pattern is formed by removing portions other than the portion to be left as 24 and the portion to be left as a dummy cell plate pattern (FIGS. 10F and 11A). In this way
The lower electrode 122 and the capacitor dielectric film 1 are provided in the DRAM area.
23 and the cell plate pattern 124 are formed, and a flat capacitor including the lower capacitor electrode 122, the capacitor dielectric film 123, and the cell plate pattern 124 is formed in the logic region (FIG. 11A).

Next, an interlayer insulating film 120 made of TEOS or the like is formed on the entire surface of the semiconductor substrate (FIG. 11B). Then, the surface of the semiconductor is polished and planarized by using the CMP method (FIG. 11C). At this time, while flowing a liquid slurry (polishing liquid) containing silica particles, the surface of the semiconductor device attached to the spindle is brought into contact with the polishing pad on the surface of the rotary table for polishing.

At this time, the level difference of about 500 Å generated by the lower electrode 122 of the capacitor formed in the logic region is flattened by the CMP method.

After CMP polishing, the flattened interlayer insulating film 1
A protective insulating film 133 is formed on the film 20. Next, a contact hole is opened to form a barrier metal (TiN / Ti).
127 and W128 are formed into a film, the barrier metal 127 and W128 on the semiconductor surface are polished and removed again by using the CMP method to form a W plug (FIGS. 11D and 11E), and further, at a predetermined position. Then, a first Al wiring layer 129 and a barrier metal 130 are formed (FIG. 11F).

As described above, according to the third embodiment, by utilizing the cell plate pattern formed in the logic region, the capacitor can be formed in the logic region with a relatively small number of steps.

Also, in order to make the height of the DRAM region from the semiconductor substrate and the height of the logic region from the semiconductor substrate substantially the same, only in the M / C portion of the DRAM region requiring the upper capacitor electrode. DRA by arranging the cell plate 124 in the logic area instead of the DRA
Since the step between the M area and the logic area is eliminated, CMP
Even after polishing, as shown in FIG.
The thickness of the interlayer insulating film 120 at the C end can be made uniform.

Fourth Embodiment The fourth embodiment is an application example in which the first embodiment and the second embodiment are combined.
As shown in FIG. 12, in the semiconductor device of the fourth embodiment, an insulating film 131 as a CMP polishing stop layer is provided on the upper capacitor electrode layer 124, and a CM
A DR requiring an upper capacitor electrode so that the height of the DRAM region from the semiconductor substrate and the height of the logic region from the semiconductor substrate at the time of P are substantially the same.
The cell pattern 124 is arranged not only in the M / C portion of the AM area but also in the logic area.

13 and 14 are process sectional views showing a method of manufacturing a semiconductor device according to the fourth embodiment. In addition, here
The manufacturing method after forming the insulating film 119 will be described, and description up to the formation of the insulating film 119 will be omitted.

First, a cylindrical capacitor hole is formed in the insulating film 119 (FIG. 13A).

After the lower capacitor electrode 122 made of doped polysilicon such as phosphorus-doped polysilicon or doped amorphous silicon is provided in the capacitor hole formed in the insulating film 119 in the DRAM region,
A capacitor dielectric film 123 is formed of a silicon oxide film or a silicon oxynitride film, and an upper capacitor electrode layer 124 is formed of polysilicon or the like on the entire surface of the semiconductor device (FIG. 13).
(B)). Further, an insulating layer 131 is formed on the upper capacitor electrode.
Are formed (FIG. 13C).

Next, photolithography is performed using the photoresist 132 to form the upper capacitor electrode layer 124 and the insulating layer 1.
31 is etched to form a cell pattern in which the insulating film 131 is laminated in the DRAM region and the logic region (FIGS. 13D and 13E). That is, the cell plate 1
Not only on the M / C of the DRAM area that requires 24,
The insulating film 13 is also formed in a region that does not require the cell plate 202 (a logic region, a region between cell blocks, a vacant region around the dicing line 206, etc.).
The cell plate pattern 124 in which 1 is stacked is left.

Next, an interlayer insulating film 120 made of TEOS or the like is formed on the entire surface of the semiconductor substrate (FIG. 13 (f)). Then, the semiconductor surface is polished and flattened by the CMP method (FIG. 14A).

At this time, conventionally, since the cell plate is patterned by leaving only the M / C portion of the DRAM area requiring the upper capacitor electrode, a step is generated between the DRAM area and the logic area. After CMP polishing, there was a difference in film thickness of the interlayer insulating film 120 in the DRAM area / logic area. Therefore, the first Al wiring layer 129 is short-circuited via the exposed cell plate 124, and the swelling of the capacitor normally insulated by the protective insulating film (TEOS film) 133 and the first Al wiring layer 1 are caused.
29 and short-circuited (Fig. 16 (2) (3)),
There is a problem that control of CMP polishing is difficult.

On the other hand, in the fourth embodiment, the DRAM
In order to make the height of the region from the semiconductor substrate and the height of the logic region from the semiconductor substrate substantially the same, not only in the M / C portion of the DRAM region requiring the upper capacitor electrode but also in the logic region. Since the step between the DRAM region and the logic region is eliminated by disposing the cell plate 124, the thickness of the inter-layer insulating film 120 on the DRAM region M / C as shown in FIG. It becomes uniform, and the above-mentioned problems can be solved.

The insulating film 13 is formed on the cell plate 124.
By providing No. 1, the insulating film 131 is only exposed even if it is slightly over-polished, and the cell plate 124 itself is not exposed. Therefore, fine adjustment of the CMP polishing amount becomes unnecessary,
The process margin required for control and adjustment of CMP polishing can be reduced.

After CMP polishing, the flattened interlayer insulating film 1
A TEOS film 133 is formed on the film 20. Next, a contact hole is opened to form a barrier metal (TiN / Ti).
127 and W128 are formed into a film, and the barrier metal 127 and W128 on the semiconductor surface are removed by polishing again using the CMP method to form a W plug (FIGS. 14B and 14C). A first Al wiring layer 129 and further a barrier metal 130 are formed (FIG. 14D).

As described above, according to the fourth embodiment, D
The M of the DRAM region that requires the upper capacitor electrode so that the height of the RAM region from the semiconductor substrate and the height of the logic region from the semiconductor substrate are substantially the same.
Cell plate 1 not only in the / C part but also in the logic area
By disposing 24, the step difference between the DRAM region and the logic region is eliminated, so that even after CMP polishing, FIG.
As shown in (a), the thickness of the interlayer insulating film 120 on the DRAM region M / C can be made uniform.

Further, since the insulating layer 131 is provided on the upper capacitor electrode layer 124, the problem that the first Al wiring layer 129 is short-circuited via the exposed cell plate 124 is eliminated, and the yield is improved.

[0088]

As described above, according to the present invention, by disposing the cell plate not only in the DRAM region requiring the upper capacitor electrode but also in the logic region, a step difference between the DRAM region and the logic region can be obtained. Therefore, the thickness of the interlayer insulating film on the DRAM region M / C can be made uniform even after the CMP polishing. As a result, it is possible to effectively prevent the exposure of the capacitor and the short circuit of the wiring, which are problems in the surface flattening step, and it is possible to reduce the process margin required for the control adjustment of the CMP polishing.

According to the next invention, since the dummy cell plate pattern is formed on the entire surface of the logic region except the portion corresponding to the contact hole, the step difference between the DRAM region and the logic region is eliminated. After the CMP polishing, the thickness of the interlayer insulating film on the M / C in the DRAM region can be made uniform, and the exposure of the capacitor and the short circuit of the wiring, which are problems in the surface flattening process, can be effectively prevented. .

According to the next invention, since the dummy cell plate pattern is dispersively formed in the logic region except the portion corresponding to the contact hole portion, the step difference between the DRAM region and the logic region is eliminated. In addition, the thickness of the interlayer insulating film on the DRAM region M / C can be made uniform even after CMP polishing, and the exposure of the capacitor and the short circuit of the wiring, which are problems in the surface flattening process, can be effectively prevented. .

According to the next invention, by providing the cell plate pattern on which the insulating film is deposited, the insulating film on the cell plate pattern is exposed and the cell plate itself is not exposed even if it is slightly overpolished. For CMP
Fine adjustment of the polishing amount becomes unnecessary, and the process margin required for control adjustment of CMP polishing can be reduced.

According to the next invention, by forming the cell plate pattern not only in the DRAM region requiring the upper capacitor electrode but also in the logic region, the DR
The step difference between the AM area and the logic area can be eliminated. Further, by providing the cell plate pattern on which the insulating film is deposited, the insulating film on the cell plate pattern is only exposed and the cell plate itself is not exposed even if it is slightly over-polished. Therefore, the CMP polishing amount is finely adjusted. Is unnecessary, CM
The process margin required for control adjustment of P polishing can be reduced, and the product yield can be further improved.

According to the next invention, by using the insulating film having the CMP polishing rate smaller than that of the upper capacitor electrode layer, the capacitor is more difficult to be exposed even after over-polishing.

According to the next invention, by using the cell plate pattern formed in the logic region as the upper capacitor electrode of the capacitor, the capacitor can be formed in the logic region with a relatively small number of manufacturing steps.

According to the next invention, not only the DRAM region requiring the upper capacitor electrode but also the non-DRAM region (for example, the region between the cell blocks,
By forming the cell plate pattern also in the empty area around the dicing line), the step difference between the DRAM area and the non-DRAM area is eliminated, and DRA is performed even after CMP polishing.
The thickness of the interlayer insulating film on the M region M / C can be made uniform. As a result, it is possible to effectively prevent the exposure of the capacitor and the short circuit of the wiring, which are problems in the surface flattening step, and it is possible to reduce the process margin required for the control adjustment of the CMP polishing.

According to the next invention, it is possible to effectively prevent the exposure of the capacitor and the short circuit of the wiring, which are problems in the surface flattening step of the multilayer wiring type semiconductor device having the DRAM area and the other area. , The process margin required for control adjustment of CMP polishing can be reduced.

[Brief description of drawings]

FIG. 1 is a sectional view showing a structure of a semiconductor device obtained by a manufacturing method according to a first embodiment.

FIG. 2 is a process cross-sectional view showing the method of manufacturing the semiconductor device of the first embodiment.

FIG. 3 is a process cross-sectional view showing the method of manufacturing the semiconductor device of the first embodiment.

FIG. 4 is a plan view showing an example of a cell plate pattern according to the first embodiment.

FIG. 5 is a plan view showing another example of the cell plate pattern according to the first embodiment.

FIG. 6 is a plan view showing a conventional cell plate pattern.

FIG. 7 is a cross-sectional view showing the structure of a semiconductor device obtained by the manufacturing method according to the second embodiment.

FIG. 8 is a step sectional view showing the method of manufacturing the semiconductor device of the second embodiment.

FIG. 9 is a cross-sectional view showing the structure of a semiconductor device obtained by the manufacturing method according to the third embodiment.

FIG. 10 is a process cross-sectional view showing the method of manufacturing the semiconductor device of the third embodiment.

FIG. 11 is a step sectional view showing the method of manufacturing the semiconductor device of the third embodiment.

FIG. 12 is a cross-sectional view showing the structure of a semiconductor device obtained by the manufacturing method according to the fourth embodiment.

FIG. 13 is a process sectional view showing the method for manufacturing the semiconductor device of the fourth embodiment.

FIG. 14 is a process cross-sectional view showing the method of manufacturing the semiconductor device of the fourth embodiment.

FIG. 15 is a cross-sectional view showing a structure of a semiconductor device in the case where a W plug is formed by a method in which the entire surface is etched back by dry etching.

FIG. 16 is a cross-sectional view showing the structure of a semiconductor device when a W plug is formed by the W-CMP method.

[Explanation of symbols]

100 semiconductor substrate, 101 bottom N well region, 1
02 P-type well region, 103 N-type LDD region, 1
04 N + high-concentration source / drain, 105 silicide layer (CoSi ₂ ), 106 isolation oxide film, 107 gate oxide film, 108 polysilicon film (phosphorus-doped polysilicon), 109 silicide layer (WSi ₂ ), 11
0 oxide film, 111 nitride film, 112 oxide film, 113
Nitride film, 114 plug, 115 BPSG, 116
Nitride film, 117 oxide film, 118 oxide film, 119
Oxide film, 120 Interlayer insulating film TEOS, 121 Phosphorus doped polysilicon, 122 Phosphorus doped polysilicon (lower capacitor electrode), 123 Capacitor dielectric film (SiON), 124 Upper capacitor electrode (cell plate), 125 TiN / Ti, 126 W, 127
Barrier metal (TiN / Ti), 128 W, 129
AlCu (first metal wiring), 130 TiN / Ti,
131 insulating film (SiN film), 132 resist, 13
3 Protective insulating film (TEOS film), 134 resist.

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5F033 HH04 HH08 JJ19 QQ48 QQ49                       RR04 RR06 SS04 TT02 VV02                       VV10 VV16                 5F083 AD31 GA27 JA33 JA35 JA36                       JA39 JA40 KA19 KA20 LA03                       LA19 MA03 MA06 MA17 MA20                       PR06 PR40 PR42 PR45 PR46                       PR47 PR52 PR55 PR56 ZA01                       ZA06 ZA12 ZA28

Claims (9)

[Claims] 1. A method of manufacturing a semiconductor device having a DRAM region having a stack capacitor on a semiconductor substrate and a logic region, wherein a lower capacitor electrode layer and a dielectric film of the stack capacitor are provided in an insulating film on the semiconductor substrate. After the DR
A first step of depositing an upper capacitor electrode layer in the AM region and the logic region; and the DRAM by etching the upper capacitor electrode layer such that the upper capacitor electrode layer at least partially remains in the logic region. A second step of forming a cell plate pattern in the region and the logic region; and after depositing an interlayer film on the cell plate pattern, C
A third step of polishing the surface of the interlayer film by using the MP method to planarize the surface, the method of manufacturing a semiconductor device. 2. The semiconductor device according to claim 1, wherein in the second step, a dummy cell plate pattern is formed on the entire surface of the logic region except a portion corresponding to a contact hole portion. Manufacturing method. 3. The semiconductor device according to claim 1, wherein in the second step, dummy cell plate patterns are dispersively formed in portions other than portions corresponding to contact hole portions in the logic region. Device manufacturing method. 4. A method of manufacturing a semiconductor device having a DRAM region having a stack capacitor on a semiconductor substrate and a logic region, wherein a lower capacitor electrode layer and a dielectric film of the stack capacitor are provided in an insulating film on the semiconductor substrate. After the DR
A first step of depositing an upper capacitor electrode layer on the AM region and the logic region, and a second step of depositing an insulating film on the upper capacitor electrode layer
And etching the upper capacitor electrode layer and the insulating film so that the upper capacitor electrode layer and the insulating film deposited in the logic region are removed and a cell plate pattern is formed in the DRAM region. A cell plate pattern on which an insulating film is deposited is used as a DRAM.
A third step of forming in the region, a fourth step of depositing an interlayer film on the insulating film, and then polishing and planarizing the surface of the interlayer film using a CMP method,
A method of manufacturing a semiconductor device, comprising: 5. A method of manufacturing a semiconductor device having a DRAM region having a stack capacitor on a semiconductor substrate and a logic region, wherein a lower capacitor electrode layer and a dielectric film of the stack capacitor are provided in an insulating film on the semiconductor substrate. After the DR
A first step of depositing an upper capacitor electrode layer on the AM region and the logic region, and a second step of depositing an insulating film on the upper capacitor electrode layer
And the step of etching the upper capacitor electrode layer and the insulating film so that the upper capacitor electrode layer at least partially remains in the logic region.
A third step of forming a cell plate pattern in which the insulating film is deposited in the M region and the logic region, and C after depositing an interlayer film on the cell plate pattern.
A fourth step of polishing and planarizing the surface of the interlayer film by using the MP method, and manufacturing the semiconductor device. 6. The method of manufacturing a semiconductor device according to claim 4, wherein the insulating film is made of a material having a CMP polishing rate lower than that of the upper capacitor electrode layer. 7. A method of manufacturing a semiconductor device, wherein a DRAM area having a stack capacitor and a logic area are formed on the same semiconductor substrate, and a capacitor for an electric circuit of the logic area is formed in the logic area. A first step of forming a lower capacitor electrode of the stack capacitor and a lower capacitor electrode of the capacitor for the electric circuit in an insulating film of a DRAM region and an insulating film of the logic region, respectively; and a lower capacitor electrode of the stack capacitor. A second step of forming a dielectric film on the upper and lower capacitor electrodes of the capacitor for the electric circuit, a third step of depositing an upper capacitor electrode layer on the DRAM region and the logic region, and the upper capacitor By etching the electrodes,
A fourth step of forming a cell plate pattern of the stack capacitor and a cell plate pattern of the capacitor for the electric circuit; and after forming an interlayer film on the cell plate pattern, C
A fifth step of polishing the surface of the interlayer film by using the MP method to planarize the surface, the method for manufacturing a semiconductor device. 8. A method of manufacturing a semiconductor device having a DRAM region having a stack capacitor and a non-DRAM region on a semiconductor substrate, wherein a lower capacitor electrode layer and a dielectric film of the stack capacitor are provided in an insulating film on the semiconductor substrate. After setting up the DR
A first step of depositing an upper capacitor electrode layer in the AM region and the non-DRAM region; and etching the upper capacitor electrode layer such that the upper capacitor electrode layer at least partially remains in the non-DRAM region. A second step of forming a cell plate pattern in the DRAM region and the non-DRAM region; and after depositing an interlayer film on the cell plate pattern, C
A third step of polishing the surface of the interlayer film by using the MP method to planarize the surface, the method of manufacturing a semiconductor device. 9. A semiconductor device manufactured by using the manufacturing method according to claim 1. Description: