JP2005252283A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method for stably realizing DRAM of a high degree of integration, without impairing the reliability. <P>SOLUTION: A semiconductor device is provided with a transfer transistor formed on a semiconductor substrate; a first insulating film formed on the substrate, by covering the transfer transistor, a conductive plug with which a first contact hole passing through the first insulating film and reaching one of a pair of impurity diffusion regions is filled; a second insulating film formed on the first insulating film, a bit line connected to the other impurity diffusion region through a second contact hole passing through the first and second insulating films and reaching the other impurity diffusion region; a third insulating film covering an upper face and sides of the bit line; a storage electrode which is matched with the third insulating film covering the sides of the bit line and is electrically connected to the conductive plug via an opening formed in the second insulating film on the conductive plug; a dielectric film formed on a surface of the storage electrode; and a counter electrode formed on a surface of the dielectric film. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device contributing to high integration and high reliability of a DRAM (Dynamic Random Access Memory) and a manufacturing method thereof.

  In order to achieve high integration and low cost of DRAM, it is necessary to proceed with miniaturization of cells which are the basic components. A typical DRAM cell is composed of one MOSFET and one capacitor.

A major problem in promoting cell miniaturization is how to secure a large capacitor capacity with a small cell size.
In recent years, as a method for securing the capacitor capacity, a trench type capacitor in which a groove is formed in a substrate and a capacitor is formed therein, and a stack type capacitor in which a capacitor is three-dimensionally formed on an upper part of a MOSFET have been proposed, and actually It is used in DRAMs. Furthermore, in the stack type capacitor, a plurality of storage electrodes arranged in a direction substantially parallel to the substrate are formed, and a FIN type capacitor using the upper and lower surfaces of each storage electrode as a capacitor, or a cylinder type using a cylindrical storage electrode Improved cell structures such as capacitors have been proposed.

By applying these cell structures and manufacturing processes thereof, it has become possible to realize a DRAM having an integration degree of about 64 MBIT.
However, in the trench type capacitor, the charge accumulation region composed of the depletion layer formed around the trench is greatly expanded by the voltage applied to the capacitor electrode. A phenomenon occurs in which information is lost due to charge leakage. For this reason, it is necessary to increase the width of the separation region between the cells, that is, the width of the region where the field oxide film is disposed, which hinders improvement in the degree of integration.

Therefore, a stacked capacitor is considered promising as a device that contributes to high integration and high reliability of DRAM.
As a miniaturized stack type capacitor, “A 0.29-μm 2 MIM-CROWN Cell and Process Technologies for 1-Gigabit DRAMs” 1994, pages 927 to 929 have been reported.

FIG. 29 shows a cross-sectional view of the memory cell. In the figure, reference numeral 100 is a WSi ₂ / polySi word line, 101 is a first polysilicon plug, 102 is a WSi ₂ / polySi bit line formed on the poly Si plug, 103 is a second polysilicon plug, Reference numeral 104 denotes a W cylinder type storage electrode, a dielectric film of 105Ta ₂ O ₅ , and 106 denotes a counter electrode of CVD-TiN.

By using the cylinder capacitor, a highly integrated DRAM can be provided.
However, when the above-described cylinder type capacitor is employed, the height of the capacitor portion needs to be increased more and more in order to ensure sufficient capacitor capacity with a smaller cell area as well as miniaturization. Therefore, the height difference between the cell portion and the peripheral circuit portion, that is, a step becomes a big problem. For example, when patterning a metal wiring on a cell portion and a peripheral circuit portion, the dimensional accuracy is lowered because the depth of focus of photolithography is insufficient due to a step.

  It is also possible to eliminate the step between the cell portion and the peripheral circuit portion by embedding an insulating film in the peripheral circuit portion, but the contact aspect ratio in the peripheral circuit portion becomes large, and etching control becomes difficult. Another problem will arise.

  Furthermore, as the miniaturization progresses, the wiring interval becomes smaller and the parasitic capacitance of the wiring tends to increase.

  An object of the present invention is to provide a semiconductor device and a method for manufacturing the same which can stably realize a highly integrated DRAM (for example, 256 MDRAM or more) without impairing its reliability.

According to one aspect of the present invention,
In a semiconductor device having a memory cell region and a peripheral circuit region on a semiconductor substrate,
A transfer transistor including a pair of impurity diffusion regions formed in the substrate and a gate electrode formed on the substrate surface;
A first insulating film formed on the substrate so as to cover the transfer transistor;
A first contact hole penetrating the first insulating film and reaching one of the pair of impurity diffusion regions;
A conductive plug filled in the first contact hole;
A second insulating film formed on the first insulating film, covering the conductive plug, and penetrating through the first and second insulating films and reaching the other of the pair of impurity diffusion regions. Two contact holes,
A bit line extending on the second insulating film and connected to the other impurity diffusion region through the second contact hole;
A third insulating film covering the upper and side surfaces of the bit line;
An opening formed in the second insulating film on the conductive plug in alignment with a third insulating film covering a side surface of the bit line;
A storage electrode insulated from the bit line by the second and third insulating films and electrically connected to the conductive plug through the opening;
A dielectric film formed on the surface of the storage electrode;
A counter electrode formed on the surface of the dielectric film;
A semiconductor device is provided.

According to another aspect of the invention,
In a method for manufacturing a semiconductor device having a memory cell region and a peripheral circuit region on a semiconductor substrate,
Forming a transfer transistor including a pair of impurity diffusion regions and a gate electrode on the substrate;
Forming a first insulating film on the substrate so as to cover the transfer transistor;
Forming a first contact hole penetrating the first insulating film and reaching one of the pair of impurity diffusion regions;
Forming a conductive layer in the first contact hole and forming a storage electrode connection plug;
Covering the connection plug and forming a second insulating film on the first insulating film;
Forming a second contact hole penetrating the second and first insulating films and reaching the other of the pair of impurity diffusion regions;
Forming a bit line extending on the second insulating film and connected to the other impurity diffusion region through the second contact hole;
Forming a storage electrode electrically connected to the plug;
Forming a dielectric film on the surface of the storage electrode;
Forming a counter electrode on the surface of the dielectric film;
A method for manufacturing a semiconductor device comprising:
Is provided.

The manufacturing yield can be maintained while reducing the number of processes, which greatly contributes to higher performance and higher density of semiconductor devices.
It has a structure in which it is raised once by one plug made of a conductive layer. That is, since the storage electrode connection plug for raising the word line is formed and the storage electrode is formed between the bit lines by SAC (Self-Aligned Contact), the capacitor height from the substrate surface is reduced. can do.

  Therefore, the height difference between the cell portion and the peripheral circuit portion can be suppressed as compared with the conventional case, and the contact hole can be easily formed in the peripheral circuit portion.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment] A first embodiment of the present invention is shown in FIGS. 1A to 2H.
In the figure, reference numeral 1 is a p-type silicon substrate, 2 is a field SiO ₂ film, 3 is a gate oxide film, 4 is a silicon layer, 5 is a tungsten silicide (WSi) layer, 6 is a SiO ₂ film, 7 is a SiON film, 8 is a gate electrode (first-layer wiring serving as a word line), 9 is an n ⁻ -type impurity diffusion layer, 10 is a sidewall, 11 is a SiO ₂ film, 12 is a Si ₃ N ₄ film, and 13 is a borophosphosilicate glass ( (BPSG) film, 14 is a Si ₃ N ₄ film, 15 is a contact hole, 16 is a conductive plug, 17 is a SiO ₂ film, 18 is a silicon layer, 19 is WSi, 20 is a SiO ₂ film, 21 is a SiON film, 22 Is a bit line (second-layer wiring), 23 is a sidewall, 24 is a SiO ₂ film, 25 is a Si ₃ N ₄ film, 27 is a storage electrode, 29 is a Ta ₂ O ₅ film serving as a capacitor dielectric film, and 30 is TiN as the counter electrode, 3 Reference numeral 1 denotes a BPSG film serving as an interlayer insulating film. N1, P1, and P2 represent an n-well, a p-well, and a p-well, respectively. Hereinafter, illustration of these wells is omitted.

  FIG. 1A is a plan view of a memory cell portion of the semiconductor device of this embodiment. In the figure, word lines 8 are arranged in the vertical direction, bit lines 22 are arranged in the horizontal direction, and capacitors C are arranged thereon.

  FIG. 1B is a cross-sectional view of the memory cell portion corresponding to FIG. 1A, and shows a cross section taken along lines A-A ′ and B-B ′ of FIG. The A-A ′ cross section intersects both the word line and the bit line, the B-B ′ cross section intersects the bit line, and is parallel to the word line. For convenience, the A-A ′ portion and the B-B ′ portion are shown in succession.

  2A to 6 are cross-sectional views of the semiconductor substrate illustrating the method of manufacturing the semiconductor device according to the present embodiment. The left side of the drawing is the memory cell portion MC, and the right side is the peripheral circuit portion PC. The memory cell part MC corresponds to FIG. 1B. An n well N2 is also formed in the peripheral circuit portion PC. Hereinafter, a method of manufacturing the semiconductor device according to the first embodiment will be described with reference to the drawings.

Referring to FIG. 2A, LOCOS separation (selective oxidation) is performed on a p-type silicon substrate 1 using a known technique to form a field SiO ₂ film 2 having a thickness of 250 nm, followed by thermal oxidation to a thickness of 5 A SiO ₂ film 3 to be a gate oxide film of ₁₀ nm is formed.

Next, a 50 nm-thick doped silicon layer 4, a 120 nm-thick WSi layer 5, and an 80 nm-thick SiO ₂ film 6 are formed in sequence on the entire surface by CVD, which contains high-concentration n-type or p-type impurities. . The doped silicon layer 4 can be any of single crystal silicon, polycrystalline silicon, and amorphous silicon.

  Next, a film having an appropriate absorption with respect to the exposure wavelength used in phytolithography, for example, a SiON film 7 having a thickness of about 30 nm, is formed thereon as an antireflection film by plasma CVD.

Further, using a patterned resist mask (not shown), the SiON film 7 and the SiO ₂ film 6 are made of an etchant gas containing, for example, F, and the WSi layer 5 and the polycrystalline silicon layer 4 are made of an etchant gas containing, for example, Cl. Each is selectively removed to form the gate electrode 8. The gate electrode 8 becomes a word line.

Referring to FIG. 2B, using the gate electrode 8 as a mask, P (phosphorus) ions are implanted into the silicon substrate 1 to form an n ⁻ -type impurity diffusion layer 9. The n ⁻ -type impurity diffusion layer 9 becomes the source and drain of the transfer transistor in the cell portion, and becomes the LDD diffusion layer of the n-channel transistor in the peripheral circuit portion. Then, a SiO ₂ film having a thickness of 60nm was formed on the entire surface by low pressure CVD, by anisotropic etching to form a side wall 10 made of SiO _2.

An n ⁺ diffusion layer 55 is formed by implanting arsenic ions into the n channel transistor region of the peripheral circuit portion, and a p ⁺ diffusion layer 57 is formed by implanting boron ions into the p channel transistor region in the n well N2 of the peripheral portion. Form. Hereinafter, the illustration of the diffusion layer is omitted as appropriate.

Referring to FIG. 2C, a 20 nm thick SiO ₂ film 11 and a 50 to 100 nm thick, preferably 80 nm Si ₃ N ₄ film 12 are formed on the entire surface by low pressure CVD.
Next, a BPSG film 13 having a thickness of 300 to 400 nm is formed as a planarizing film on the entire surface, and the BPSG film 13 is reflowed by a heat treatment at about 800 ° C. in a nitrogen atmosphere. In order to completely planarize, it is preferable to perform planarization by polishing the surface by CMP (Chemical Mechanical Polishing).

Instead of the BPSG film, phosphosilicate glass (PSG), spin-on glass (SOG), insulating resin, or the like can be used.
SiO ₂ film 11 serves as a stopper film when removing the Si ₃ N ₄ film 12, the Si ₃ N ₄ film 12 as a stopper film when removing the BPSG film 13. At this time, if the thickness of the Si ₃ N ₄ film 12 is increased, the capacitance between the wirings increases because the dielectric constant of the Si ₃ N ₄ film is higher than that of the SiO ₂ film. If the function as an etching stopper can be ensured, the Si ₃ N ₄ film 12 is preferably thin.

Referring to FIG. 2D, a Si ₃ N ₄ film 14 having a thickness of 50 nm is formed on the entire surface by low pressure CVD, and the Si ₃ N ₄ film 14 is selectively formed by a patterned resist mask (not shown). Remove. Next, the BPSG film 13 is selectively etched to stop when the Si ₃ N ₄ film 12 is partially removed, and then the Si ₃ N ₄ film 12 and the SiO ₂ film 11 are selectively removed. The opening subordinates Si ₃ Si by selective etching of the N ₄ film 12 ₃ N ₄ film 14 holes leaving the SiO ₂ film 11 is formed. Next, the substrate surface is exposed by performing selective etching of SiO ₂ . The sidewall 10 remains almost unetched.

  Consider in more detail the area between adjacent word lines. In the state of FIG. 2C, the upper surface of the word line is covered with the oxide film 6 and the SiON film 7. The side surfaces of the word lines are covered with silicon oxide sidewalls 10. An oxide film 11 and a nitride film 12 are formed on the entire surface of the substrate so as to cover the word line structure. Furthermore, a BPSG film 13 is formed thereon. When a region between adjacent word line structures is viewed from above, the BPSG film 13, the nitride film 12, and the oxide film 11 are present in a convex shape downward in this order. These films can be selectively etched one by one from above. When the BPSG film 13 is anisotropically selectively etched using a photoresist mask, the etching is completed with the nitride film 12 exposed on the bottom surface. Since the nitride film 12 and the oxide film 11 are formed conformally along the side wall of the word line and the substrate surface, the etching is finished following the shape. Next, when the nitride film 12 is selectively etched, the etching is completed with the oxide film 11 exposed. In this state, the region between the word line structures is occupied by the etched openings leaving the oxide film 11. When the thin oxide film 11 is etched, the substrate surface is exposed. The word line structure remains almost complete.

In this way, the contact hole 15 by SAC is formed. Next, a 300 nm thick doped silicon layer is buried in the contact hole 15 by low pressure CVD, and the doped silicon layer on the Si ₃ N ₄ film 14 is removed by CMP to form plugs 16a and 16b. The plug 16b is for bit line contact, and the plug 16a is for storage electrode contact. Hereinafter, the plug 16 refers to both the plugs 16a and 16b.

Note that the plug 16 can be formed using W, TiN, or the like in addition to doped silicon. The W or TiN layer can be deposited by CVD.
Referring to FIG. 2E, a SiO ₂ film 17 having a thickness of 20 to 60 nm is formed on the entire surface by a low pressure CVD method. The oxide film 17 is preferably formed of a dense high temperature oxide film. Such a film has conformal properties. Since the base surface is flattened, a flat film is formed. The SiO ₂ film 17 insulates the plug 16 from the bit line serving as the second layer wiring at a necessary portion. Next, the SiO ₂ film 17 is selectively removed with a patterned resist mask (not shown) to form a bit line contact portion HB. In the figure, the contact portion between the plug 16 and the upper wiring is also opened in the right peripheral circuit. Next, a 40-nm-thick doped silicon layer 18, a 120-nm-thick WSi layer 19, a 120-nm-thick SiO ₂ film 20, and a SiON film 21 serving as an anti-reflection film are sequentially formed on the entire surface by low-pressure CVD. To do. Next, each layer is selectively removed using a patterned resist mask (not shown) to form the bit line 22. Also in the peripheral circuit, wiring connected to the lower plug is formed as necessary.

Further, a SiO ₂ film having a thickness of 60 nm is formed on the entire surface by a low pressure CVD method, and sidewalls 23 made of SiO ₂ are formed by anisotropic etching.
Referring to FIG. 2F, an SiO ₂ film 24 having a thickness of 10 to 30 nm and an Si ₃ N ₄ film 25 having a thickness of 60 to 100 nm are formed on the entire surface by a low pressure CVD method.

  Referring to FIG. 2G, a BPSG film 26 having a thickness of 1000 to 1500 nm is formed as a planarizing film on the entire surface, and the BPSG film 26 is reflowed by a heat treatment at 800 ° C. in a nitrogen atmosphere. Note that in order to achieve complete planarization, it is preferable to perform planarization by polishing the surface by a CMP method.

The SiO ₂ film 24 serves as a stopper film for removing the Si ₃ N ₄ film 25 and is formed to ensure a withstand voltage. Further, the Si ₃ N ₄ film 25 serves as a stopper film when the BPSG film 26 is removed. At this time, if the thickness of the Si ₃ N ₄ film 25 is increased, the capacitance between the wirings increases because the dielectric constant of the Si ₃ N ₄ film is higher than that of the SiO ₂ film. The Si ₃ N ₄ film 25 is preferably thin as long as it can function as an etching stopper.

Next, the BPSG film 26, the Si ₃ N ₄ film 25, and the SiO ₂ film 24 are selectively removed sequentially using a patterned resist mask (not shown) to form a storage electrode forming contact hole HC. . Similar to the formation of the contact hole 15 for the plug 16, self-alignment is performed by the SiO ₂ film 24 and the Si ₃ N ₄ film 25 covering the bit line structure.

  Next, a 60 nm-thick doped silicon layer is formed on the entire surface by low pressure CVD, and a storage electrode layer is formed in the contact hole for forming the storage electrode. After applying the resist 28 so as to fill the remaining holes, the surface is polished by CMP to remove the silicon layer on the BPSG film 26 and form the storage electrode 27.

The resist 28 in the storage electrode 27 is removed. Next, the BPSG film 26 is removed by HF wet etching using the Si ₃ N ₄ film 25 and the silicon storage electrode 27 as an etching stopper, and the outer surface of the storage electrode 27 is also exposed.

Referring to FIG. 2H, the surface of storage electrode 27 is nitrided by a rapid thermal nitridation (RTN) method. Next, a Ta ₂ O ₅ film 29 having a film thickness of 5 to 15 nm is formed by low-pressure CVD, and oxidation heat treatment or oxygen plasma annealing at about 800 to 850 ° C. is performed. In this way, the capacitor dielectric film 29 is formed.

  Further, TiN having a thickness of 50 nm serving as a counter electrode is formed on the entire surface by low pressure CVD, and the counter electrode 30 is formed by etching using a patterned resist mask (not shown) as a mask.

Thereafter, through the steps of forming an interlayer insulating film and opening a contact hole, the structure of FIG. 1B is obtained. Furthermore, a stack type capacitor is manufactured through processes such as wiring layer formation.
In the present embodiment, a structure in which the plug 16 made of a conductive layer is raised once is employed. That is, the connection plug 16 for raising the word line is formed, and the storage electrode 27 is formed between the bit lines by SAC. For this reason, the height of the capacitor can be lowered by the wiring structure of the bit line.

Therefore, the height difference between the cell portion and the peripheral circuit portion can be suppressed, and the contact hole can be easily formed in the peripheral circuit portion.
In this embodiment, as shown in FIG. 1A, the contact hole of the storage electrode is opened in a lattice-shaped region surrounded by the word line and the bit line.

FIG. 3 is a plan view in the process of forming the plugs 16b and 16a in the bit line contact portion and the storage electrode contact portion, and corresponds to FIG. 2D.
For example, when the design rule is 0.2 μm, an insulating film such as a sidewall is formed with a thickness of 0.06 μm on one side in a region surrounded by 0.2 μm, that is, in a 0.2 μm square contact hole. Then, the contact hole becomes 0.08 μm □. The problem at this time is etching, and etching such a fine and deep contact hole is extremely difficult.

  In particular, in a highly integrated device of 256 MDRAM or more (design rule is about 0.22 μm or less), an excimer stepper with a short wavelength must be used to increase the resolution. When considered, it is insufficient, and some super-resolution technique is necessary. Among them, the most prominent is the method called the phase shift method, and the Levenson type phase shift method that inverts the phase of adjacent patterns by 180 ° is the method that is expected to be most effective.

  However, the effect cannot be exhibited unless the pattern conforms to the principle of inverting the phase of the adjacent patterns. In the layout of the plug 16 shown in FIG. 3, two storage electrode contacts 16b are adjacent to one bit line contact 16b in a triangular shape. Three contacts adjacent to each other cannot be out of phase with each other. Therefore, FIG. 3 has a layout in which the Levenson type phase shift is difficult to apply.

  Further, the bit line needs to contact the n-type diffusion layer also in the peripheral circuit portion (especially the sense amplifier). In that case, as shown in FIG. 2D, the plug 16 is also provided in the peripheral circuit portion. That is, the contact in the peripheral circuit portion has a contact structure of bit line / plug / n-type diffusion layer, and has two contact surfaces. Therefore, there is a problem that the value of the contact resistance increases or the contact resistance varies as compared with the case where the bit line directly contacts the diffusion layer.

  Further, in the peripheral circuit portion, the contact portions are scattered as compared with the memory cell portion, and an isolated pattern is formed. At this time, even if the Levenson type phase shift is used for the patterning of the plug 16, this method is not effective for the isolated pattern. However, the exposure condition (numerical aperture, σ) When the value and exposure time are optimized, there is a problem that the contact hole cannot be opened unless the contact hole has a larger diameter.

  [Second Embodiment] In the second embodiment, the plug 16 is formed only in the contact portion of the storage electrode, and the contact hole of the storage electrode portion is formed with the effect of the Levenson type phase shift.

In addition, the bit line is brought into direct contact with the peripheral circuit portion to suppress variations in contact resistance.
Hereinafter, the second embodiment will be specifically described with reference to the drawings. The second embodiment is shown in FIGS. 4A to 9I. In the figure, the same reference numerals denote the same components, and the description of the steps corresponding to those in FIGS. 1A to 3 is omitted.

  4A, 5A,... 8A are plan views of the memory cell in the present embodiment. In the figure, a word line 8 extends in the vertical direction. 4B, 5B,... 8B are plan views of two MOS transistors of the peripheral circuit in the present embodiment.

  9A to 9I are cross-sectional views of the chip for explaining the manufacturing process of the semiconductor device according to the present embodiment, taken along the lines AA ′ and BB ′ of the memory cell portion MC in FIGS. 4A, 5A,. 4B, 5B,... 8B respectively correspond to the CC ′ cross section of the peripheral circuit PC.

  Referring to FIGS. 4A, 4B, and 9A, field oxide film 2 is formed on p-type silicon substrate 1 using the same technique as described in FIG. 2A, and then gate oxide film 3 and gate electrode 8 are formed. Form. The gate electrode becomes a word line. Although the well structure is omitted, it is the same as FIG. 1B.

Referring to FIG. 9B, n ⁻ -type impurity diffusion layer 9 is formed using gate electrode 8 as a mask, using the same technique as described in FIG. 2B. The n ⁻ type impurity diffusion layer 9 serves as the source and drain of the transfer transistor. Next, a SiO ₂ film having a thickness of 60 nm is formed and anisotropically etched to form the sidewall 10 made of SiO ₂ .

Referring to FIG. 9C, the SiO ₂ film 11 and the Si ₃ N ₄ film 12 are formed using the same technique as described in FIG. 2C.
Next, a BPSG film 13 is formed as a planarizing film, and the BPSG film 13 is reflowed by heat treatment. Note that in order to achieve complete planarization, it is preferable to perform planarization by polishing the surface by a CMP method.

5A, 5B, and 9D, a Si ₃ N ₄ film 14 having a thickness of 50 nm is formed on the entire surface by a low pressure CVD method. Next, the Si ₃ N ₄ film 14, the BPSG film 13, the Si ₃ N ₄ film 12, and the SiO ₂ film 11 are selectively used by a resist mask (not shown) patterned by applying a Levenson type phase shift method. By removing, only the contact hole 15 a for contacting the storage electrode with the n ⁻ -type impurity diffusion layer 9 is formed. A contact hole for contacting the bit line with the n ⁻ -type diffusion layer 9 and a contact hole for the peripheral circuit are not formed at this stage.

Further, a doped silicon layer having a thickness of 300 nm is buried in the contact hole 15a by the low pressure CVD method, and the doped silicon layer on the Si ₃ N ₄ film 14 is removed by the CMP method to form the conductive plug 16a.

Referring to FIGS. 6A, 6B, and 9E, a SiO ₂ film 17 having a thickness of 20 to 60 nm is formed on the entire surface by a low pressure CVD method. The SiO ₂ film 17 covers the surface of the plug 16a, and insulates the plug 16a from the bit line serving as the second layer wiring.

Next, the SiO ₂ film 17, Si ₃ N ₄ film 14, BPSG film 13, Si ₃ N ₄ film 12, and SiO ₂ film 11 are selectively removed with a patterned resist mask (not shown) to form a bit. The contact hole 15b of the line 22 and the contact hole 15b of the peripheral circuit are formed simultaneously.

Referring to FIGS. 7A, 7B, and 9E, 40 nm-thick doped silicon layer 18, 120 nm-thickness WSi layer 19, 120 nm-thickness SiO ₂ film 20, and antireflection by plasma CVD method are applied to the entire surface by low-pressure CVD. A SiON film 21 to be a film is sequentially formed. Next, each layer is selectively removed using a patterned resist mask (not shown) to form the bit line 22.

Further, a SiO ₂ film having a thickness of 60 nm is formed on the entire surface of the substrate so as to cover the bit line structure by a low pressure CVD method, and a side wall 23 made of SiO ₂ is formed by anisotropic etching.

Referring to FIG. 9F, a SiO ₂ film 24 and a Si ₃ N ₄ film 25 are sequentially formed on the entire surface of the substrate using the same technique as described in FIG. 2F.
Referring to FIG. 9G, BPSG film 26 is formed using the same technique as described in FIG. 2G, and BPSG film 26 is reflowed by heat treatment. Note that in order to achieve complete planarization, it is preferable to perform planarization by polishing the surface by a CMP method.

Referring to FIGS. 8A, 8B, and 9G, the BPSG film 26, the Si ₃ N ₄ film 25, and the SiO ₂ film 24 are selectively removed sequentially to form a contact hole for forming a storage electrode.
Further, after forming a doped silicon layer and applying a resist 28 so as to fill the contact hole for forming the storage electrode, the surface is polished by a CMP method to remove the silicon layer on the BPSG film 26 and store it. An electrode 27 is formed.

Referring to FIG. 9H, the resist 28 in the storage electrode is removed using a technique similar to that described in FIG. 2H. Next, the BPSG film 26 is removed by wet etching using the Si ₃ N ₄ film 25 as an etching stopper, and the outer surface of the storage electrode is also exposed. The surface of the storage electrode 27 is nitrided by the RTN method. Next, a Ta ₂ O ₅ film 29 is formed and oxidation heat treatment or oxygen plasma annealing is performed.

  Further, a counter electrode 30 is formed by forming and patterning a TiN film to be a counter electrode. Further, the interlayer insulating film 31 is formed of BPSG or the like, and the surface is planarized by reflow or CMP. A contact hole CH of the peripheral circuit is opened using the resist pattern.

Referring to FIG. 9I, a DRAM device having a stack type capacitor is manufactured through processes such as wiring formation including barrier metal layer 32, main conductive layer 33, and the like.
In some cases, a plug for raising the bit line 22 may be further formed after the bit line 22 is formed. In this case, the height of the cell portion becomes higher than that of the first embodiment. However, since the contact hole 15a of the storage electrode connecting plug 16 is formed by using the Levenson type phase shift method, the contact is easily made. Holes can be formed.

  According to the present embodiment, the contact hole 15b in the peripheral circuit portion is opened at the same time as the contact hole 15b for the bit line separately from the contact hole 15a for the storage electrode, so that the Levenson type phase shift method is not required. Since the contact diameter of the peripheral circuit portion can be reduced, the layout area can be reduced.

Further, since the contact hole 15b with the n-type diffusion layer of the peripheral circuit portion is directly opened on the substrate, the contact resistance of the peripheral circuit portion is stabilized and variation can be suppressed.
[Third Embodiment] Next, a third embodiment will be described with reference to the drawings.

  In the second embodiment, since the silicon layer and WSi are used as the bit line material, the contact in the peripheral circuit portion is only in contact with the n-type diffusion layer when n-type doped silicon is used. I could not do it.

  Therefore, in the peripheral circuit portion, the only way to make contact with the p-type diffusion layer is to make contact using the upper metal wiring. In addition, since a deep contact hole from the upper layer wiring to the substrate surface has to be formed, there is a problem that the layout area is increased in order to provide an alignment margin. Furthermore, there is a problem that the controllability of etching is difficult in forming such a deep contact hole.

  According to this embodiment, in the bit line structure formed under the capacitor, the material is a metal wiring. Therefore, the n-type diffusion layer and the p-type diffusion layer in the peripheral circuit portion can be contacted through the shallow contact hole, and the layout area can be reduced.

  FIG. 10 is a cross-sectional view of the semiconductor device according to the third embodiment, and corresponds to the cross-sectional view of FIG. 9I described in the second embodiment. In the figure, 9a indicates an n-type diffusion layer, and 9b indicates a p-type diffusion layer. A bit line 22 as a second conductive layer is formed by two layers of metal wirings 18a and 19a. Other reference numerals are the same as those described in the second embodiment. A part of the well structure is not shown.

  According to the present embodiment, when the contact hole 15b of the bit line is formed, the contact hole 15b can be simultaneously formed in the n-channel transistor region and the p-channel transistor region of the peripheral circuit portion.

  Therefore, as shown in FIG. 9I, it is not necessary to directly contact the substrate using the upper metal wiring, so that the layout area of the peripheral circuit portion can be reduced.

[Fourth Embodiment] The fourth embodiment of the present invention will be described in detail with reference to FIGS.
This embodiment will be described below with a focus on a method for contacting the first conductive layer and the second conductive layer in the peripheral circuit portion.

  FIG. 11 is a cross-sectional view of the semiconductor device corresponding to FIG. 9I in the second embodiment, in which the first conductive layers 4 and 5 and the second conductive layers 18 and 19 contact each other at the right end of the peripheral circuit portion. It shows the case.

  FIG. 12 shows a cross-sectional view of the semiconductor device according to the fourth embodiment, which is an improvement of the semiconductor device shown in FIG. Further, the cell portion corresponds to the cell portion of FIG. 9I, and the peripheral circuit portion is similar to the peripheral circuit portion of FIG. 9I. In the drawings, the same reference numerals denote the same items.

In the present embodiment, after an Si ₃ N ₄ film 12 used in the SAC, the removal of the Si ₃ N ₄ film 12 in the peripheral circuit region. That is, for example, in the steps of FIGS. 2C and 9C, the Si ₃ N ₄ film 12 is selectively removed in a region including a portion where contact between the first conductive layer and the second conductive layer is desired. To do. In the cell portion, there is one Si ₃ N ₄ film 12 between the n-type diffusion layer 9 and the interlayer insulating film 13, and in the peripheral circuit portion, the first conductive layers 4 and 5 and the interlayer insulating film 13, there is a single layer of SiON film 7. The SiON film 7 and the SiN film 12 can be selectively etched by the same etching.

  Accordingly, when the contact hole between the bit line and the substrate is opened, it is possible to simultaneously form a contact between the first conductive layer and the second conductive layer. Compared with the method of FIG. 11 in which a fine contact hole to the first conductive layer must be opened separately from the contact hole with the substrate, the SiON film in the region where the contact hole is to be opened is removed in FIG. Therefore, a separate fine pattern is not required, and the yield and reliability can be improved.

[Fifth Embodiment] A fifth embodiment of the present invention will be described with reference to FIG.
This embodiment is a combination of the third embodiment and the fourth embodiment, and is a method for contacting the first conductive layer and the second conductive layer, and the second conductive layer. The case where a metal is applied to the layer is shown.

FIG. 13 is a cross-sectional view of the semiconductor device according to the present embodiment, which is an improvement over FIG. 12 described in the fourth embodiment. In the drawings, the same reference numerals denote the same items.
According to the present embodiment, when forming the contact of the bit line, the contact hole can be formed simultaneously in the n-channel transistor region and the p-channel transistor region of the peripheral circuit portion, and the substrate is directly contacted by the upper wiring. Therefore, the layout area of the peripheral circuit portion can be reduced.

Further, after an Si ₃ N ₄ film 12 to be used in the SAC, since the removal of the Si ₃ N ₄ film 12 in the peripheral circuit region, when the contact hole for the bit line and the substrate, at the same time a first layer A contact between the second conductive layer and the second conductive layer can be formed, and the number of steps can be reduced.

[Sixth Embodiment] A sixth embodiment of the present invention will be described with reference to FIG.
The present embodiment relates to a method for forming a contact hole in a peripheral circuit portion. When the contact hole is formed in the impurity diffusion layer or the wiring layer by etching the interlayer insulation film, if the interlayer insulation film is composed of a plurality of oxide films or a plurality of nitride films, Etching becomes complicated.

Therefore, the present embodiment is characterized in that the process of forming contact holes in the peripheral circuit portion is stably performed.
FIG. 14 is a cross-sectional view of the semiconductor device showing the present embodiment, which is an improvement of the semiconductor device described in the second embodiment. In the drawings, the same reference numerals denote the same items.

  Referring to FIG. 14, the manufacturing process of the semiconductor device in the present embodiment is substantially the same as the manufacturing process described with reference to FIGS. 9A to 9I in the second embodiment, and different points will be described below.

First, after patterning the gate electrode serving as the first layer wiring, the SiON film 7 on the gate electrode 8 is removed by, for example, phosphoric acid boil in the peripheral circuit portion. Even after patterning the bit line to be the second layer wiring, the SiON film 21 on the bit line is removed in the peripheral circuit portion. Further, following the patterning of the counter electrode 30, the SAC Si ₃ N ₄ film 25 is removed from the peripheral circuit portion. The SiON films 7 and 21 are used as antireflection films when patterning the wiring. If the wiring is patterned without using the SiON films 7 and 21, it is not necessary to remove the SiON films 7 and 21.

  According to this embodiment, there is no SiON film on the first layer wiring and bit line in the peripheral circuit portion, and a single layer SiN film is formed. The nitride film used for the SAC necessary for forming the memory cell portion can be removed, and at the same time, the SiN film in the peripheral circuit portion can be removed, and the underlying oxide film can be removed at the same time. In particular, since the peripheral circuit portion is selectively removed without increasing the number of steps, it is easy to form contact holes in the peripheral circuit portion.

[Seventh Embodiment] A seventh embodiment of the present invention will be described with reference to FIG.
In the sixth embodiment, the SiON film 7 on the first layer wiring (gate electrode) 7 and the SiON film 21 on the second layer wiring (bit line) are respectively removed, and the Si ₃ N ₄ film 25 under the counter electrode is removed. Is removed using the counter electrode as a mask to facilitate the formation of the contact hole in the peripheral circuit portion. In this embodiment, a method for further facilitating the formation of the contact hole is provided.

FIG. 15 is a cross-sectional view of the semiconductor device according to the present embodiment, which is an improvement of the semiconductor device described in the sixth embodiment. In the drawings, the same reference numerals denote the same items.
Referring to FIG. 15, the manufacturing process of the semiconductor device according to the present embodiment is substantially the same as the manufacturing process described with reference to FIGS. 9A to 9I in the second embodiment, as in the sixth embodiment. The point will be described.

First, after patterning the gate electrode to be the first layer wiring, the SiON film 7 on the gate electrode 8 in the peripheral circuit portion is removed by, for example, phosphoric acid boil.
Then, after an Si ₃ N ₄ film 12 used in the SAC, selectively remove the Si ₃ N ₄ film 12 in the peripheral circuit region. Next, the SiON film 21 on the bit line is also removed after patterning the bit line to be the second layer wiring. Further, following the patterning of the counter electrode 30, the SAC Si ₃ N ₄ film 25 in the peripheral circuit portion, the SiO ₂ film 24 as the interlayer insulating film, and the SAC Si ₃ N ₄ film 14 are sequentially removed.

  The SiON films 7 and 21 are used as antireflection films when patterning the wiring. If the wiring is patterned without using the SiON films 7 and 21, it is not necessary to remove the SiON films 7 and 21.

According to the present embodiment, since all the SiON films 7 and 21 and the Si ₃ N ₄ films 12, 25 and 14 in the peripheral circuit portion are removed, the formation of contact holes in the peripheral circuit portion is further facilitated.

[Eighth Embodiment] An eighth embodiment of the present invention is shown in FIGS.
The present embodiment provides a method of contacting the first conductive layer and the second conductive layer in the peripheral circuit portion by using means different from the fourth embodiment.

16A to 16I are cross-sectional views of the chip showing the manufacturing process of the semiconductor device according to the present embodiment, in which the same reference numerals denote the same parts.
Referring to FIG. 16A, LOCOS separation (selective oxidation) is performed on a p-type silicon substrate 1 using a known technique to form a field SiO ₂ film 2 having a thickness of 250 nm, and then a thickness of 5 nm is obtained by thermal oxidation. A SiO ₂ film 3 to be a gate oxide film of ₁₀ nm is formed. Next, a 50 nm thick silicon layer 4, a 120 nm thick WSi layer 5, a 20 nm thick SiO ₂ film 6, and an 80 nm thick Si ₃ N ₄ film 7 containing P (phosphorus) at a high concentration by low pressure CVD. 'Is formed sequentially.

Further, the Si ₃ N ₄ film 7 ′ is selectively applied to a region including a portion where contact between the first conductive layer and the second conductive layer is desired by a patterned resist mask (not shown). Remove.

Referring to FIG. 16B, Si ₃ N ₄ film 7 ′, SiO ₂ film 6, WSi layer 5, and silicon layer 4 are selectively removed with a patterned resist mask (not shown) to obtain a gate electrode. 8 (first layer wiring) is formed. The gate electrode becomes a word line.

Referring to FIG. 16C, P (phosphorus) ions are implanted into silicon substrate 1 using gate electrode 8 as a mask to form n ⁻ -type impurity diffusion layer 9. The n ⁻ -type impurity diffusion layer 9 serves as the source and drain of the transfer transistor in the cell portion, and serves as a low concentration diffusion layer for LDD of the n-channel transistor in the peripheral circuit portion. Then, a reduced pressure CVD method by to form a Si ₃ N ₄ film having a thickness of 60nm on the entire surface by anisotropic etching to form sidewall 10 'made of Si ₃ N _4.

Referring to FIG. 16D, arsenic ions are implanted into the n-channel transistor region of the peripheral circuit portion to form an n ⁺ -type diffusion layer. A p ⁺ diffusion layer is formed by implanting boron ions into the peripheral p-channel transistor region.

Next, a 20 nm thick SiO ₂ film 11 and a 300 to 400 nm thick BPSG film 13 are formed on the entire surface by low pressure CVD, and the BPSG film 13 is reflowed by a heat treatment at about 800 ° C. in a nitrogen atmosphere. Note that in order to achieve complete planarization, it is preferable to perform planarization by polishing the surface by a CMP method.

Then, select the entire surface by low pressure CVD method, an Si ₃ N ₄ film 14 having a thickness of 50 nm, a patterned resist mask (not shown) the Si ₃ N ₄ film 14 in the region where the storage electrode is a contact To remove. Next, the BPSG film 13 is removed by self-alignment using the nitride films 7 ′ and 10 ′ to form a contact hole 15a by SAC.

Further, a doped silicon layer having a thickness of 300 nm is buried in the contact hole 15a by the low pressure CVD method, and the doped silicon layer on the Si ₃ N ₄ film 14 is removed by the CMP method to form the plug 16.

Referring to FIG. 16E, a SiO ₂ film 17 having a thickness of 20 to 60 nm is formed on the entire surface covering the plug 16 by a low pressure CVD method. The SiO ₂ film 17 insulates the plug 16 from the bit line that becomes the second layer wiring. Next, the SiO ₂ film 17, the Si ₃ N ₄ film 14, the BPSG film 13, and the SiO ₂ film 11 are selectively removed by a patterned resist mask (not shown) to form the contact hole 15b of the bit line 22 and The contact hole 15b of the peripheral circuit is formed at the same time. Similar to the formation of the contact hole 15a, the contact hole 15b is formed by self-alignment using the nitride films 7 ′ and 10 ′.

Referring to FIG. 16F, a 40 nm-thick doped silicon layer 18 having a high concentration of P, a 120 nm-thick WSi layer 19, a 20 nm-thick SiO ₂ film 20, and a thickness of 120 nm are formed on the entire surface by low-pressure CVD. The Si ₃ N ₄ film 21 ′ is sequentially formed. Next, each layer is selectively removed using a patterned resist mask (not shown) to form the bit line 22.

Furthermore, low pressure CVD by to form a Si ₃ N ₄ film having a thickness of 60nm is formed on the entire surface of the side wall 23 of Si ₃ N ₄ 'by anisotropic etching.
Referring to FIG. 16G, a SiO ₂ film 24 having a thickness of 10 to 30 nm is formed on the entire surface by a low pressure CVD method. Next, a BPSG film 26 having a thickness of 1000 to 1500 nm is formed on the entire surface as a planarizing film, and the BPSG film 26 is reflowed by heat treatment at 850 ° C. in a nitrogen atmosphere. Note that in order to achieve complete planarization, it is preferable to perform planarization by polishing the surface by a CMP method.

Next, by using a patterned resist mask (not shown), the BPSG film 26 and the SiO ₂ film 24 are selectively removed sequentially in a self-alignment manner using the nitride films 21 and 23 ′, thereby forming a storage electrode forming contact. Hall HC is formed.

  Next, a doped silicon layer having a thickness of 60 nm containing phosphorus at a high concentration is formed by low pressure CVD, and a resist 28 is buried in a contact hole for forming a storage electrode, and then the surface is polished by CMP to BPSG The silicon layer on the film 26 is removed, and the storage electrode 27 is formed.

Referring to FIG. 16H, the resist 28 in the storage electrode is removed. Next, the BPSG film 26 is removed by HF wet etching to expose the outer surface of the storage electrode. In the figure, a case where a part of the BPSG film 26 is left is shown. Next, the surface of the storage electrode 27 is nitrided by the RTN method. Next, a Ta ₂ O ₅ film 29 having a film thickness of 5 to 15 nm is formed by low-pressure CVD, and oxidation heat treatment or oxygen plasma annealing at about 800 to 850 ° C. is performed.

  Further, TiN having a thickness of 50 nm serving as a counter electrode is formed on the entire surface by low pressure CVD, and the counter electrode 30 is formed by etching using a patterned resist mask (not shown) as a mask.

Referring to FIG. 16I, a stack type capacitor is manufactured through steps such as formation of interlayer insulating film 31 and wiring layers 32 and 33.
In the present embodiment, in the step of FIG. 16A, 'after forming, Si ₃ N ₄ film 7 of the peripheral circuit region' Si ₃ N ₄ film 7 used in the SAC by the selective removal of, in the step of FIG. 16E When the contact hole between the bit line and the substrate is opened, it is possible to simultaneously form a contact between the first conductive layer and the second conductive layer, thereby reducing the number of steps. .

Further, according to the present embodiment, the Si ₃ N ₄ film is formed so as to surround the gate electrode (first layer wiring) and the bit line (second layer wiring), and the self-alignment contact is performed. Since there is no extra Si ₃ N ₄ film in the peripheral circuit portion, it is easy to form contact holes in the peripheral circuit portion.

[Ninth Embodiment] In the fourth to eighth embodiments, the contact hole can be easily formed in the peripheral circuit portion by selectively removing the Si ₃ N ₄ film in the peripheral circuit portion. Explained.

  The present embodiment provides a semiconductor device that can reduce the number of steps in a memory cell portion and can easily form a contact hole in a peripheral circuit portion, and a method for manufacturing the same.

  The ninth embodiment will be specifically described below with reference to the drawings. This embodiment is shown in FIGS. 17A, 17B, 18A-18L. In the drawings, the same reference numerals indicate the same items.

  FIG. 17A is a plan view of the memory cell portion in the present embodiment. FIG. 17B is a cross-sectional view of the memory cell portion and the peripheral circuit portion in this embodiment, and the memory cell portion corresponds to a cross section taken along lines X-X ′ and Y-Y ′ in FIG. 17A, respectively.

  18A to 18L are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the present embodiment. This embodiment is a modification of the second embodiment, and in the figure, the same reference numerals as those of the second embodiment denote the same components.

Referring to FIG. 18A, LOCOS isolation (selective oxidation) is performed on a p-type silicon substrate 1 using a known technique to form a field SiO ₂ film 2 having a thickness of 250 nm. Next, a well diffusion layer, an element isolation diffusion layer, and a channel diffusion layer are formed by ion implantation (not shown). Next, a SiO ₂ film 3 to be a gate oxide film having a thickness of 5 to 10 nm is formed by thermal oxidation.

Referring to FIG. 18B, a 50 nm thick doped silicon layer 4, a 120 nm thick WSi layer 5, and an 80 nm thick SiO ₂ film 6 containing phosphorus at a high concentration are sequentially formed on the entire surface by CVD. Next, a film having an appropriate absorption with respect to the exposure wavelength used in phytolithography, for example, a SiON film 7 having a thickness of about 30 nm, is formed thereon as an antireflection film by plasma CVD.

Further, by using a patterned resist mask (not shown), the SiON film 7 and the SiO ₂ film 6 are selectively removed by, for example, an F system, and the WSi layer 5 and the silicon layer 4 by, for example, a Cl system, respectively. A gate electrode 8 is formed. The gate electrode 8 becomes a word line. Hereinafter, the SiON film 7 is not shown for simplification.

Referring to FIG. 18C, P ions are implanted into substrate 1 using gate electrode 8 as a mask to form an n ⁻ -type impurity diffusion layer (not shown). The n ⁻ -type impurity diffusion layer serves as the source and drain of the transfer transistor in the cell portion, and serves as a low concentration diffusion layer for LDD of the n-channel transistor in the peripheral circuit portion (not shown). Next, a SiO ₂ film having a thickness of 70 nm is formed on the entire surface by the low pressure CVD method, and the sidewall 10 is formed by anisotropic etching.

Next, arsenic ions are implanted into the n-channel transistor region of the peripheral circuit portion to form an n ⁺ diffusion layer. Further, boron ions are implanted into the peripheral p channel transistor region to form ap ⁺ diffusion layer (not shown).

Next, a Si ₃ N ₄ film 12 having a thickness of 50 to 100 nm, preferably 60 to 80 nm is formed on the entire surface by low pressure CVD. The Si ₃ N ₄ film 12 serves as a stopper film when forming contact holes.

  Next, a BPSG film 13 having a thickness of 300 to 400 nm is formed on the entire surface as a planarizing film, and the BPSG film 13 is reflowed by heat treatment. Thereafter, the BPSG film 13 is polished by CMP to have a thickness of about 100 nm above the gate electrode 8, and the surface is flattened.

Referring to FIG. 18D, the BPSG film 13 is selectively etched by a patterned resist mask (not shown) and stopped when the Si ₃ N ₄ film 12 is partially removed, and subsequently the Si ₃ N ₄ film. 12 is selectively removed to form a contact hole 15a by SAC using the oxide films 10 and 6 as etching stoppers. Note that the resist mask in this case is preferably formed by a phase shift method. In order to reduce the contact resistance, phosphorus may be ion-implanted into the substrate 1 after the contact hole 15a is formed.

  Next, a 200-300 nm thick doped silicon layer containing phosphorus at a high concentration is buried in the contact hole 15a by low pressure CVD, and the doped silicon layer on the BPSG film 13 is removed by CMP to remove the plug 16 Form.

Referring to FIG. 18E, a SiO ₂ film 17 having a thickness of 20 to 50 nm is formed on the entire surface covering the plug 16 by low pressure CVD. The SiO ₂ film 17 insulates the plug 16 from the bit line 22 that becomes the second layer wiring. Next, the SiO ₂ film 17 and the BPSG film 13 are selectively etched by a patterned resist mask (not shown) and stopped when a part of the Si ₃ N ₄ film 12 is removed, and then the Si ₃ N ₄ film. 12 is selectively removed to form a contact hole 15b by SAC using an oxide film as an etching stopper.

Referring to FIG. 18F, a 40 nm thick doped silicon layer 18, a 120 nm thick WSi layer 19 and a 160 nm thick SiO ₂ film 20 containing phosphorus at a high concentration are sequentially formed by low pressure CVD. Next, an SiON film 21 having a thickness of about 30 nm, which becomes an antireflection film, is sequentially formed thereon by plasma CVD.

  Further, each layer is selectively removed by a patterned resist mask (not shown) to form the bit line 22. If necessary, contact annealing may be performed by the RTA method. Thereafter, the SiON film 21 is not shown for simplification.

Referring to FIG. 18G, an SiO ₂ film having a thickness of about 60 to 70 nm is formed by a low pressure CVD method, and sidewalls 23 made of SiO ₂ are formed by anisotropic etching.
Here, by the amount of etching in the thickness portion of the SiO ₂ film 17 and the SiO ₂ film for the sidewall, leaving the SiO ₂ film 17 under the bit line 22 and side wall 23 only. As a result, the surface of the plug 16 filled in the contact hole 15a is exposed.

Referring to FIG. 18H, a Si ₃ N ₄ film 25 having a thickness of 50 to 100 nm is formed as a SAC etching stopper film by low pressure CVD. Next, a BPSG film 26 having a thickness of 1000 to 1200 nm is formed on the entire surface as a planarizing film, the BPSG film 26 is reflowed by heat treatment, and then the surface is polished and flattened to a thickness of about 800 nm by CMP. To do.

Referring to FIG. 18I, with a patterned resist mask (not shown), the BPSG film 26 is selectively etched to stop when the Si ₃ N ₄ film 25 is partially removed, and then the Si ₃ N ₄ film. 25 is selectively etched to form a contact hole HC for storage electrode formation by SAC using an oxide film and a silicon film as an etching stopper.

  Referring to FIG. 18J, a 60 nm-thick doped silicon layer containing phosphorus at a high concentration is formed by low pressure CVD, and the silicon layer on BPSG film 26 is removed by CMP to form a storage electrode. The portion in contact with the inner wall surface of the contact hole is left as the storage electrode 27.

  In this case, if necessary, the resist is embedded in the recesses of the silicon layer before the CMP, and the resist is removed after the CMP so that the abrasive particles in the CMP enter the recesses and are difficult to remove. It can also be prevented.

Referring to FIG. 18K, BPSG film 26 is removed by HF wet etching using Si ₃ N ₄ film 25 as an etching stopper film, and the outer surface of the storage electrode is also exposed. Next, a Ta ₂ O ₅ film 29 having a film thickness of 5 to 15 nm is formed by CVD, and oxidation heat treatment or oxygen plasma annealing is performed to densify the Ta ₂ O ₅ film 29.

  Further, a TiN film having a thickness of 100 nm to be a counter electrode is formed by a low pressure CVD method, and the counter electrode 30 is formed by performing dry etching with a Cl-based gas using a patterned resist mask (not shown) as a mask. Form.

At this time, it is also preferable to etch the Ta ₂ O ₅ film following the etching of the TiN film. It is also preferable to nitride the surface of the storage electrode 27 by RTN before forming the Ta ₂ O ₅ film.

Referring to FIG. 18L, a 1000 nm thick SiO ₂ film 31 to be an interlayer insulating film is formed by HDP (High Density Plasma) CVD method, and the surface is polished and planarized by CMP method. Next, contact holes are formed in the peripheral circuit portion.

  Next, a Ti film having a thickness of 60 nm is formed as a contact metal by a collimator sputtering method, and a TiN film having a thickness of 30 nm is formed by a CVD method to form a barrier medal layer 32. A W film 33 having a thickness of 150 nm is formed thereon.

Thereafter, a semiconductor device having a stack type capacitor is manufactured through steps such as an interlayer insulating film and a wiring layer.
In the present embodiment, compared to the first to eighth embodiments, the Si ₃ N ₄ film 14 serving as a stopper film when forming the contact hole of the storage electrode is not formed, and therefore the contact hole formed in the peripheral circuit portion. Can be easily formed.

Furthermore, in the etching process for forming the sidewalls 23 on the bit lines 22, the SiO ₂ film 17 that insulates the bit lines 22 and the plugs 16 is subsequently etched away, so that the etching process can be reduced.

  In the ninth embodiment, it has been explained that the manufacturing process can be mainly reduced. However, in the ninth embodiment, when the bit line contact hole 15b and the bit line 22 are displaced, the bit line contact portion is exposed in the storage electrode contact, and the storage electrode comes into contact with the bit line. The problem arises.

  FIG. 19 shows a case where the above-mentioned positional deviation occurs, and FIG. 20 shows a case where the bit line 22 and the storage electrode come into contact when the storage electrode 27 is formed in the subsequent process. 19 and 20 correspond to the state of FIG. 18F of the ninth embodiment and the state of removing the BPSG film after FIG. 18J.

  In the ninth embodiment, when the hole diameter of the bit line contact is considerably larger than the width of the bit line 22, or when the displacement occurs even if the size is the same, the pattern of the bit line contact hole 15b is The shape protrudes from the pattern of the line 22. In particular, it has been found that the following problem occurs when the side wall 23 formed on the bit line 22 exceeds the thickness of the side wall 23.

  FIG. 19 is a view when the amount of deviation is about 1.5 times the thickness of the sidewall 23, and shows a state immediately after the bit line 22 is formed. If the etching amount of the bit line 22 is equivalent to the thickness of the formed WSi 19 / silicon layer 18, the upper surface of the conductor film can be seen at the portion where the contact hole 15b of the bit line protrudes as shown in the figure. .

  FIG. 20 shows a state in which the storage electrode 27 is formed through the steps described in the ninth embodiment. In this figure, the storage electrode contact hole pattern for shaping the storage electrode is also similarly shifted. The upper surface of the bit line 22 conductor is at the portion where the contact hole of the storage electrode protrudes, and the amount of protrusion is larger than the thickness of the sidewall 23, so that the storage electrode is not covered with the sidewall 23. For this reason, the bit line 22 and the storage electrode 27 are short-circuited.

With such a design and misalignment, the yield decreases, but it is disadvantageous to design with a misalignment margin in order to reduce the cell area and improve the degree of integration.
[Tenth Embodiment] This embodiment provides a semiconductor device in which the bit line 22 and the storage electrode 27 do not come into contact with each other even if the above-mentioned positional deviation occurs, and a method for manufacturing the same.

  Hereinafter, the tenth embodiment will be specifically described with reference to the drawings. This embodiment is shown in FIGS. FIG. 21A is a continuation of FIG. 18E described in the ninth embodiment. In the drawings, the same reference numerals indicate the same items.

Referring to FIG. 21A, the process up to opening the bit line contact hole 15b is the same as in the ninth embodiment.
Next, a 40 nm thick doped silicon layer 18 containing a high concentration of phosphorus, a 120 nm thick WSi layer 19 and a 160 nm thick SiO ₂ film 20 are sequentially formed by CVD. Thereafter, a SiON film 21 having a thickness of about 30 nm is formed as an antireflection film by plasma CVD.

Further, a mask (not shown) is formed by lithography using a normal or phase shift reticle, and the SiON film 21 and the SiO ₂ film 20 are F-based, and the WSi layer 19 and the silicon layer 18 are Cl-based dry etched. Thus, the bit line 22 is formed. If necessary, contact annealing may be performed at this stage by the RTA method. Hereinafter, illustration of the SiON film 21 is omitted for simplification.

Referring to FIG. 21B, a SiO ₂ film having a thickness of 70 nm is formed by CVD, and sidewalls 23 are formed by anisotropic etching. Here, by the amount of etching in the thickness portion of the SiO ₂ film 17 and the SiO ₂ film for the sidewall, leaving the SiO ₂ film 17 under the bit line 22 and side wall 23 only. As a result, the surface of the plug 16 filled in the contact hole 15a is exposed.

  The feature of this embodiment is that the bit line conductor film in the bit line contact hole 15b is recessed by performing over-etching in the etching for forming the bit line 22.

The amount to be recessed by this etching is determined as follows. Let d be the amount that the bit line contact hole 15b protrudes from the bit line 22 pattern due to misalignment or the like. The thickness of the SiO ₂ film for forming the sidewall 23 in the next step is t. In order to simplify the explanation, it is assumed that this SiO ₂ film has 100% coverage, that is, is completely conformal.

  In the case of d ≦ t, the amount to be recessed may be an amount necessary for ensuring insulation. For example, the same value as t can be selected. As a result, the distance between the conductor constituting the bit line and the conductor constituting the storage electrode is t or more in any portion. Note that the amount necessary for securing insulation is w, and if d <tw, it is not necessary to be recessed.

Referring to FIG. 21B, when 2t>d> t, the sidewall 23 formed from the right side wall of the bit line contact hole 15b is rounded so that it is recessed in the insulator portion integrated with the sidewall 23. Produce. This amount, t-- a ^{(t 2 (d-t)} 2) 1/2. The conductor constituting the bit line may be recessed by an amount obtained by adding an amount necessary for ensuring insulation.

  When d ≧ 2t, a short circuit cannot be avoided even with this embodiment. However, this means that when t = 0.07 μm as in the present embodiment, d is 0.14 μm or more. If the positional deviation is 0.1 μm at the maximum, the diameter of the contact hole 15b of the bit line is set to a bit. This corresponds to the case of (0.14-0.1) × 2 = 0.08 μm larger than the line width. It is considered that there is no merit in designing devices with such a large difference in the generation of devices of about 0.25 μm or less.

  When the coverage is not 100%, d, t, and the amount of dent are set in consideration of the reduction of the film thickness in the lateral direction and the formation of voids. In addition, if the inside of the bit line contact hole 15b is forward tapered by over-etching the bit line, the bit line can be embedded well even when the coverage is poor. It is also effective to form a forward taper on top of the bit line contact hole 15b.

Further, the amount of the bit line conductor film that is over-etched and recessed in the bit line contact hole 15b will be described in detail using specific numerical values.
An example of a 0.2 μm device will be described. The bit lines and the distance between them are 0.2 μm, but the diameter of the bit line contact hole 15b is preferably about 0.24 μm in view of photolithography. A typical value of the maximum position deviation is 0.1 μm. The numerical value of the positional deviation includes variations in the size of the bit line contact hole 15b and the size of the bit line 22. In other words, it is assumed that the bit line contact hole 15b is large and the bit line 22 is made thin (half each because 10% is one side).

  Then, d = (0.24-0.2) /2+0.1=0.12 μm. The thickness of the sidewall insulating film is close to 70 nm. This is because the distance between the bit lines 22 is 0.2 μm, and if 0.07 μm sidewalls are formed on both sides, the contact width is already 0.06 μm.

  In actual manufacturing, not only the positional deviation but also the film thickness and the etching amount vary. Typically, a width of 7% for film formation and 7% for etching is assumed. Therefore, to consider the worst case, it is appropriate to set t = 0.065 μm.

Then, Δ = t− (t ² − (dt) ² ) ^1/2 = 0.03 μm. Here, considering the variation in the thickness of the sidewall insulating film and the etching amount, it is necessary to assume that an excess of 0.01 μm is removed. Since it is considered preferable to leave about 0.02 μm at a minimum to ensure the withstand voltage, it is preferable to have a total of 0.06 μm or more recessed.

  On the other hand, in etching such as bit line formation, over-etching has conventionally been performed in order to absorb variations in film thickness and etching amount. The minimum amount is about 20%. Note that no further over-etching is required in the prior art because the structure is planarized. In the film thickness of the present embodiment, since the silicon layer is 40 nm and the WSi film is 120 nm, 20% thereof is 0.032 μm. Therefore, in the conventional bit line formation, the recess in the bit line contact hole 15b portion is typically about 0.032 μm.

  On the other hand, in this embodiment, since the recess of 0.06 μm or more is made, it is possible to prevent a short circuit between the bit line conductor and the storage electrode conductor at the bit line contact portion.

  In the prior art, it is typical to design a pattern so that the bit line is not exposed from the bit line contact hole even if misalignment occurs by thickening the bit line in the bit line contact hole portion. It was the target.

  In this case, no matter how much over-etching is performed, no dent in the contact hole 15b portion can occur, and at the same time, a short circuit, which is a problem of the present embodiment, does not occur. In other words, there is no longer room for miniaturization, and the above-described device structure causes the problem of this embodiment.

  As another numerical example, when the diameter of the bit line contact hole 15b is designed to be 0.22 μm and the positional deviation is 0.09 μm, d = 0.1 μm, t = 0.065 μm, Δ = 0.01 μm.

Again, when 0.01 μm of shaving in the formation of the sidewall and 0.02 μm of withstand voltage are added, the minimum value of the recess becomes 0.04 μm.
As another numerical example, when the coverage is not 100% and the side wall width is 60 nm at the contact hole 15b based on the present embodiment, d = 0.1 μm, t = 0.056 μm and Δ = 0.024 μm. When 0.01 μm of shaving due to sidewall formation and 0.02 μm of withstand voltage are added again, the minimum value of the dent becomes 0.054 μm.

Referring to FIG. 21C, thereafter, the storage electrode 27 is formed in the same manner as in FIGS. 18H to 18J described in the ninth embodiment.
Referring to FIG. 21D, capacitor insulating film 29 (not shown), counter electrode 30, interlayer insulating film 31, and wiring layers 32, 33 are further formed in the same manner as in FIGS. 18K and 18L described in the ninth embodiment. Form.

Thereafter, a semiconductor device having a stack type capacitor is manufactured through processes such as an interlayer insulating film and a wiring layer.
In this embodiment, the bit line contact portion is exposed in the storage electrode contact, and the bit line 22 and the storage electrode 27 are in contact with each other. Etching is performed.

  That is, the conductor constituting the bit line in the contact hole 15b portion of the bit line protruding from the bit line pattern is recessed, and the sidewall 23 is formed on the bit line 22 when the sidewall 23 is formed. By filling with a film, the contact can be prevented without increasing the number of steps.

[Eleventh Embodiment] An eleventh embodiment of the present invention will be described with reference to the drawings.
FIG. 22 is a cross-sectional view of the semiconductor device according to the eleventh embodiment, in which the same reference numerals as those in the ninth embodiment denote the same components.

Hereinafter, differences from the ninth embodiment will be described with reference to FIG. In the ninth embodiment, as shown in FIG. 18G, the sidewalls 23 are formed so that the SiO ₂ film 17 that insulates the bit lines 22 and the plugs 16 remains only under the bit lines 22 and the sidewalls 23 on the sidewalls. Sometimes removed at the same time. In the present embodiment, at the time of etching for forming the side wall 23, leaving the SiO ₂ film 17, in the step of forming a contact hole for forming a storage electrode, Si ₃ N ₄ film 25 is a stopper film when etching Following the removal, the SiO ₂ film 17 is removed so that the surface of the plug 16 is exposed.

The advantage of this embodiment is that when the Si ₃ N ₄ film 25 that is an etching stopper film is removed, the underlying layers are all made of the SiO ₂ films 17 and 23, so that the selection ratio with respect to silicon (plug 16) cannot be obtained. It can also be manufactured by the method of removing the Si ₃ N ₄ film 25.

  Note that the short-circuit problem described in detail in the tenth embodiment also occurs in the manufacturing method according to the present embodiment. FIG. 23 shows a case where the contact hole 15b of the bit line greatly protrudes from the bit line 22. The conductor constituting the bit line 22 is exposed when a contact hole for forming the storage electrode is opened, and the bit line 22 and the storage electrode 27 are short-circuited.

However, this problem can also be dealt with by making the bit line recessed as in the tenth embodiment (see FIG. 22).
[Twelfth Embodiment] In the tenth embodiment, the method for preventing a short circuit between the bit line 22 and the storage electrode 27 when the bit line contact hole 15b and the bit line 22 are displaced has been described. In the present embodiment, as a countermeasure against the same problem, another embodiment will be specifically described with reference to the drawings.

  This embodiment is shown in FIGS. 24, 25A and 25B. FIG. 24 is a plan view of the memory cell portion in the present embodiment, and FIGS. 25A and 25B are cross-sectional views of the semiconductor device in the present embodiment. 25A and 25B are a continuation of FIG. 19 described in the tenth embodiment. In the figure, the same reference numerals as those in the tenth embodiment denote the same parts.

Referring to FIG. 25A, the process up to patterning bit line 22 is the same as in the tenth embodiment.
Next, a SiO ₂ film having a thickness of 70 nm is formed by CVD, and the sidewalls 23 are formed by anisotropic etching. At this time, the SiO ₂ film 17 may be etched so as to expose the surface of the plug 16 following the anisotropic etching of the sidewall 23.

Next, an SiO ₂ film 24 having a thickness of about 30 nm is formed by CVD. Thereafter, the SiO ₂ films 17 and 24 on the plug 16 of the storage electrode contact are selectively etched by lithography using a normal or phase shift reticle to expose the surface of the plug 16 (see FIG. 24).

Referring to FIG. 25B, thereafter, the storage electrode 27 is formed in the same manner as in FIG. 21C described in the tenth embodiment. Here, in the step of opening the contact hole for forming the storage electrode, when the Si ₃ N ₄ film 25 serving as an etching stopper is etched, the SiO ₂ film 24 is used as an etching stopper. Even if the line 22 is displaced, the bit line contact portion is not exposed.

Thus, under the Si ₃ N ₄ film 25 serving as an etching stopper to form a SiO ₂ film 24, by leaving open only the top of the plug 16 of the storage electrode contact the SiO ₂ film 24, the bit Even if the line contact hole 15b and the bit line 22 are misaligned, a short circuit between the bit line and the storage electrode can be prevented.

Further, by using together with the over-etching described in the tenth embodiment, it is possible to further improve the breakdown voltage.
[Thirteenth Embodiment] In the first to twelfth embodiments, the cylinder type capacitor has been described in which the storage electrode is left on the inner wall of the contact hole forming the storage electrode 27 to obtain a crown shape. The present invention is not limited to the cylinder type capacitor, and can be applied to a simple stacked capacitor type or FIN type capacitor.

Hereinafter, an embodiment in which a simple stacked capacitor is used will be described with reference to the drawings.
FIG. 26 is a cross-sectional view of a semiconductor device having a simple stacked capacitor. In particular, the semiconductor device described in the tenth embodiment is modified to a simple stacked capacitor type. In the figure, the same reference numerals as those described in the first to twelfth embodiments denote the same elements.

Referring to FIG. 26, after the step shown in FIG. 19, side wall 23 is formed, and at that time, SiO ₂ film 17 that insulates bit line 22 and plug 16 is removed. The process up to this point is the same as in the tenth embodiment.

  Next, a doped silicon layer having a thickness of about 1 μm containing phosphorus at a high concentration is formed by CVD. At this time, it is also preferable that the surface is polished and planarized by a CMP method if necessary.

  Further, the storage electrode 27 is formed by dry etching with a Br-based gas using a patterned resist mask (not shown). Here, if necessary, irregularities can be formed on the surface of the storage electrode using a known method to increase the capacitance of the capacitor.

  If the contact hole 15b of the bit line 22 and the bit line 22 are misaligned, a short circuit between the bit line 22 and the storage electrode 27 may be a problem as before, but the bit line 22 conductor is connected to the bit line 22 as a contact. This can be prevented by recessing in the hole 15b.

Thereafter, the DRAM wafer process is completed as in the tenth embodiment.
According to this embodiment, the number of processes can be significantly reduced. In the present invention, several combinations of the first to thirteenth embodiments can be implemented.

For example, the eighth embodiment and the tenth embodiment can be combined and will be described below.
In this embodiment, when the gate electrode 8 (word line) and the bit line 22 are formed, the SiO ₂ films 6 and 20 simultaneously formed on the respective gate electrodes 8 and 20 are replaced with SiN films. 23 is changed from the SiO ₂ film to the SiN film. The SAC etching stopper films 12 and 25 used when forming the bit line contact hole 15b and the contact hole for forming the storage electrode are thin SiN films of about 20 nm so as to leave a gap. In the etching for forming the SAC, the BPSG films 13 and 26 embedded in the gap are removed, and then the thin SiN film is removed by anisotropic etching.

  Even in this case, the same technology as that of the tenth embodiment can be applied. In other words, the WSi / silicon layer in the bit line contact hole is recessed by over-etching during the bit line formation etching. And when forming SiN film side wall, this dent can be filled up.

  The relationship between the amount of the bit line contact hole 15b protruding from the bit line 22 due to misalignment, the thickness of the side wall SiN film, and the required amount of recess is substantially the same as in the tenth embodiment.

In the anisotropic etching for forming the side walls of the SiN film on the side surfaces, contact holes for forming the storage electrodes are formed without removing the SiO ₂ film 17 that insulates the bit lines 22 and the plugs 16 from each other. After the SAC etching, the SiO ₂ film 17 can be removed following the removal of the Si ₃ N ₄ film 25 as a stopper film.

  Further, in forming the word line 8 or the bit line 22, there is a method in which an organic material film is applied under or on the resist instead of the SiON films 7 and 21 as an antireflection film. In this case, the antireflection film does not remain on the device.

  Further, the material of the word line 8 or the bit line 22 is not limited to the WSi layers 5 and 19 and the silicon films 4 and 18, but a metal film such as a W / TiN film can also be used. In the case of a bit line, it is preferable to use a W / TiN / Ti film to which Ti is added as a contact metal.

[Fourteenth Embodiment] As described in the first to thirteenth embodiments, the SAC process is extremely important for manufacturing a highly integrated semiconductor device.
The key technology in the SAC process is the selection ratio between the insulating film to be etched and the stopper film that stops etching. At present, when an oxide film is used as an interlayer insulating film, a nitride film is dominant as a stopper film, but its selectivity in dry etching is not sufficient.

FIG. 27A is a cross-sectional view of the semiconductor device showing the SAC process. In the figure, the same reference numerals as those used in the first to thirteenth embodiments denote the same elements.
FIG. 27A shows a state where the SiO ₂ films 6 and 10 covering the gate electrode 8 are shaved at the shoulder of the gate electrode 8. That is, when the BPSG 13 that is the interlayer insulating film is formed thick, it is necessary to form it thick so that the Si ₃ N ₄ film 12 functions as a stopper film. However, when the Si ₃ N ₄ film 12 is etched, if the Si ₃ N ₄ film 12 is thick, the underlying SiO ₂ films 6 and 10 are scraped, and the breakdown voltage between the gate electrode and the contact is lowered. is there.

Therefore, it is difficult to use the SAC process with the current selection ratio. Therefore, in this embodiment, a stable SAC process is provided by forming the stopper Si ₃ N ₄ film in a double structure.

The fourteenth embodiment will be specifically described below with reference to the drawings. This embodiment is shown in FIGS. 27B and 27C. In the drawings, the same reference numerals indicate the same items.
FIG. 27B is a cross-sectional view of the semiconductor device of this embodiment. Referring to FIG. 27B, after forming gate electrode 8, Si ₃ N ₄ film 12a, oxide film 13a, Si ₃ N ₄ film 12b, and oxide film 13b are formed by CVD, respectively 10 nm, 50 nm, 70 nm, and 300 nm.

Next, a method for forming a contact hole between the gate electrodes 8 will be described. First, the oxide film 13b is etched using a mixed gas of C ₄ F ₈ and Ar, for example, with high density plasma. Next, the Si ₃ N ₄ film 12b is removed under conditions that allow a selective ratio to the oxide film 13a, for example, wet etching using phosphoric acid, or dry etching using a mixed gas of SF ₆ , O _2, SF ₆ , and HBr. In the same manner, the oxide film 13a and the Si ₃ N ₄ film 12a are etched.

In the case of performing the above-described dry etching in the etching of the Si ₃ N ₄ film 12a, depending on the application it is necessary to deposit an oxide film 11 under the Si ₃ N ₄ film 12a. The oxide film 11 is removed by RIE etching using CF ₄ , CHF ₃ , and Ar gas. Further, the nitride film may be etched by RIE using CF ₄ , CHF ₃ , or Ar gas.

Further, in the embodiment of FIG. 27B, the upper Si ₃ N ₄ film 12b is used as a stopper film when etching the thick oxide film 13b, so that the lower Si ₃ N ₄ film 12a It can be made much thinner than the Si ₃ N ₄ film 12b.

Next, the SAC process that can form the upper Si ₃ N ₄ film 12b thinly will be described.
Referring to FIG. 27C, after forming gate electrode 8, Si ₃ N ₄ film 12a and oxide film 13a (not shown) are formed to a thickness of 20 nm and 50 nm, respectively, by CVD, and SOG 13c is applied to 100 nm and planarized. At this time, SOG may be applied directly without forming an insulating film. Alternatively, an insulating film may be formed to 600 nm and polished to 500 nm by CMP for planarization.

Next, an Si ₃ N ₄ film 12b and an oxide film 13b are formed to a thickness of 50 nm and 300 nm, respectively, by CVD.
Note that a technique similar to that described in FIG. 27B may be used as an etching method for forming the contact hole.

In the embodiment of FIG. 27C, after forming the lower Si ₃ N ₄ film 12a, the oxide film 13c thereon is flattened. The thick oxide film 13b becomes flat, the burden on the upper Si ₃ N ₄ film 12b during etching can be reduced, and the upper Si ₃ N ₄ film 12b can be made thinner.

In this embodiment, the case where the Si ₃ N ₄ film is used as the stopper film has been described. However, as the stopper film, polysilicon or a metal oxide such as alumina can be used. At this time, the stopper alumina is etched by RIE using Cl ₂ or BCl ₃ gas or Ar sputter etching. The polysilicon is etched using Cl ₂ , BCl ₃ gas, or HBr gas. In the case where alumina or polysilicon is etched using a chlorine-based or bromine-based gas, an oxide film is preferably formed under the film.

  According to the present embodiment, the stopper film can be made sufficiently thin by using the double stopper structure. As a result, the amount of over stopper removal etching can be reduced, and a breakdown voltage can be secured.

  [Fifteenth Embodiment] FIG. 28 is a sectional view of a semiconductor substrate showing a fifteenth embodiment of the present invention. In the surface layer of the p-type silicon substrate 1, an n-type well N1 is formed in the memory cell region, a p-type well P1 is formed therein, and an n-type well N2 is formed in the peripheral circuit portion. In the memory cell region, an n-channel transfer transistor is formed in the p-type well P1, and in the peripheral circuit region, a p-channel transistor is formed in the n-type well N2. In the peripheral circuit region, a double well can be formed, and an n-channel transistor can be formed in a p-type well in an n-type well.

  A field oxide film 2 is formed on the substrate surface, and an active region surrounded by the field oxide film 2 is defined. In the memory cell region, a polycrystalline silicon layer 4 and a tungsten silicide layer 5 are formed on the gate insulating film 3 to form a gate electrode 8. On the gate electrode 8, a silicon oxide film 6 and a SiON film 7 functioning as an antireflection film are formed. The SiON film 7, the silicon oxide film 6, and the gate electrode 8 are patterned by photolithography, and a SiN sidewall insulating film 10 is formed on the sidewalls. Source / drain regions 9 into which n-type impurities are implanted are formed on both sides of the gate electrode.

  A SiN film 12 is formed on the entire surface of the substrate on which such a gate electrode (word line) is formed. A BPSG film 13 is formed on the SiN film 12 and constitutes an interlayer insulating film. Contact holes for storage electrode contacts are formed through the BPSG film 13 and the SiN film 12 and are filled with the polycrystalline silicon region 16. The polycrystalline silicon region 16 is etched back or polished so as to form the same surface as the BPSG film 13, and an HTO (high temperature oxidation) silicon oxide film 17 is formed on the surface by CVD.

  In the bit line contact region, a contact hole is formed through the HTO film 17, the BPSG film 13, and the SiN film 12, and a polycrystalline silicon film 18 and tungsten are formed on the surface of the HTO film 17 so as to bury the inner surface of the contact hole. A wiring composed of a stack of silicide films 19 is formed. This wiring constitutes a bit line. The bit line is insulated from the polycrystalline silicon region 16 buried with the HTO film 17. A stack of a silicon oxide film 21 and a SiN film 22 is formed on the surface of the bit line and patterned simultaneously with the bit line. A sidewall spacer of the SiN film 23a is formed on the side wall of the bit line structure.

  Using the SiN film 22 and the SiN sidewall spacer 23a as an etching stopper, a contact hole for a storage electrode is formed, and the surface of the polycrystalline silicon region 16 is exposed.

In addition to this structure, the storage capacitor is formed by the polycrystalline silicon layer 27 to be the storage electrode, the Ta ₂ O ₅ capacitor dielectric layer 29 formed on the surface thereof, and the TiN layer 30 formed on the surface thereof. It is formed.

A BPSG film 31 serving as an interlayer insulating film is formed so as to embed the storage capacitor, and its surface is flattened by etch back, polishing, or the like.
In the peripheral circuit region, the bit line and the wiring layer formed by the same structure as the bit line through the BPSG film 31, the wiring layer formed by the same process as the word line and the word line, and the conductive region on the substrate surface A reaching hole is formed, and a wiring composed of a laminate of a barrier layer 32 and a W layer 33 by a TiN / Ti laminate is formed.

  In this configuration, an SiN film is directly formed on the gate electrode sidewall and the bit line sidewall of the transfer transistor, and functions as an etching stopper. On the surface of the BPSG film 13, the SiN film is not formed, but the CVD oxide film 17 is formed directly. Even in such a configuration, the contact hole can be opened at a desired position by using the SiN film covering the upper and side surfaces of the bit line as an etching stopper.

  Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

1 is a plan view of a semiconductor device according to a first embodiment of the present invention. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by 1st Embodiment of this invention. It is a top view corresponding to sectional drawing of FIG. 2D. FIG. 6 is a plan view of a memory cell of a semiconductor device according to a second embodiment of the present invention. It is a top view of the peripheral circuit of the semiconductor device by 2nd Embodiment of this invention. In the following, the figure with the letter A shows a memory cell, and the figure with the letter B shows a peripheral circuit. FIG. 6 is a plan view of a memory cell of a semiconductor device according to a second embodiment of the present invention. It is a top view of the peripheral circuit of the semiconductor device by 2nd Embodiment of this invention. FIG. 6 is a plan view of a memory cell of a semiconductor device according to a second embodiment of the present invention. It is a top view of the peripheral circuit of the semiconductor device by 2nd Embodiment of this invention. FIG. 6 is a plan view of a memory cell of a semiconductor device according to a second embodiment of the present invention. It is a top view of the peripheral circuit of the semiconductor device by 2nd Embodiment of this invention. FIG. 6 is a plan view of a memory cell of a semiconductor device according to a second embodiment of the present invention. It is a top view of the peripheral circuit of the semiconductor device by 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by 2nd Embodiment of this invention. It is sectional drawing of the semiconductor device by 3rd Embodiment of this invention. FIG. 9D is a cross-sectional view of the semiconductor device corresponding to FIG. 9I. It is sectional drawing of the semiconductor device by 4th Embodiment of this invention. It is sectional drawing of the semiconductor device by 5th Embodiment of this invention. It is sectional drawing of the semiconductor device by 6th Embodiment of this invention. It is sectional drawing of the semiconductor device by 7th Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by 8th Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by 8th Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by 8th Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by 8th Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by 8th Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by 8th Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by 8th Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by 8th Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by 8th Embodiment of this invention. It is a top view of the memory cell part by a 9th embodiment of the present invention. 14 is a sectional view of a memory cell and a peripheral circuit according to a ninth embodiment of the present invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by 9th Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by 9th Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by 9th Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by 9th Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by 9th Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by 9th Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by 9th Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by 9th Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by 9th Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by 9th Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by 9th Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by 9th Embodiment of this invention. It is sectional drawing of the semiconductor device explaining the problem of 9th Embodiment. It is sectional drawing of the semiconductor device explaining the problem of 9th Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device by 10th Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by 10th Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by 10th Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device by 10th Embodiment of this invention. It is sectional drawing of the semiconductor device by 11th Embodiment of this invention. It is sectional drawing of the semiconductor device explaining the problem of 11th Embodiment. It is a top view of the memory cell part of the semiconductor device by 12th Embodiment of this invention. It is sectional drawing of the semiconductor device by 12th Embodiment of this invention. It is sectional drawing of the semiconductor device by 12th Embodiment of this invention. It is sectional drawing of the semiconductor device by 13th Embodiment of this invention. It is a substrate sectional view for explaining a semiconductor device by a 14th embodiment of the present invention. It is a substrate sectional view for explaining a semiconductor device by a 14th embodiment of the present invention. It is a substrate sectional view for explaining a semiconductor device by a 14th embodiment of the present invention. It is a substrate sectional view for explaining a semiconductor device by a 15th embodiment of the present invention. It is sectional drawing of the semiconductor device by a prior art example.

Explanation of symbols

4 Silicon layer 5 WSi
6 SiO ₂ film 7 SiON film 8 Gate electrode (word line, first layer wiring)
9 n ⁻ type impurity diffusion layer 10 Side wall 11 SiO ₂ film 12 Si ₃ N ₄ film 13 BPSG
14 Si ₃ N ₄ film 15 Contact hole 15 a Contact hole 15 b for storage electrode connection Bit hole contact hole 16 Plug 17 SiO ₂ film 18 Silicon layer 19 WSi
20 SiO ₂ film 21 SiON film 22 Bit line 23 Side wall 24 SiO ₂ film 25 Si ₃ N ₄ film 27 Storage electrode 29 Dielectric film 30 Counter electrode

Claims (13)

In a semiconductor device having a memory cell region and a peripheral circuit region on a semiconductor substrate,
A transfer transistor including a pair of impurity diffusion regions formed in the substrate and a gate electrode formed on the substrate surface;
A first insulating film formed on the substrate so as to cover the transfer transistor;
A first contact hole penetrating the first insulating film and reaching one of the pair of impurity diffusion regions;
A conductive plug filled in the first contact hole;
A second insulating film formed on the first insulating film, covering the conductive plug, and penetrating the first and second insulating films and reaching the other of the pair of impurity diffusion regions. Two contact holes,
A bit line extending on the second insulating film and connected to the other impurity diffusion region through the second contact hole;
A third insulating film covering the upper and side surfaces of the bit line;
An opening formed in the second insulating film on the conductive plug in alignment with a third insulating film covering a side surface of the bit line;
A storage electrode insulated from the bit line by the second and third insulating films and electrically connected to the conductive plug through the opening;
A dielectric film formed on the surface of the storage electrode;
A counter electrode formed on the surface of the dielectric film;
A semiconductor device.   The semiconductor device according to claim 1, wherein an upper surface of the first insulating film is substantially flat.   The semiconductor device according to claim 1, wherein the bit line is made of a metal layer.   The semiconductor device according to claim 1, wherein a contact hole similar to the second contact hole in the memory cell region is also formed in the peripheral circuit region. In a method for manufacturing a semiconductor device having a memory cell region and a peripheral circuit region on a semiconductor substrate,
Forming a transfer transistor including a pair of impurity diffusion regions and a gate electrode on the substrate;
Forming a first insulating film on the substrate so as to cover the transfer transistor;
Forming a first contact hole penetrating the first insulating film and reaching one of the pair of impurity diffusion regions;
Forming a conductive layer in the first contact hole and forming a storage electrode connection plug;
Covering the connection plug and forming a second insulating film on the first insulating film;
Forming a second contact hole penetrating the second and first insulating films and reaching the other of the pair of impurity diffusion regions;
Forming a bit line extending on the second insulating film and connected to the other impurity diffusion region through the second contact hole;
Forming a storage electrode electrically connected to the plug;
Forming a dielectric film on the surface of the storage electrode;
Forming a counter electrode on the surface of the dielectric film;
A method for manufacturing a semiconductor device comprising:   6. The method of manufacturing a semiconductor device according to claim 5, further comprising a step of making the surface of the first insulating film substantially flat after forming the first insulating film.   6. The method of manufacturing a semiconductor device according to claim 5, wherein the step of forming the second contact hole simultaneously forms a contact hole in the memory cell region and the peripheral circuit region. Forming the first insulating film comprises:
Forming a lower insulating film on a region including the transfer transistor;
A step of selectively removing the lower insulating film in the peripheral region;
Forming an upper insulating film;
A method for manufacturing a semiconductor device according to claim 5, comprising:   The step of forming the first insulating film includes a step of forming an uppermost insulating film on the upper insulating film. Further, following the step of forming the counter electrode, the counter electrode is used as a mask. 6. The method of manufacturing a semiconductor device according to claim 5, further comprising a step of selectively removing the uppermost insulating film. Forming the transfer transistor comprises:
Forming an antireflection film on the conductive layer;
A step of patterning the conductive layer thereafter;
Next, removing the antireflection film;
A method for manufacturing a semiconductor device according to claim 5, comprising: The step of removing the antireflection film comprises:
11. The method for manufacturing a semiconductor device according to claim 10, further comprising a step of selectively removing the antireflection film in the peripheral circuit region. In a method for manufacturing a semiconductor device having a memory cell region and a peripheral circuit region on a semiconductor substrate,
Forming a transfer transistor including a pair of impurity diffusion regions and a gate electrode on the substrate;
Forming a first insulating film on the substrate so as to cover the transfer transistor;
Forming a first contact hole penetrating the first insulating film and reaching one of the pair of impurity diffusion regions;
Forming a conductive layer in the first contact hole and forming a storage electrode connection plug;
Covering the plug and forming a second insulating film on the first insulating film;
Forming a second contact hole penetrating through the second insulating film and the first insulating film and reaching the other of the pair of impurity diffusion regions;
Forming a bit line extending on the second insulating film and connected to the other impurity diffusion region through the second contact hole;
Forming a third insulating film covering the bit line;
Anisotropically etching the third insulating film to form a sidewall made of the third insulating film on the side wall of the bit line;
Etching the second insulating film using the bit line and the sidewall as a mask to expose the connection plug;
Forming a storage electrode electrically connected to the connection plug;
Forming a dielectric film on the surface of the storage electrode;
Forming a counter electrode on the surface of the dielectric film;
A method for manufacturing a semiconductor device comprising: In a method for manufacturing a semiconductor device having a memory cell region and a peripheral circuit region on a semiconductor substrate,
Forming a transfer transistor including a pair of impurity diffusion regions and a gate electrode on a substrate;
Forming a first insulating film on the substrate so as to cover the transfer transistor;
Forming a first contact hole penetrating the first insulating film and reaching one of the pair of impurity diffusion regions;
Filling the first contact hole with a conductive layer to form a storage electrode connection plug;
Covering the plug and forming a second insulating film on the first insulating film;
Forming a second contact hole penetrating through the second insulating film and the first insulating film and reaching the other impurity diffusion region;
Forming a bit line extending on the second insulating film and connected to the other of the pair of impurity diffusion regions via the second contact hole;
Forming a third insulating film covering the bit line;
Anisotropically etching the third insulating film to leave the third insulating film on the side wall of the bit line;
Then, forming a storage electrode electrically connected to the plug;
Forming a dielectric film on the surface of the storage electrode;
Forming a counter electrode on the surface of the dielectric film;
Have
In the step of forming the bit line, the etching is performed so that a larger amount of the conductive layer than the total thickness of the conductive layer and the second insulating film can be removed.

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