JPH11260915A - Semiconductor device and manufacture of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the deterioration of characteristics and reliability due to a void generated in an isolated area, by forming an opening for connecting wiring layers across an element formation region and the isolated region. SOLUTION: An opening is formed across an element formation region 2 and an isolated region 1 so that a coating body 10 covering the side face of a void generated in the isolated region 1 can be formed. Also, the opening is formed across the element formation region 2 and the isolated region 11 so that the coating body 10 can be formed in a boundary part between the isolated area 1 and the element formation region 2 can be formed for preventing the generation of the void in the isolated area 1. The opening is formed across the element formation region 2 and the isolated region 1, so that the side face of the void generated in the isolated region 1 can be covered by the coating body 10, or the generation of the void can be prevented, and the generation of joint leak can be prevented by the coating body 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a technique effective when applied to isolation between elements of a semiconductor device.

[0002]

2. Description of the Related Art In a semiconductor device, in order to prevent a plurality of elements formed on the same semiconductor substrate from interfering with each other, an inter-element separation for separating a region where each element is formed is performed. . As one of the methods of forming an isolation insulating film as such an isolation region and performing element isolation, a LOCOS (LOCalO) method for forming a thick oxide film on a main surface of a semiconductor substrate is known.
An xidation of Silicon field insulating film is known.

In this LOCOS type field insulating film, the silicon nitride film formed on the main surface of the semiconductor substrate via the silicon oxide film is used as a mask by utilizing the effect of preventing the diffusion of oxygen and water vapor of the silicon nitride film. Oxidation is performed to form a thick silicon oxide film in the silicon nitride film exposed region on the surface of the semiconductor substrate. During this thermal oxidation, the oxidation also proceeds in the lateral direction, so that a bird's beak is formed on the periphery of the silicon nitride film. An inclined surface is formed. This bird's beak limits the minimum distance between elements, which is a major problem in improving the degree of integration of elements.

One of the methods to solve this problem is to use S
A GI (Shallow Groove Isolation) type field insulating film has been considered. In the SGI field insulating film,
A groove is provided in the main surface of the semiconductor substrate, and the groove is filled with an insulator such as silicon oxide. About SGI, for example, IEEE "1996 Symposium on VLSI Technology
Digest of Technical Papers, pp. 158-159
Page.

Further, as shown in FIG. 1, in a semiconductor device, a semiconductor region 3 such as a source region and a drain region of an element formed in an element forming region 2 separated by an isolation region 1 in this manner, and a semiconductor substrate. Interlayer insulating film 4 on the main surface
And the wiring layer 5 formed through the hole is connected and conductive through an opening provided in the interlayer insulating film to form a circuit. Conventionally, in consideration of the alignment error of photolithography and the like, an alignment margin where the semiconductor region 3 is widened with respect to the opening provided for the connection is provided to absorb the error when the opening is formed.

However, since this alignment margin is an obstacle to advancement of miniaturization, a self-aligned contact (SAC) utilizing a difference in etching selectivity to a material is used.
Is used. In this method, as shown in FIG.
For example, in an opening for making contact with a source region, a drain region, or the like, an interlayer insulating film 4 mainly made of silicon oxide is formed by utilizing an etching selectivity between silicon nitride and silicon oxide.
A stopper film 6 made of relatively thin silicon nitride is provided underneath. First, using this stopper film 6 as an etching stopper, the interlayer insulating film 4 made of silicon oxide is removed by etching, and then etching for removing the stopper film 6 is performed. And
The connection area is exposed.

In the etching of the thick interlayer insulating film 4, the etching progresses partially due to a difference in thickness or the like. However, the progress is stopped by the stopper film 6 even in a portion where the etching progresses rapidly, and the semiconductor region 3 or the isolation region is separated. It is possible to prevent the etching from progressing to the region 1.

In the SAC, when the cap and the sidewall 8 are made of, for example, silicon nitride and the interlayer insulating film 4 is made of silicon oxide, the cap and the sidewall 8 are formed on the cap or the sidewall 8 due to a mask alignment error or the like. Utilizes the difference in the etching selectivity for each material to prevent the gate electrode 7 from being exposed by this etching by slowing the progress of the etching 8 to the cap and the side wall, and to form an opening in the isolation insulating film 1.
Is applied, the isolation insulating film 1 is etched.
The influence of the conductor of the wiring layer 5 formed in the void formed therein is avoided by the depth of the semiconductor region 3 such as the source region and the drain region.

Regarding SAC, see, for example, “U
LSI Process Technology ”, pp. 41-55.

[0010]

However, the aforementioned SG
When I is not formed flat with respect to the element formation region and a slope due to a height difference is generated at the boundary between the SGI and the element formation region, as shown in FIG. 3, the stopper film 6 made of silicon nitride is formed at this portion. Due to poor step coverage
The formed silicon nitride becomes thinner than other portions. Therefore, as shown in FIG. 4, in addition to the stopper film 6, the isolation insulating film 1 in this portion is removed by etching, so that a gap is generated.

Further, even if the SGI is formed flat,
Overetching is performed to eliminate the residue of the stopper film, and the surface portion of single crystal silicon in the element formation region and the surface portion of silicon oxide in the isolation region are removed. At this time, the progress of etching of silicon oxide is faster than that of single crystal silicon. As a result, the isolation insulating film is shaved, and a void is generated in the isolation region.

As each element is miniaturized, a diffusion layer such as a source region and a drain region formed on the main surface of the semiconductor substrate is formed shallower, so that the opening is formed as shown in FIG. 5 or FIG. Is partially located in the isolation insulating film 1, the isolation insulating film 1 is etched by the opening formation.
Is cut off, voids are formed beyond the depth of the semiconductor region 3 such as the source region and the drain region, and the wiring layer 5 may be connected to the element formation region 2. In such a state, when the wiring layer 5 is at the power supply potential and the element formation region 2 is at the ground potential, the power supply is short-circuited immediately.
As the shallow junction advances, the occurrence of such defects increases.

Further, when the opening is partially located in the isolation insulating film, the contact area between the wiring layer and the connection region is reduced, so that the connection resistance is increased.

An object of the present invention is to provide a technique capable of solving such a problem and improving characteristics and reliability of a semiconductor device provided with an isolation insulating film.

Another object of the present invention is to provide a technique capable of reducing the alignment margin and improving the degree of integration of elements. The above and other problems and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0016]

Means for Solving the Problems Among the inventions disclosed in the present application, the outline of typical inventions will be briefly described.
It is as follows. An opening for connecting an element formed in an element formation region in which the main surface of the semiconductor substrate is separated by an isolation region and a wiring layer formed on the main surface of the semiconductor substrate via an insulating film is provided in the element formation region and the opening. By forming over the separation region, a covering is formed to cover the side surface of the void generated in the separation region.

Further, since the opening is formed over the element formation region and the isolation region, the opening is formed at a boundary between the isolation region and the element formation region in order to prevent a gap from being generated in the isolation region. Form a coating.

[0018] According to the above-described means, by the covering,
The opening is formed over the element formation region and the isolation region, thereby covering a side surface of a void generated in the isolation region, or preventing the void from being generated and preventing the occurrence of a junction leak. Becomes possible.

Hereinafter, embodiments of the present invention will be described. In all the drawings for describing the embodiments, components having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted.

[0020]

(Embodiment 1) FIG. 7 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention. In the present embodiment, a semiconductor substrate main surface made of, for example, single crystal silicon is separated into each element formation region 2 by an SGI type isolation insulating film 1 as a selectively formed isolation region, and the isolated element formation region 2, for example, boron or phosphorus is implanted as an impurity depending on the element to be formed.

Here, a MISFET is formed as the element, and a gate insulating film 9 is formed on the main surface of the element forming region 2.
, A gate electrode 7 is provided. Gate electrode 7
For example, a silicide film 7b is laminated on a low-resistance polycrystalline silicon film 7a, and a side wall 8 made of silicon oxide is formed on a side surface of the gate electrode 7. A semiconductor region 3 serving as a source region and a drain region of the MISFET is formed in the element forming region 2 located on both sides of the gate electrode 7, and the surface of the semiconductor region 3 is self-aligned at the same time as the silicide film 7b of the gate electrode 7. The resistance is reduced by the silicide film 3b which is formed in an intended manner.

Each element forming region 2 and the elements formed therein are covered with an interlayer insulating film 4.
For example, a silicon oxide film made of P-TEOS, a silicon oxide film made of SOG, and a silicon oxide film made of P-TEOS are sequentially deposited and planarized.

The wiring layer 5 formed on the main surface of the semiconductor substrate via the interlayer insulating film 4 is connected to the connection region of the device formed in the device forming region 2 through an opening provided in the interlayer insulating film 4. However, during the etching for forming the opening, the opening is formed over the element formation region 2 and the isolation insulating film 1 due to an error in mask alignment or the like. Voids may occur in the insulating film 2.

For this reason, in the present embodiment, the side surface of the element forming region 2 and the side surface of the isolation region 1 that are exposed to the voids thus formed in the isolation insulating film 1 are covered with the cover 10. The cover 10 is also provided on the side surface of the interlayer insulating film 4 exposed at the opening. Polycrystalline silicon is used as the coating 10, and this polycrystalline silicon is
An impurity of the same conductivity type that is the same as or lower than that of the semiconductor region 3 such as a non-doped or adjacent source region or drain region is introduced.

When non-doped high-resistance polycrystalline silicon is used, junction leakage can be prevented by covering and insulating the element formation region 2 where the cover 10 is exposed. When impurities of the same conductivity type are introduced into the semiconductor region 3 at a concentration equal to or lower than that of the semiconductor region 3, the semiconductor region 3 is extended and interposed between the semiconductor region 3 and the wiring layer 4. Junction leakage with the region 2 can be prevented.

When a film is formed at a sharp corner portion of the opening by sputtering or the like, as shown in FIG. As a result, as shown in FIG. 9, the corners in the opening are made gentle, and there is also an effect that such a film formation defect can be prevented. This effect is based on the presence / absence of voids generated in the isolation insulating film. It is valid regardless of.

Although the wiring layer 5 formed on the main surface of the semiconductor substrate via the interlayer insulating film 4 and the connection region of the semiconductor region 3 are connected through an opening provided in the interlayer insulating film 4, The wiring layer 5 may extend directly into the opening or may be connected through a plug provided in the opening.

Next, a method of manufacturing a semiconductor device according to the present embodiment will be described for each step with reference to FIGS. First, the main surface of the semiconductor substrate is separated into each element formation region 2 by an isolation insulating film 1, and a semiconductor region 3 serving as a source region, a drain region, or the like is formed in each element formation region 2.
A polycrystalline silicon film 7a of a gate electrode 7 made of polycrystalline silicon is formed on the element forming region 2 between the semiconductor region 3 serving as a source region and a drain region via a gate insulating film 9. The side surface of the gate electrode 7 is covered with a side wall 9, and the semiconductor region 3 and the gate electrode 7
A salicide process is performed to form silicide films 3b and 7b by reacting with a high melting point metal such as titanium or tungsten.

Each element formed in the element forming region 2 is covered with an interlayer insulating film 4, which is made of, for example, a silicon oxide film made of P-TEOS, a silicon oxide film made of SOG, or a P-TEOS. Silicon oxide films are sequentially deposited to flatten device steps caused by the gate electrode 7 and the like. In the interlayer insulating film 4, an opening for exposing a connection region of the semiconductor region 3, such as a source region and a drain region, is formed by photolithography and dry etching.
In the present embodiment, the opening on the right side in the figure is formed so as to be shifted from the isolation insulating film 1 due to a mask alignment error or the like, and forms the isolation insulating film 1 with the silicide film 3b of the semiconductor region 3 or the silicon of the element formation region 2. Due to the difference in the etching rate from that of silicon oxide, a gap exceeding the depth of the semiconductor region 3 is formed in the isolation insulating film 1. This state is shown in FIG.

Next, the non-doped polycrystalline silicon film 11
With a relatively low temperature plasma C where impurity diffusion hardly occurs.
VD is deposited on the entire surface by 50 ° to 500 °.
This state is shown in FIG.

Next, the deposited polycrystalline silicon film 11
Is anisotropically etched by dry etching to form a coating 10 on the side surfaces of the element forming region 2 and the side surfaces of the isolation region 1 exposed in the voids. This coating 10
Is similarly formed on the side surface of the interlayer insulating film 4 exposed in the opening. This state is shown in FIG.

Thereafter, for example, a barrier film made of titanium nitride and a metal film made of tungsten are sequentially deposited by sputtering to perform patterning to form a wiring layer 5, and the state shown in FIG. 7 is obtained.

Although the coating 10 functions even in a non-doped state, when impurities are introduced, polycrystalline silicon doped with impurities may be deposited in advance. Alternatively, as shown in FIG. A coating on which non-doped polycrystalline silicon is deposited is formed, annealed at 700 ° C. to 1000 ° C. for about 1 minute, and impurities are diffused from the adjacent semiconductor region 3 such as a source region and a drain region into the coating 10 by impurity diffusion. There is also a method to introduce. Since the impurity diffusion of single crystal silicon forming the element forming region is slower than that of polycrystalline silicon, the influence of this annealing on the impurity distribution of the element forming region 2 is small.

As shown in FIG. 14, a method of implanting impurities into the coating 10 by implanting impurity ions in a state where the coating 10 is formed and activating it by annealing at 700 ° C. to 1000 ° C. for about 1 minute. There is also. In this ion implantation, ion implantation is also performed on the source region and the drain region. However, since the depth of the ion implantation is reduced by the silicide film 3b provided for lowering the resistance, the vicinity of the silicide film 3b is low. Although the resistance is changed, the influence on the boundary region of the semiconductor region 3 serving as the source region and the drain region is small.

As a modification of this embodiment, FIG.
As shown in (1), the cover 10 may be formed by selective growth of the exposed element formation region 2 or semiconductor region 3. In order to introduce impurities into the coating 10 formed in this manner, as in the case described above, for example, as shown in FIG. 16, impurity ions are implanted while the coating 10 is formed, and 700 ° C. to 1000 ° C., 1 Activated by annealing for about a minute, impurities can be introduced into the coating body 10.

(Embodiment 2) FIGS. 17 to 19 are longitudinal sectional views showing a main part of a semiconductor device according to another embodiment of the present invention.

In this embodiment, a semiconductor substrate main surface made of, for example, single crystal silicon is separated into each element formation region 2 by an SGI type separation insulating film 1 as a selectively formed separation region, and the separation is performed. In the element formation region 2, for example, boron or phosphorus is implanted as an impurity depending on the element to be formed.

Here, a MISFET is formed as the element, and a gate insulating film 9 is formed on the main surface of the element forming region 2.
, A gate electrode 7 is provided. Gate electrode 7
For example, a silicide film 7b is laminated on a low-resistance polycrystalline silicon film 7a, and a side wall 8 made of silicon oxide is formed on a side surface of the gate electrode 7. A semiconductor region 3 serving as a source region and a drain region of the MISFET is formed in the element forming region 2 located on both sides of the gate electrode 7, and the surface of the semiconductor region 3 is self-aligned at the same time as the silicide film 7b of the gate electrode 7. The resistance is reduced by the silicide film 3b which is formed in an intended manner.

Each element formation region 2 and the elements formed therein are covered with an interlayer insulating film 4.
For example, a silicon oxide film made of P-TEOS, a silicon oxide film made of SOG, and a silicon oxide film made of P-TEOS are sequentially deposited and planarized.

The wiring layer 5 formed on the main surface of the semiconductor substrate via the interlayer insulating film 4 and the connection region of the device formed in the device forming region 2 are connected through an opening provided in the interlayer insulating film 4. However, at the time of etching for forming the opening, the opening may be formed over the element formation region 2 and the isolation insulating film 1 as shown on the right side of the drawing due to a mask alignment error or the like. is there.

In the present embodiment, the cover 10 is formed at the boundary between the element formation region 2 and the isolation region 1 in order to prevent a gap from being generated in the isolation insulating film 1 due to such a displacement of the opening. . As shown in FIG. 17 or FIG. 18, when the height of the isolation insulating film 1 is different from that of the element formation region 2, the cover 10 is separated by the height difference. As shown in FIG. 19, the side wall is formed to cover the slope formed at
If a recess is formed at the boundary between the isolation insulating film 1 and the element formation region 2, the recess is formed to cover the recess.

As the coating 10, for example, silicon nitride or polycrystalline silicon is used, and this coating prevents generation of voids in the isolation region 1 due to the etching.

When low-resistance polycrystalline silicon doped with impurities is used, the connection region between the wiring layer 5 and the semiconductor region 3 is formed by covering and insulating the element formation region 2 where the cover 10 is exposed. Can be prevented from decreasing.

The wiring layer 5 formed on the element forming region 2 via the interlayer insulating film 4 and the connection region of the element formed in the element forming region 2 are connected through an opening provided in the interlayer insulating film 4. Although the connection is made, the wiring layer 5 may extend directly into the opening, or may be connected through a plug provided in the opening.

Next, a method of manufacturing a semiconductor device according to the present embodiment will be described for each step with reference to FIGS. Here, the case where the isolation region is formed higher than the element formation region is described as an example.

First, the main surface of the semiconductor substrate is separated into each element formation region 2 by an isolation insulating film 1, and in each element formation region 2, a semiconductor region 3 serving as a source region, a drain region and the like is formed. Polycrystalline silicon film 7a of gate electrode 7 made of polycrystalline silicon is formed on element formation region 2 between semiconductor regions 3 to be regions through gate insulating film 9.
Are formed. The side surface of the gate electrode 7 is covered with a side wall 9, and the semiconductor region 3 and the gate electrode 7 are subjected to salicide treatment for forming silicide films 3b and 7b by reacting with a high melting point metal such as titanium or tungsten. . FIG. 20 shows this state.

Next, a silicon nitride film or a polycrystalline silicon film 12 is deposited on the entire surface of the semiconductor substrate. This state is shown in FIG.
It is shown in FIG.

Next, the deposited silicon nitride film or polycrystalline silicon film 12 is subjected to anisotropic etching by dry etching to cover the slope of the isolation region 1 formed at the boundary with the element formation region 2. The cover 10 is formed in a sidewall shape. The cover 10 is similarly formed on the side wall 8 of the gate electrode 7. This state is shown in FIG.

Next, each element formed in the element formation region 2 is formed, for example, by an interlayer insulating film 4 in which a silicon oxide film of P-TEOS, a silicon oxide film of SOG, and a silicon oxide film of P-TEOS are sequentially deposited. And flatten the element steps caused by the gate electrode 7 and the like. The interlayer insulating film 4 is formed by photolithography and dry etching.
An opening for exposing a connection region of the semiconductor region 3 such as a source region and a drain region is formed. This state is shown in FIG.

Thereafter, for example, a barrier film made of titanium nitride and a metal film made of tungsten are sequentially deposited by sputtering, and patterning is performed to form a wiring layer 5, and the state shown in FIG. 17 is obtained.

When impurities are introduced into the polycrystalline silicon used as the cover 10, polycrystalline silicon doped with impurities may be deposited in advance. Alternatively, non-doped polycrystalline silicon may be deposited. There is also a method in which impurity ions are implanted and activated to introduce impurities into the cover 10.

Here, the case where the isolation insulating film 1 shown in FIG. 17 is formed higher than the element formation region 2 is taken as an example, but the isolation insulation film 1 shown in FIG. On the other hand, when formed low, the cover 10 can be formed by the same process even when a recess is formed at the boundary between the isolation insulating film 1 and the element formation region 2 shown in FIG.

The wiring layer 5 formed on the main surface of the semiconductor substrate via the interlayer insulating film 4 and the connection region of the device formed in the device forming region 2 are connected through an opening provided in the interlayer insulating film 4. Although the connection is made, the wiring layer 5 may extend directly into the opening, or may be connected through a plug provided in the opening.

As described above, the invention made by the present inventor is:
Although a specific description has been given based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the gist of the invention.

For example, in the above description, the SGI type isolation insulating film has been described. However, the present invention can be carried out using another isolation region such as LOCOS.

[0056]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. (1) According to the present invention, even when an opening for connecting a wiring layer is formed over an element formation region and an isolation region by forming a cover, the effect of voids generated in the isolation region can be reduced. There is an effect that it can be alleviated. (2) According to the present invention, by forming a cover, even when an opening for connecting a wiring layer is formed over an element formation region and an isolation region, it is possible to prevent a gap from being generated in the isolation region. There is an effect that it can be prevented. (3) According to the present invention, the effects (1) and (2)
There is an effect that junction leakage can be prevented. (4) According to the present invention, by forming the covering, there is an effect that a decrease in the contact area between the wiring layer and the connection region can be prevented, and an increase in connection resistance can be prevented. (5) According to the present invention, according to the effects (3) and (4),
There is an effect that characteristics and reliability of the semiconductor device can be improved. (6) According to the present invention, according to the above effects (3) and (4),
There is an effect that the integration margin can be reduced and the degree of integration of the element can be improved.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing a main part of a conventional semiconductor device.

FIG. 2 is a longitudinal sectional view showing a main part of a conventional semiconductor device.

FIG. 3 is a longitudinal sectional view illustrating a problem of a conventional semiconductor device.

FIG. 4 is a longitudinal sectional view illustrating a problem of a conventional semiconductor device.

FIG. 5 is a longitudinal sectional view illustrating a problem of a conventional semiconductor device.

FIG. 6 is a longitudinal sectional view illustrating a problem of a conventional semiconductor device.

FIG. 7 is a longitudinal sectional view illustrating a main part of a semiconductor device according to an embodiment of the present invention;

FIG. 8 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention.

FIG. 9 is a longitudinal sectional view illustrating a main part of a semiconductor device according to an embodiment of the present invention;

FIG. 10 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process.

FIG. 11 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process.

FIG. 12 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process;

FIG. 13 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process.

FIG. 14 is a longitudinal sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process.

FIG. 15 is a vertical cross-sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process;

FIG. 16 is a vertical cross-sectional view showing a main part of a semiconductor device according to an embodiment of the present invention for each process;

FIG. 17 is a longitudinal sectional view showing a main part of a semiconductor device according to another embodiment of the present invention.

FIG. 18 is a longitudinal sectional view showing a main part of a semiconductor device according to another embodiment of the present invention.

FIG. 19 is a longitudinal sectional view showing a main part of a semiconductor device according to another embodiment of the present invention.

FIG. 20 is a longitudinal sectional view showing a main part of a semiconductor device according to another embodiment of the present invention for each step.

FIG. 21 is a longitudinal sectional view showing a main part of a semiconductor device according to another embodiment of the present invention for each step.

FIG. 22 is a longitudinal sectional view showing a main part of a semiconductor device according to another embodiment of the present invention for each step.

FIG. 23 is a longitudinal sectional view showing a main part of a semiconductor device according to another embodiment of the present invention for each step.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Isolation insulating film, 2 ... Element formation area, 3 ... Semiconductor area,
3b, 7b: silicide film, 4: interlayer insulating film, 5: wiring layer, 6: stopper film, 7: gate electrode, 7a, 11: polycrystalline silicon film, 8: sidewall, 9: gate insulating film, 10 ... Covering member, 12: silicon nitride film or polycrystalline silicon film.

Claims (10)

[Claims] An insulating film includes an element formed in an element forming region in which a main surface of a semiconductor substrate is separated by an isolation region, and a wiring layer formed on the main surface of the semiconductor substrate via an insulating film. A semiconductor device connected through the opening, wherein the opening is formed over the element formation region and the isolation region, thereby forming a cover that covers a side surface of a void generated in the isolation region. Semiconductor device. 2. An insulating film comprising: an element formed in an element forming region in which a main surface of a semiconductor substrate is separated by an isolation region; and a wiring layer formed on the main surface of the semiconductor substrate via an insulating film. In a semiconductor device connected through an opening, a cover is formed at a boundary portion between the isolation region and the element formation region, and the opening is formed over the element formation region and the isolation region, thereby achieving isolation. A semiconductor device which prevents generation of a void in a region. 3. The semiconductor device according to claim 1, wherein the cover is made of silicon nitride or polycrystalline silicon. 4. The semiconductor device according to claim 3, wherein no impurity is introduced into said polycrystalline silicon. 5. The semiconductor device according to claim 3, wherein an impurity is introduced into said polycrystalline silicon. 6. An insulating film comprising: an element formed in an element forming region in which a main surface of a semiconductor substrate is separated by an isolation region; and a wiring layer formed on the main surface of the semiconductor substrate via an insulating film. In a method of manufacturing a semiconductor device connected through an opening, a step of forming an insulating film covering a main surface of a semiconductor substrate on which the element is formed, and a step of forming an opening in the insulating film located in a connection region of the element Forming the cover covering the side surface of the void formed in the isolation region by forming the opening over the element formation region and the isolation region; and forming a conductor filling the opening. A semiconductor device. 7. An element formed in an element formation region in which a main surface of a semiconductor substrate is separated by an isolation region, and a wiring layer formed on the main surface of the semiconductor substrate via an insulating film are provided in the insulating film. In a method of manufacturing a semiconductor device connected through an opening, a step of separating a main surface of a semiconductor substrate on which the element is formed to form an isolation region for forming each element formation region; A step of forming a cover for preventing a void from being formed in the separation region by forming the opening over the element formation region and the separation region at a boundary portion of the element; Forming an insulating film covering the main surface of the semiconductor substrate; forming an opening in the insulating film located in a connection region of the element; and forming a conductor filling the opening. Wherein a. 8. The semiconductor device according to claim 6, wherein the cover is made of silicon nitride or polycrystalline silicon. 9. The semiconductor device according to claim 8, wherein no impurities are introduced into said polycrystalline silicon. 10. The semiconductor device according to claim 8, wherein an impurity is introduced into said polycrystalline silicon.