JPH10284700A - Manufacture of semiconductor integrated circuit device and semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To ensure a sufficient contact area at the bottom of a contact hole, even if the contact hole is shifted a little in the direction crossing a wiring by a method, wherein the connection hole is drilled in a self-alignment manner and its shape is so formed as to be long in a direction crossing the wirings adjacent to each other. SOLUTION: The shape of a connection hole STC for a capacitor is such that a dimension in the extension direction of a bit line BL is larger than a dimension in the widthwise direction of the bit line BL. Therefore, the area of the upper surface of a plug P, which is exposed from the opening of the connection hole STC 51 for the capacitor, i.e., the contact area between the storage electrode of the capacitor C and the plug P, is larger than the contact area in the case of a connection hole 51. Further, even if the position of the connection hole STC for the capacitor is shifted from the position of the pattern of the plug P, the contact area between the storage electrode of the capacitor C and the plug P can be fully ensured. Therefore, the electrical connection between the capacitor C and a selective MOS-FET Q can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor integrated circuit device and a semiconductor integrated circuit device technology, and more particularly to a method of manufacturing a semiconductor integrated circuit device having a DRAM (Dynamic Random Access Memory) and a semiconductor integrated circuit device. It is about technology that is effective to apply.

[0002]

2. Description of the Related Art A DRAM is a semiconductor memory that represents a large-capacity memory. The memory capacity of the DRAM tends to increase more and more, and accordingly, the area occupied by the memory cell must be reduced from the viewpoint of improving the integration degree of the memory cell of the DRAM.

However, the storage capacitance of an information storage capacitor (capacitor) in a memory cell of a DRAM is DR
It is known that a certain amount is required regardless of the generation from the viewpoint of consideration of the operation margin of the AM, the soft error, and the like, and it is generally not possible to reduce proportionally.

Therefore, a capacitor structure capable of securing a required storage capacity within a limited small occupied area has been developed. As the structure, a two-layer electrode made of polysilicon or the like is used to form a capacitor insulating film. Stack through,
A three-dimensional capacitor structure such as a so-called stacked capacitor is used.

In a stacked capacitor, a capacitor electrode is formed of a selection MOS.FET (Metal Oxide Semi) of a memory cell.
In general, the structure is arranged in a layer above the conductor field effect transistor. In this case, a large storage capacity can be secured with a small occupation area, and the required storage capacity can be reduced.

As such a stacked capacitor structure, for example, a capacitor is arranged above a bit line, that is, a so-called capacitor over bit line (Capacitor).
Over Bitline (hereinafter abbreviated as COB).

In this structure, since the underlying step of the storage electrode (storage node) can be flattened by the bit line, various loads such as a reduction in process load when forming a capacitor can be achieved. There are features.

In the COB structure, since the capacitors are arranged in the upper layer of the bit line, the capacitor connection holes for electrically connecting the capacitors and the semiconductor regions of the selection MOS • FETs are adjacent to each other. A structure is provided between bit lines and between adjacent word lines under the bit lines.

However, in this case, it is necessary to form the connection holes so that the conductor film in the capacitor connection holes does not short-circuit with the bit lines and the word lines. Bit line spacing
It must be widened to some extent in consideration of misalignment and the like, which hinders improvement in the degree of element integration and reduction in chip size. Therefore, in order to realize high integration, advanced alignment technology and process management are required.

Therefore, in order to avoid such a problem, the surface of the word line is covered with an insulating material different from the interlayer insulating film such as a nitride film or the like, so that the connection hole for the capacitor is subjected to a normal etching process. There is a technique for forming the self-alignment.

In this technique, when a connection hole for a capacitor is formed by etching, the nitride film around the word line functions as an etching stopper, even if the connection hole extends over the word line in plan. So
Without the word line being exposed from the connection hole,
Connection holes can be formed.

It is to be noted that D having a memory cell having a COB structure
The RAM is described in JP-A-7-122654 and the like. Japanese Patent Application Laid-Open No. 9-55479 describes a technique for forming a capacitor connection hole in a self-aligned manner.

[0013]

By the way, the present inventor has studied a technique of forming the above-mentioned connection hole for a capacitor in a self-aligned manner. The following is not a known technique, but is a technique studied by the present inventor, and its outline is as follows.

That is, in the above-described technology for forming the capacitor connection holes in a self-alignment manner, the capacitor connection holes are formed in a plane circular shape, and the hole diameter is determined by the distance between adjacent bit lines. The interval is set.

However, when the diameter of the capacitor connection hole is set to the minimum distance between adjacent bit lines, there is a problem that a sufficient contact area with the semiconductor region cannot be secured at the bottom of the connection hole. In particular, the plane position of the connection hole is
The contact area is expected to shift, and in that case, the contact area is further reduced.

For this reason, the capacitor and the selection MOS / FE
As a result of an increase in the contact resistance of the T with the semiconductor region,
However, there is a problem that the reading and writing of information cannot be performed sufficiently and the operation margin of the DRAM is significantly reduced, and the function and operation reliability of the DRAM are significantly reduced.

Also, the capacitor connection hole, whose hole diameter is determined by the minimum interval between adjacent bit lines, is very fine and is approaching the processing limit, so that it is difficult to make a good hole, and sometimes it is not opened. As a result, there is a problem that the yield of the DRAM is significantly reduced.

On the other hand, as a technique for forming such fine connection holes, there is a photolithography technique using a phase shift mask. In this technique, the resolution of the transfer pattern can be improved by manipulating the phase of the transmitted light.

However, the phase shift technique is an advanced and expensive technique, and it takes time and labor to introduce a new process into the manufacturing process of the semiconductor integrated circuit device, and the development period of the semiconductor integrated circuit device becomes longer. There's a problem.

In particular, in the memory cell region of a DRAM, connection holes are arranged at high density and the space between adjacent holes tends to be reduced more and more, so that it is difficult to design a pattern on a phase shift mask and to properly arrange the patterns. Under the circumstances, the transfer of the fine pattern is being limited.

An object of the present invention is to provide a technique capable of sufficiently securing a contact area at a bottom portion of a connection hole when the connection hole is formed in a self-alignment manner even if the connection hole is slightly displaced. is there.

Another object of the present invention is to provide a technique capable of improving a processing margin of a connection hole when the connection hole is formed in a self-aligned manner.

Still another object of the present invention is to form a connection hole in a self-aligned manner without introducing a sophisticated and expensive technique such as a phase shift technique. It is to provide the technology that can be done.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0025]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

According to the method of manufacturing a semiconductor integrated circuit device of the present invention, there are provided (a) a step of forming a plurality of wirings on a semiconductor substrate, and (b) a step of covering the surfaces of the plurality of wirings with a nitride film. c) a step of depositing an insulating film made of a material different from the nitride film on the semiconductor substrate after the nitride film covering step; and (d) wiring of the plurality of wirings adjacent to each other in the insulating film. In the case of forming a connection hole such that a part of the semiconductor substrate is exposed in a region between the above, by performing an etching process in a state where the etching selectivity between the insulating film and the nitride film is increased, Perforating the connection hole in a self-aligning manner; and (e)
The planar shape of the connection hole is formed so that the length in the direction intersecting the adjacent wires is longer than the length in the extending direction of the adjacent wires.

Further, according to the method of manufacturing a semiconductor integrated circuit device of the present invention, a memory cell selection MIS formed on a semiconductor substrate is provided.
A semiconductor integrated circuit device having a DRAM including a plurality of word lines constituting a gate electrode of an FET and a plurality of bit lines extending above the word lines so as to be orthogonal to the extending direction of the word lines; A manufacturing method, comprising: (a) forming the plurality of word lines on a semiconductor substrate; and (b)
Covering the surfaces of the plurality of word lines with a nitride film; and (c) forming a nitride film on the semiconductor substrate after the nitride film covering step.
Depositing an insulating film made of a material different from the nitride film; and (d) in the insulating film, a portion of the semiconductor region of the memory cell selection MIS • FET is exposed between adjacent word lines. When drilling a simple connection hole,
By performing an etching process in a state where the etching selectivity between the insulating film and the nitride film is increased, the connection holes are formed in a self-aligned manner, and the planar shape of the connection holes is set to the word line. The length in the crossing direction is
Forming a shape longer than the length of the word line in the extending direction.

Another outline of the invention disclosed in the present application is as follows.

The method of manufacturing a semiconductor integrated circuit device according to the present invention comprises the steps of (a) depositing a conductor film and a first nitride film for forming a wiring on a semiconductor substrate in order from the bottom, and then depositing the conductor film and the first nitride film; Forming a plurality of wirings on which a cap film made of a first nitride film is provided by patterning the film; and (b) forming the plurality of wirings and the cap on the semiconductor substrate after the wiring forming step Depositing a second nitride film so as to cover the film, and etching back the nitride film to form sidewalls made of a nitride film on side surfaces of the plurality of wirings and the cap film; (c) A) depositing an insulating film made of a material different from the nitride film on the semiconductor substrate after the sidewall forming step; and (d) in the insulating film, In the case where a connection hole exposing a part of the semiconductor substrate is formed in a region between adjacent wirings, an etching selectivity between the insulating film and the first nitride film and the second nitride film is increased. (E) forming a plane shape of the connection hole in a direction intersecting the adjacent wirings by performing an etching process in a state where the connection hole is formed. However, it is formed in a shape that is longer than the length of the adjacent wiring in the extending direction.

According to the method of manufacturing a semiconductor integrated circuit device of the present invention, a memory cell selection MIS · F formed on a semiconductor substrate is provided.
Manufacturing of a semiconductor integrated circuit device having a DRAM including a plurality of word lines forming a gate electrode of an ET and a plurality of bit lines extending in a layer above the word lines so as to be orthogonal to a direction in which the word lines extend. And (a) depositing a conductor film and a first nitride film for forming a wiring on a semiconductor substrate in order from a lower layer, and then patterning the conductor film and the first nitride film, thereby forming a first Forming a plurality of wirings provided with a cap film made of one nitride film;
(B) depositing a nitride film on the semiconductor substrate after the wiring formation step so as to cover the plurality of wirings and the cap film, and etching back the nitride film to form the plurality of wirings and the cap film; Forming a sidewall made of a nitride film on the side surface; (c) depositing an insulating film made of a material different from the nitride film on the semiconductor substrate after the sidewall forming step; In the insulating film, the memory cell selection MIS • FET is provided in a region between adjacent wirings of the plurality of wirings.
When drilling a connection hole such that the semiconductor region is exposed, the etching process is performed in a state where the etching selectivity between the insulating film and the first nitride film and the second nitride film is increased. (E) making the plane shape of the connection hole in the direction crossing the word line longer than the length in the direction in which the word line extends. It is formed in a shape that becomes longer.

According to the method of manufacturing a semiconductor integrated circuit device of the present invention, a memory cell selection MIS · F formed on a semiconductor substrate is provided.
Manufacturing of a semiconductor integrated circuit device having a DRAM including a plurality of word lines forming a gate electrode of an ET and a plurality of bit lines extending in a layer above the word lines so as to be orthogonal to a direction in which the word lines extend. And (a) depositing a conductor film and a first nitride film for forming a wiring on a semiconductor substrate in order from a lower layer, and then patterning the conductor film and the first nitride film, thereby forming a first Forming a plurality of word lines provided with a cap film made of one nitride film; and (b) depositing a second nitride film on the semiconductor substrate after the word line forming step, thereby forming the plurality of word lines. Covering the side surfaces of the word lines, the surface of the cap film, and the flat surface on the semiconductor substrate with a second nitride film; and (c) forming the first nitride film on the semiconductor substrate after the second nitride film covering process. Different from nitride film (D) forming a connection hole in the insulating film between the word lines so that a semiconductor region of the memory cell selection MIS • FET is exposed. By performing the etching process in a state where the etching selectivity between the insulating film and the first nitride film and the second nitride film is increased,
When the connection holes are formed in a self-aligned manner, the etching rate of the insulating film is higher than that of the first nitride film and the second nitride film.
An etching process is performed under conditions such that the etching speed is higher than the etching speed of the nitride film to expose the second nitride film on the flat surface of the semiconductor substrate. Then, the first nitride film and the second nitride film are exposed. Performing an etching process under such a condition that the etching rate is higher than the etching rate of the insulating film, and drilling the connection holes in a self-aligning manner. Are formed in such a shape that the length in the direction intersecting with the word line is longer than the length in the extending direction of the word line.

The method of manufacturing a semiconductor integrated circuit device according to the present invention is directed to a method of selecting a memory cell MIS.F formed on a semiconductor substrate.
Manufacturing of a semiconductor integrated circuit device having a DRAM including a plurality of word lines forming a gate electrode of an ET and a plurality of bit lines extending in a layer above the word lines so as to be orthogonal to a direction in which the word lines extend. (B) forming a groove-shaped buried isolation region in the semiconductor substrate by forming a separation groove in the semiconductor substrate and then burying a separation film in the separation groove; After a conductor film and a first nitride film for wiring formation are sequentially deposited from the lower layer on the semiconductor substrate, the conductor film and the first nitride film are patterned to form a cap made of the first nitride film on the upper portion. Forming a plurality of word lines provided with a film, and (c) depositing a second nitride film on the semiconductor substrate after the word line forming step, thereby forming side surfaces of the plurality of word lines and a cap film. Surface and A step of covering a flat surface on the semiconductor substrate with a second nitride film, and (d) an insulating layer made of a material different from the first nitride film on the semiconductor substrate after the step of covering the second nitride film. Depositing a film; and (e) forming the memory cell selection MIS • FE in the insulating film in a region between adjacent ones of the plurality of wirings.
In order to drill a connection hole where the semiconductor region of T is exposed,
By performing an etching process in a state where the etching selectivity between the insulating film and the first nitride film and the second nitride film is increased, when the connection holes are formed in a self-aligned manner, An etching process is performed under such a condition that the etching rate is higher than the etching rates of the first nitride film and the second nitride film, thereby exposing the second nitride film on the flat surface of the semiconductor substrate. After the first
The etching rates of the nitride film and the second nitride film are
Performing an etching process under conditions such that the etching speed is higher than the etching rate of the insulating film, and piercing the connection hole in a self-aligned manner.
The wiring is formed in such a shape that the length in the direction intersecting the adjacent wirings is longer than the length in the extending direction of the adjacent wirings.

The method of manufacturing a semiconductor integrated circuit device according to the present invention comprises the steps of: (a) depositing a conductor film and a first nitride film for forming a wiring on a semiconductor substrate in order from the bottom, and then depositing the conductor film and the first nitride film; Forming a plurality of wirings on which a cap film made of a first nitride film is provided by patterning the film; and (b) forming the plurality of wirings and the cap on the semiconductor substrate after the wiring forming step Depositing a second nitride film so as to cover the film, and etching back the nitride film to form sidewalls made of a nitride film on side surfaces of the plurality of wirings and the cap film; (c) A) depositing a first insulating film made of a material different from the nitride film on the semiconductor substrate after the sidewall forming step; and (d) forming the plurality of first insulating films on the first insulating film. Wiring Forming a plurality of second wirings extending in a direction intersecting the existing direction; and (e) depositing a second insulating film made of the same material as the second wiring on the first insulating film. Covering the plurality of second wirings, and (f) in the first insulating film and the second insulating film, between the first wirings adjacent to each other and between the second wirings adjacent to each other. In the case where a connection hole such that a part of the semiconductor substrate is exposed is formed in the region, the first insulating film and the second insulating film and the first nitride film and the second nitride film Performing a self-aligned drilling of the connection hole by performing an etching process in a state where the etching selectivity is increased, and (g) changing the planar shape of the connection hole to the first wiring adjacent to each other. The length in the direction intersecting Is to shaped to be longer than the length in the extending direction of the first wiring.

The method of manufacturing a semiconductor integrated circuit device according to the present invention relates to a method of manufacturing a memory cell selection MIS · F formed on a semiconductor substrate.
Manufacturing of a semiconductor integrated circuit device having a DRAM including a plurality of word lines forming a gate electrode of an ET and a plurality of bit lines extending in a layer above the word lines so as to be orthogonal to a direction in which the word lines extend. And (a) depositing a conductor film and a first nitride film for forming a wiring on a semiconductor substrate in order from a lower layer, and then patterning the conductor film and the first nitride film, thereby forming a first Forming a plurality of word lines provided with a cap film made of one nitride film; and (b) depositing a second nitride film on the semiconductor substrate after the word line forming step, thereby forming the plurality of word lines. Covering the side surfaces of the word lines, the surface of the cap film, and the flat surface on the semiconductor substrate with a second nitride film; and (c) forming the first nitride film on the semiconductor substrate after the second nitride film covering process. Different from nitride film Depositing a first insulating film made of a material; (d) forming the plurality of bit lines on the first insulating film; and (e) forming the same on the first insulating film. Depositing a second insulating film made of a material to cover the plurality of bit lines; and (f) between the word lines adjacent to each other in the first insulating film and the second insulating film. In order to form a connection hole for a capacitor between adjacent bit lines so that a semiconductor region of the memory cell selection MIS • FET is exposed,
By performing an etching process in a state where the etching selectivity between the first insulating film and the second insulating film and the first nitride film and the second nitride film is increased, the connection hole for the capacitor can be formed by itself. When drilling in a consistent manner, under the condition that the etching rate of the first insulating film and the second insulating film is faster than the etching rate of the first nitride film and the second nitride film. After performing an etching process to expose the second nitride film on the flat surface of the semiconductor substrate, the etching rates of the first nitride film and the second nitride film are higher than those of the first insulating film and the second nitride film. Performing an etching process under conditions such that the etching speed is higher than the etching rate of the second insulating film, and piercing the connection hole for the capacitor in a self-aligning manner; and (g) planarizing the connection hole for the capacitor. Shape, front Length in a direction crossing the word lines, and forms the shape is longer than the extending direction of the length of the word line.

According to the semiconductor integrated circuit device of the present invention, a plurality of word lines forming a gate electrode of a memory cell selection MIS • FET formed on a semiconductor substrate and a word line above the word lines in a direction perpendicular to the word lines extend. A semiconductor integrated circuit device having a DRAM having a plurality of bit lines extending so as to perform: (a) an isolation region in which an isolation film is buried in an isolation trench dug in the semiconductor substrate; (B) a nitride film covering the surfaces of the plurality of word lines; and (c) a material different from the nitride film and deposited on the semiconductor substrate so as to cover the nitride film and the plurality of word lines. The first insulating film, and (d) the first insulating film,
A connection hole formed in a region between adjacent word lines so that a semiconductor region of the memory cell selection MIS • FET is exposed, and has an etching selectivity between the first insulating film and the nitride film. A connection hole for a bit line formed in a self-aligned manner by an etching process in an enlarged state; and (e) the memory cell selection MIS formed on the first insulating film through the connection hole for the bit line.・ FE
A plurality of bit lines electrically connected to the semiconductor region of T; (f) a second insulating film deposited on the first insulating film so as to cover the plurality of bit lines; g) In the first insulating film and the second insulating film, a semiconductor region of the memory cell selection MIS • FET is exposed in a region between adjacent word lines and between adjacent bit lines. Connection hole drilled as follows,
(H) a capacitor connection hole formed in a self-aligned manner by an etching process in a state where an etching selectivity between the first insulating film and the second insulating film and the nitride film is increased. The planar shape of the connection hole for the bit line and the connection hole for the capacitor is such that the length in the direction crossing the word line is longer than the length in the extending direction of the word line. It is.

[0036]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings. (Note that components having the same functions in all drawings for describing the embodiments are denoted by the same reference numerals.) , And the repeated explanation is omitted).

(Embodiment 1) FIGS. 1 and 2 are plan views of a main part of a memory area of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIGS. 3 and 4 are FIGS.
5 is a plan view of a main part of a memory area for explaining misalignment of a pattern in a memory area of the semiconductor integrated circuit device, and FIG. 5 and FIG. FIG. 7 is a plan view of a main part of the memory region for comparing the case of the semiconductor integrated circuit device of FIG. 1 with the technology studied by the present inventor, and FIG. FIG. 8B is a cross-sectional view taken along line VIII-VIII, FIG. 8B is a cross-sectional view of a main part of a peripheral circuit region in the semiconductor integrated circuit device of the present embodiment, and FIG.
FIG. 10 is a sectional view taken along the line XX of FIG. 1 and FIG.
1 to 43 are explanatory diagrams of a method of manufacturing the semiconductor integrated circuit device of FIG.

In the first embodiment, the case where the present invention is applied to, for example, a 64M DRAM will be described. However, the word configuration is not limited to this, and can be variously changed.

First, the planar structure of the memory area in the DRAM according to the first embodiment will be described with reference to FIGS.
In FIGS. 1 and 3 to 7, a predetermined pattern is hatched in a mesh pattern so as to make the drawings easy to see.

The semiconductor substrate 1 constituting this DRAM is
For example p ^- made form of silicon (Si) single crystal, on the main surface of the semiconductor substrate 1 in the memory region, a plurality of active regions D, a separation region S is disposed surrounding it.

The active region D in the memory region is patterned, for example, in a gull wing shape. From the active region D, a part of the main surface of the semiconductor substrate 1 is not covered with the insulating film for forming the isolation region. Is exposed.

Then, in the active region D where the main surface of the semiconductor substrate 1 is exposed, the selection MOS
FET (Metal Oxide Semiconductorr Field Effect Tr)
A pair of source / drain semiconductor regions and a channel region in an anistor (Q) are formed.

In the active regions D, D vertically adjacent to each other in FIGS. 1 to 7, the center line position of each is approximately half the length of the active region D in the horizontal direction of FIGS. However, they are arranged only in the lateral direction in FIGS.

The isolation region S is a region for electrically isolating adjacent integrated circuit elements. In the isolation region S, the main surface of the semiconductor substrate 1 is covered with an insulating film for forming an isolation region. Therefore, the semiconductor substrate 1
The exposed portion of the main surface, that is, the planar shape of the active region D is formed by the insulating film of the isolation region S.

In the upper layer of the active region D and the isolation region S on the semiconductor substrate 1, patterns of a plurality of word lines WL are arranged in parallel with each other at a predetermined adjacent distance.

This word line WL is a strip-shaped conductor pattern extending in the vertical direction in FIGS. 1 to 7, and a part of the word line WL overlaps the active region D. Four lines are placed between the center lines of the active regions D adjacent to each other in the lateral direction in FIGS. 1 to 7 so that the space is arranged above the vicinity of the wing tip of the active region D and above the central region. Are located.

The portion of the word line WL that overlaps with the active region D is the gate electrode of the above-mentioned selection MOSFET Q. In the active region D, the region where the word line WL overlaps becomes the channel region of the selection MOS • FET Q, and the region on both sides of the word line WL is the source region.
It is a pair of semiconductor regions for drain.

The word line WL has a line width selected by the selection MOS.
Has a certain width required to obtain the threshold voltage of the FET Q, for example, 0.20 to 0.30 μm, preferably 0.25
It is about μm. The interval between adjacent word lines WL is, for example, about 0.15 to 0.25 μm, and preferably about 0.20 μm.

The self-aligned pattern SA overlapping each word line WL is used to form a plug connection hole PC and a bit line connection hole BLC which will be described later so that a part of the active region D is exposed. This is a pattern for forming the connection holes BLC in a self-aligned manner.

The self-aligned pattern SA is made of, for example, silicon nitride or the like, and is projected from both sides of the word line WL by a predetermined dimension in the width direction of the word line WL so as to cover the entire word line WL. It is formed wider than the word line WL.

By providing this self-aligned pattern SA, the active region D exposed from the connection holes PC and BLC is provided.
In other words (in the pair of semiconductor regions of the selection MOSFET Q), the width dimension of the word line WL is substantially defined by the interval between the self-aligned patterns SA adjacent to each other. Therefore, the word line WL is not exposed from the connection holes PC and BLC. In the active region D exposed from the connection holes PC, BLC, the dimension in the extending direction of the word line WL is defined by the diameter of the connection holes PC, BLC.

The word line WL and the self-aligned pattern SA
In the upper layer, a plurality of patterns of plugs P such as circular shapes are arranged. In FIGS. 1 and 7, the plugs P are hatched in a mesh shape so that the drawings are easy to see.

The plug P is a conductor pattern for electrically connecting the storage electrode of the capacitor C of the memory cell MC and one semiconductor region of the selection MOS • FETQ. It is arranged so as to overlap on one semiconductor region of the FET Q.

In the upper layer of the plug P, patterns of a plurality of bit lines BL are arranged in parallel with each other at a predetermined adjacent distance. The bit line BL is a conductor pattern extending in a direction intersecting the extending direction of the word line WL, and a part of the bit line BL overlaps a central protruding region of the active region D in the lower layer, and The lower plug P is provided between adjacent bit lines BL.

Each bit line BL is basically formed in a band shape. However, the portion overlapping with the above-mentioned protruding region of the active region D is formed in a pattern wider than other portions. The line width of the thin portion of the bit line BL is, for example, 0.
The distance between the narrow portions of the bit lines BL adjacent to each other is about 17 μm, for example, about 0.40 μm.

In the wide portion of the bit line BL, there is provided a bit line BL for electrically connecting the bit line BL to the protruding region of the active region D, that is, the other semiconductor region of the selection MOSFET Q. The pattern of the connection hole BLC is arranged. In FIG. 1, the bit line connection hole BLC is provided with a mesh-like hatching finer than the mesh attached to the plug P in order to make the drawing easy to see.

In the first embodiment, the shape of the connection hole BLC for the bit line is such that the dimension in the extending direction of the bit line BL (the width direction of the word line WL) is larger in the width direction of the bit line BL (the word line WL). (Extending direction).

That is, in the connection hole BLC for the bit line, the ratio of the dimension in the extending direction of the bit line to the dimension in the width direction of the bit line is larger than 1, for example.

Thus, the bit line BL and the selection MOS
The contact area of the FET Q with the other semiconductor region can be increased. That is, the bit line BL and the selection MOS
It is possible to improve the electrical connection state with the FET Q.

Moreover, the bit line BL and the selection MOS
The contact area between the FET Q and the other semiconductor region can be sufficiently ensured even if a slight misalignment occurs between the bit line connection hole BLC and the semiconductor region of the selection MOSFET Q. I have. Therefore, the connection hole BLC for the bit line and the active region D, that is, the selection MOS F
It is possible to increase the alignment margin between the ETQ and the semiconductor region.

For example, FIG. 5 shows a connection hole 50 for a bit line studied by the present inventors. In the case of this technique, the hole diameter of the connection hole 50 for the bit line is set in the width direction of the bit line (FIG. 5).
(Up and down directions). Therefore, the shape of the connection hole 50 is formed in a plane circular shape.

FIG. 5 shows a case where the alignment between the bit line connection hole 50 and the active region D is good. In FIG. 5, to make the drawing easier to see,
The active region D exposed from the bit line connection hole 50 is hatched in a mesh shape.

However, in the case of the technique shown in FIG. 5, when a misalignment occurs between the bit line connection hole 50 and the active region D, the area of the active region D exposed from the connection hole 50 is reduced. That is, the bit line and the selection MOSFET Q
The contact area with the other semiconductor region becomes very small due to the formation of the connection hole 50 in a self-aligned manner.

FIG. 6 shows an example in which the relative positions of the connection holes 50 and the active regions D are shifted so as to be separated from each other in the horizontal direction in FIG. In this case, the active region D exposed from the connection hole 50, that is, the contact area between the bit line and the other semiconductor region of the selection MOS • FET Q becomes extremely small as shown by a mesh-like hatching. .

On the other hand, in the first embodiment, the case where the alignment between the connection hole BLC for the bit line and the active region D is good, and the relative position between the connection hole BLC and the active region D are shown in FIG. FIGS. 3 and 4 show the case where the position is shifted similarly to the case. 3 and 4, in order to make the drawings easy to see, the connection holes BLC for the bit lines are used.
The active region D exposed from the surface is hatched in a mesh shape.

In the first embodiment, as shown in FIG. 4, even if the relative position between bit line connection hole BLC and active region D is displaced in the same manner as in FIG. The exposed area of the active region D exposed from the connection hole BLC, that is, the contact area between the bit line BL and the semiconductor region can be sufficiently ensured as compared with the case of FIG.

In the first embodiment, the connection hole BLC of the bit line BL is elongated in the direction in which the bit line BL extends in the plane direction of the connection hole BLC. Can be improved. Thereby, it is possible to prevent a defective opening of the connection hole BLC for the bit line.
Further, it is not necessary to introduce a sophisticated and expensive exposure technique using a phase shift mask in order to prevent the opening defect.

Next, storage electrodes of a plurality of capacitors C are arranged above the bit lines BL and the connection holes BLC for bit lines. This capacitor C is connected to the memory cell MC
, And the storage electrodes are arranged so as to overlap the pattern of the plug P.

In the first embodiment, for example, a crown-shaped capacitor C is employed. However, the capacitor C is not limited to the crown shape, but can be variously changed, and may be, for example, a fin shape.

In FIGS. 1 and 2, the frame on the outer periphery of the capacitor C indicates the side wall electrode portion of the crown-shaped storage electrode. 1 and 2 show that fine irregularities are formed on the outer periphery and the like of the side wall electrode portion.

At the center of the storage electrode of the capacitor C,
A pattern of a capacitor connection hole STC for electrically connecting the storage electrode and the plug P is arranged.

That is, the storage electrode of the capacitor C is electrically connected to the plug pattern P through the connection hole STC for the capacitor, and further electrically connected to one semiconductor region of the selection MOSFET Q through the plug pattern P. It is connected.

In FIG. 1, the connection hole STC for the capacitor is provided with a mesh-like hatching finer than the mesh attached to the plug P in order to make the drawing easy to see.

In the first embodiment, the shape of the connection hole STC for the capacitor is such that the dimension in the extending direction of the bit line BL (the width direction of the word line WL) is larger in the width direction of the bit line BL (the word line WL). (Extending direction).

That is, in the connection hole STC for the capacitor, the ratio of the dimension in the extending direction of the bit line to the dimension in the width direction of the bit line is, for example, larger than 1.

Thus, the contact area between the storage electrode of the capacitor C and the plug P can be increased. That is, it is possible to improve the electrical connection state between the capacitor C and the selection MOS • FETQ.

For example, FIG. 7 shows a comparison between the capacitor connection hole STC in the case of the present invention and the capacitor connection hole 51 studied by the present inventors. In FIG. 7, for the sake of clarity, the connection hole STC for the capacitor is used.
The connection holes 51 are provided with a mesh-like hatching, and the connection holes STC for the capacitors are provided with a mesh-like hatching finer than the mesh provided with the connection holes 51.

The connection hole 51 for the capacitor is formed such that the diameter of the connection hole 51 is smaller than that of the bit line BL so that the bit line BL is not exposed from a part of the connection hole 51 because the capacitor C is arranged above the bit line BL. It is set to the minimum dimension determined by the interval between BLs. Therefore, the connection hole 51 is formed in a plane circular shape.

On the other hand, the connection hole STC for the capacitor in the case of the first embodiment is set in such a manner that the width direction size of the bit line BL is set to the minimum size determined by the interval between the bit lines similarly to the connection hole 51. But bit line B
The dimension in the extending direction of L is set longer than the dimension in the width direction of the bit line BL.

Therefore, as can be seen from FIG. 7, the connection hole STC for the capacitor according to the first embodiment has an area where the upper surface of plug P is exposed from the opening thereof, that is, the connection hole STC for the capacitor, that is, It can be seen that the contact area between the storage electrode of the capacitor C and the plug P is large.

The storage electrode of the capacitor C and the plug P
Can be sufficiently ensured even if misalignment occurs between the capacitor connection hole STC and the pattern of the plug P. This is for the same reason as the bit line connection hole BLC described above. Therefore, it is possible to increase the alignment margin between the connection hole STC for the capacitor and the plug P.

In the first embodiment, since the planar shape of connection hole STC for capacitor C is elongated in the extending direction of bit line BL, it is possible to improve the opening processing margin of connection hole STC. It has become. Thus, it is possible to prevent a defective opening of the connection hole STC for the capacitor. Further, it is not necessary to introduce a sophisticated and expensive exposure technique using a phase shift mask in order to prevent the opening defect.

Next, the cross-sectional structure of the semiconductor integrated circuit device according to the first embodiment will be described with reference to FIGS. In addition,
FIGS. 8A, 9 and 10 are cross-sectional views of main parts of a memory area of the DRAM, and FIG. 8B is a cross-sectional view of main parts of a peripheral circuit area of the DRAM.

A deep n-well DW is formed in the semiconductor substrate 1 in the memory area. This deep n-well DW
Is a region having a function of electrically isolating the memory region from the peripheral circuit region and the like, and is formed by, for example, introducing an n-type impurity phosphorus. The deep n-well DW is set to a predetermined potential.

In the memory region and the peripheral circuit region, p wells Wpm and Wpp are formed in the upper layer of the deep n well DW of the semiconductor substrate 1. This p-well Wpm, Wpp
Is formed by introducing, for example, a p-type impurity such as boron.

A channel stopper region CS is formed in a predetermined depth region of the p wells Wpm and Wpp so that the impurity concentration reaches a peak particularly in a depth region near the bottom of the isolation groove 2a. . The channel stopper region PS is formed by introducing, for example, a p-type impurity such as boron.

In the memory region and the peripheral circuit region, the isolation region S is formed in the upper layer of the semiconductor substrate 1. In the first embodiment, the structure of the isolation region S is, for example, a groove-shaped buried isolation structure.

That is, the isolation region S is formed within the isolation trench 2a dug in the thickness direction of the semiconductor substrate 1 and the insulating film 2b for isolation.
It is formed by embedding. The isolation insulating film 2b is made of, for example, silicon dioxide (SiO ₂ ).

Here, first, the memory area will be described in detail, and then the peripheral circuit area will be described.

A memory cell MC is formed on p well Wpm of semiconductor substrate 1 in the memory area. This memory cell MC is composed of one selection MOSFET Q and one capacitor C. The size of this one memory cell MC, for example 0.35～0.65Myuemu ^2, preferably about 0.5 [mu] m ^2.

The selection MOSFET Q has a pair of semiconductor regions 3d formed on the semiconductor substrate 1 and separated from each other.
a, 3db, a gate insulating film 3i formed on the semiconductor substrate 1, and a gate electrode 3g formed on the gate insulating film 3i and being a part of the word line WL as described above.

The semiconductor regions 3da and 3db are connected to the selection MOS
This is a region for forming a source / drain region of the FET Q, and is formed by introducing, for example, an n-type impurity phosphorus.

This semiconductor region 3db is
b1 and a semiconductor region 3db2. Semiconductor region 3d
b2 is formed in a region in contact with the plug P and has a function of reducing the contact resistance with the plug P. A channel region of the selection MOSFET Q is formed below the gate electrode 3g between the semiconductor regions 3da and 3db.

The gate insulating film 3i is made of, for example, SiO ₂ . The gate electrode 3g is formed by stacking a conductor film 3g2 on the conductor film 3g1. The lower conductive film 3g1 is made of, for example, a low-resistance polysilicon film.
Upper conductive film 3g2 are, for example made of tungsten silicide (WSi _2).

The gate electrode 3 is formed by the conductive film 3g2.
g, that is, the resistance of the word line WL is lowered.
However, the gate electrode 3g may be formed of a single film of low-resistance polysilicon, or may be formed of a predetermined metal such as tungsten.

On the gate electrode 3g, that is, on the upper surface of the word line WL, a cap insulating film 5 is formed via an insulating film 4. The insulating film 4 is made of, for example, SiO ₂ or the like, and has a stress buffering function for relaxing stress from the cap insulating film 5. The cap insulating film 5 is made of, for example, silicon nitride and has the above-described self-aligned pattern SA.
(See FIG. 1 etc.).

An insulating film 6 is formed on the upper surface and side surfaces of the cap insulating film 5 and the gate electrode 3g, that is, on the flat surface of the semiconductor substrate 1 between the side surfaces of the word lines WL and adjacent word lines WL. I have.

The insulating film 6 is made of, for example, silicon nitride and has a function as the above-described self-aligned pattern SA (see FIG. 1 and the like). Note that, in the self-aligned pattern SA in FIG. 1 and the like, a region that protrudes from the word line WL by a predetermined dimension in a plane is equal to the insulating film 6 portions attached to both side surfaces of the word line WL.

As an upper layer of the insulating film 6, an interlayer insulating film 7a
Has been deposited. The interlayer insulating film 7a is made of, for example, SiO ₂
The upper surface is formed flat. On the interlayer insulating film 7a, interlayer insulating films 7b to 7d are sequentially deposited from the lower layer. In the memory region, the upper surfaces of the interlayer insulating films 7b to 7d are formed flat so as to improve the accuracy of photolithography when forming the connection holes and the like.

The interlayer insulating film 7a and the insulating film 6 include
The above-described connection hole PC for a plug is formed. One semiconductor region 3db of the selection MOSFET Q is exposed from the plug connection hole PC.

Under the plug connection hole PC, the width of the gate electrode 3g, that is, the dimension of the word line WL in the width direction is, as shown in FIG. 8A and FIG. It is defined by the insulating film 6 formed on the side surface of the word line WL). As a result, even if the position of the plug connection hole PC is slightly shifted, there is no problem that a part of the gate electrode 3g (word line WL) is exposed from the plug connection hole PC. .

On the other hand, in the plug connection hole PC, the dimension in the extending direction of the gate electrode 3g, that is, the word line WL, is determined by the diameter of the connection hole PC as shown in FIG.

However, since no other wiring is arranged in the extending direction of the word line WL in this layer, no other wiring is exposed from the connection hole PC for the plug in the extending direction. .

In the first embodiment, the insulating film 6 is also provided on the flat surface of the semiconductor substrate 1 between the word lines WL (gate electrodes 3g) adjacent to each other. When the hole PC is formed, the etching process is performed separately such that the interlayer insulating films 7a to 7d are removed by etching and then the insulating film 6 is removed by etching.

As a result, the connection hole P for the plug is planarly viewed.
This makes it possible to avoid the problem that the insulating film 2b portion of the isolation region S that falls within the range of C is etched away in the etching step for forming the connection hole PC for the plug.

The plug P described above is embedded in the plug connection hole PC. The plug P is made of, for example, low-resistance polysilicon, and is electrically connected to the semiconductor region 3db of the select MOSFET Q. The plug P
Contains, for example, an n-type impurity phosphorus.

On the upper surface of the interlayer insulating film 7d, an interlayer insulating film 7e made of, for example, SiO ₂ is deposited so as to cover the upper surface of the plug P. The bit line BL described above is formed on the interlayer insulating film 7e.

The bit line BL is formed by depositing a conductor film BL2 on the conductor film BL1 and is electrically connected to the semiconductor region 3da via the above-described bit line connection hole BLC. The conductor film BL1 is made of, for example, low-resistance polysilicon, and the conductor film BL2 is made of, for example, W.
Consisting of Si _2.

Below the bit line connection hole BLC, the width of the gate electrode 3g, that is, the width of the word line WL, as shown in FIG. WL) is defined by the insulating film 6 formed on the side surface. As a result, even if the position of the bit line connection hole BLC is slightly shifted, the problem that a part of the gate electrode 3g (word line WL) is exposed from the bit line connection hole BLC does not occur. ing.

Further, in the first embodiment, as described above, the bit line connection hole BLC is formed so that the width direction dimension of the word line WL is longer, so that the bit line connection hole is formed. Even if the relative position between the semiconductor region and the semiconductor region 3da is deviated, it is possible to ensure a sufficient contact area therebetween.

On the other hand, in this bit line connection hole BLC, the dimension in the extending direction of gate electrode 3g, ie, word line WL, is set to a value determined by the alignment condition in the width direction of bit line BL. .

However, since no other wiring is arranged in the extending direction of word line WL in this layer, another wiring may be exposed from connection hole BLC for the bit line in the extending direction. Absent.

In the first embodiment, the insulating film 6 is also provided on the flat surface of the semiconductor substrate 1 between the word lines WL (gate electrodes 3g) adjacent to each other. When drilling the connection holes BLC, the interlayer insulating films 7a to 7d are removed by etching, and then the insulating film 6 is removed by etching.

As a result, the insulating film 2b of the isolation region S which enters the range of the bit line connection hole BLC in a planar manner.
It is possible to avoid the problem that the portion is etched away during the etching process for forming the bit line connection hole BLC.

An interlayer insulating film 7f made of, for example, SiO ₂ is formed on the interlayer insulating film 7e, and covers the bit line BL. Further, the interlayer insulating film 7
7 g of an interlayer insulating film made of, for example, SiO ₂
Are formed. The upper surface of the interlayer insulating film 7g is formed flat.

On the flat upper surface of the interlayer insulating film 7g,
An interlayer insulating film 7h is formed. This insulating film 7g is
This film functions as an etching stopper when removing the base insulating film after forming the storage electrode 8 of the capacitor C, and is made of, for example, silicon nitride.

That is, by interposing the interlayer insulating film 7g on the interlayer insulating film 7f, the interlayer insulating film 7h made of silicon nitride or the like is separated from the bit line BL.
It is possible to suppress an increase in the capacity of the bit line BL due to the interlayer insulating film 7h.

Further, by flattening the upper surface of the interlayer insulating film 7g, the amount of etching can be made uniform in the plane of the memory region when the underlying insulating film after forming the storage electrode of the capacitor C is removed by etching. Thereby, the controllability of the etching can be improved.

On the interlayer insulating film 7h, the above-mentioned capacitor C is formed. That is, D of Embodiment 1
The RAM has a so-called COB structure in which a capacitor C is provided above a bit line BL.

The capacitor C is configured such that the surface of the storage electrode 8a is covered with a plate electrode 8b via a capacitor insulating film. That is, in the first embodiment, the capacitance portion is also formed on the lower surface side and the shaft portion side surface of the storage electrode 8a, so that a large capacitance can be secured.

The storage electrode 8a has a shaft 8a1 and a bottom 8a.
2, a bottom side wall 8a3, and a side wall 8a4. The shaft 8a1, the bottom 8a2, the bottom side wall 8a3 and the side wall 8a4 are made of, for example, low-resistance polysilicon.
Fine irregularities are formed on the surface.

The bottom 8a2 and the bottom side wall 8a3 of the storage electrode 8a are portions used as an etching mask when the connection hole STC for the capacitor is formed.

The capacitor insulating film is formed, for example, by depositing a SiO ₂ film on a silicon nitride film. Also,
The plate electrode 8b is made of, for example, low-resistance polysilicon and is electrically connected to a predetermined wiring.

The shaft portion 8a1 of the storage electrode 8a of the capacitor C is connected to the connection hole S for the capacitor.
It is electrically connected to one semiconductor region 3db of the selection MOS-FET Q through TC.

The connection hole STC for the capacitor is formed between the adjacent bit lines BL in the lower layer of the capacitor C, and the upper surface of the plug P is exposed from the connection hole STC for the capacitor.

In the connection hole STC for the capacitor, the dimension of the gate electrode 3g, that is, the direction in which the word line WL extends (the width direction of the bit line BL), is as shown in FIGS. It is set to the minimum value determined by the interval between the bit lines BL adjacent to each other.

On the other hand, in the first embodiment, the gate electrode 3g,
That is, as shown in FIG. 9, the dimension of the word line WL in the width direction is longer than the dimension of the word line WL in the extending direction. Therefore, as mentioned above,
It is possible to increase the contact area between the storage electrode 8 of the capacitor C and the plug P.

On this plate electrode 8b, for example, Si
Through an interlayer insulating film 7i made of O ₂ or the like, for example, BPS
An interlayer insulating film 7j made of G (Boro Phospho Silicate Glass) or the like is formed. The upper surface of the interlayer insulating film 7j is formed flat. Further, an interlayer insulating film 7k made of, for example, SiO ₂ is formed on the interlayer insulating film 7j.

Next, the peripheral circuit area will be described in detail. Above the semiconductor substrate 1 in the peripheral circuit region, the above-described p-well Wpp is formed.
An n-channel type MOSFET Qn is formed on pp.

The semiconductor substrate 1 in the peripheral circuit region
In this case, an n-well is also formed in the same layer as the p-wells Wpm and Wpp. The n-well is formed by introducing, for example, an n-type impurity such as phosphorus. On this n-well,
A p-channel type MOSFET is formed.

These n-channel type MOSFETs Q
A sense amplifier circuit, a column decoder circuit, a column driver circuit, a row decoder circuit, a row driver circuit, an I / O selector circuit, a data input buffer circuit, a data output buffer circuit, a power supply circuit, etc. of a DRAM by n- and p-channel MOSs. Is formed.

The n-channel type MOS-FET Qn has p
The semiconductor device includes a pair of semiconductor regions 9da and 9db formed apart from each other on the well Wpp, a gate insulating film 9i formed on the semiconductor substrate 1, and a gate electrode 9g formed on the gate insulating film 9i. doing.

The semiconductor regions 9da and 9db are regions for forming the source / drain of the n-channel type MOSFET Qn, and have low impurity concentration regions 9da1 and 9da, respectively.
db1 and high impurity concentration regions 9da2 and 9db2 having a higher impurity concentration.

The low impurity concentration regions 9da1 and 9db1 are formed by introducing, for example, n-type impurity phosphorus, and the high impurity concentration regions 9da2, 9db2 are formed by introducing, for example, n-type impurity As. Note that this semiconductor region 9da,
The channel region of the n-channel type MOSFET Qn is formed between 9 db.

The gate insulating film 9i is made of, for example, SiO ₂ . The gate electrode 9g is formed by depositing a conductor film 9g2 on a conductor film 9g1. The conductor film 9g1 is made of, for example, low-resistance polysilicon, and the conductor film 9g2 is made of, for example, W.
Consisting of Si _2. However, the gate electrode 9g may be formed of, for example, a single film of low-resistance polysilicon, or may be formed of metal.

The insulating film 4 is formed on the upper surface of the gate electrode 9g.
A cap insulating film 5 is formed through the substrate. Insulating film 4
Is made of, for example, SiO ₂ or the like, and has a stress buffering function for relaxing stress from the cap insulating film 5. The cap insulating film 5 is made of, for example, silicon nitride.

On the side surfaces of the gate electrode 9g and the cap insulating film 5, a side wall 6a made of, for example, silicon nitride is formed. Further, a side wall 10a made of, for example, SiO ₂ or the like is formed on a side surface of the side wall 6a.

The side walls 6a, 10a
Are mainly provided in the semiconductor substrate 1 in the low impurity concentration region 9da1,
It has a function as a mask for ion implantation for forming 9db1 and the high impurity concentration regions 9da2 and 9db2.

On such a semiconductor substrate 1, the above-mentioned interlayer insulating films 7c to 7g are deposited. Interlayer insulating film 7
The upper surfaces of d, 7e, 7g and 7i are formed flat.
The above-described interlayer insulating film 7j is formed on the interlayer insulating film 7i. The upper surface of the interlayer insulating film 7j is also formed flat.

A first layer wiring 11L1 is formed on the upper surface of interlayer insulating film 7j. This first layer wiring 11L1
Is, for example, an aluminum (Al) -Si-copper (Cu) alloy or a titanium nitride (TiN) or titanium (T
i) and the like are provided.

The first layer wiring 11L1 is formed on the interlayer insulating film 7
The semiconductor region 9da of the n-channel type MOS-FET Qn is formed through the connection holes 12 formed in the holes c to 7g, 7i and 7j.
Is electrically connected to On the interlayer insulating film 7j, the above-described interlayer insulating film 7k is formed, thereby covering the first layer wiring 11L1.

Next, a method of manufacturing the DRAM of the first embodiment will be described with reference to FIGS.

FIG. 11 is a cross-sectional view of a main part of the memory region and the peripheral circuit region of the semiconductor substrate 1 during the manufacturing process of the semiconductor integrated circuit device.

[0144] The semiconductor substrate 1 is, for example, p ^- consists shape of Si single crystal, the separation region S of the upper portion thereof for example grooved buried structure is formed. This separation region S is formed, for example, as follows.

First, after a pad film made of SiO ₂ or the like is formed on the semiconductor substrate 1 by a thermal oxidation method or the like, an insulating film made of silicon nitride or the like is formed on the upper surface by a CVD method or the like, and further, on the upper surface thereof. A photoresist pattern is formed so as to cover the active region D (see FIG. 1).

Subsequently, using the photoresist pattern as an etching mask, an insulating film made of silicon nitride or the like is patterned, and then the photoresist pattern is removed.

Thereafter, the semiconductor substrate 1 is subjected to dry etching or the like using the remaining insulating film made of silicon nitride or the like as an etching mask to separate the semiconductor substrate 1 exposed from the insulating film made of silicon nitride or the like. A groove 2a is formed.

Finally, on the semiconductor substrate 1, for example, SiO
After depositing an insulating film made of ₂ etc. by a CVD method or the like,
An isolation region S is formed by etching back the upper surface of the insulating film by a CMP (Chemical Mechanical Polishing) method or the like so that the insulating film remains only in the isolation groove 2a.

Then, as shown in FIG. 12, a deep n-well DW is formed in the semiconductor substrate 1 by introducing, for example, phosphorus as an n-type impurity by an ion implantation method or the like.

Subsequently, for example, boron, which is a p-type impurity, is introduced into the semiconductor substrate 1 by an ion implantation method or the like, so that the p-wells Wpm and Wpp and the channel stopper region C are formed.
Form S. Note that an n-well is formed by introducing, for example, phosphorus of an n-type impurity into the semiconductor substrate 1 before and after the formation process of the p-wells Wpm, Wpp and the like by an ion implantation method or the like.

After that, by optimizing the impurity concentration in the channel region to set the threshold voltage of each MOS to a predetermined value, a predetermined impurity is added to the main surface of the semiconductor substrate 1 (active region). Ions are implanted.

Then, as shown in FIG. 13, the semiconductor substrate 1 is subjected to a thermal oxidation treatment or the like, so that the main surface of the semiconductor substrate 1 is covered with the gate insulating film 3i of the selection MOS • FET and the MOS • FET of the peripheral circuit. Of the gate insulating film 9i is formed.

Subsequently, on the semiconductor substrate 1, a conductor film made of, for example, low-resistance polysilicon doped with phosphorus and W
After sequentially depositing a conductive film made of Si ₂ or the like by the CVD method or the like, an insulating film made of, for example, SiO ₂ and an insulating film made of silicon nitride are sequentially deposited on the upper conductive film by the CVD method or the like.

Thereafter, the insulating film made of a silicon nitride film or the like, the insulating film made of SiO ₂ or the like, and the two-layer conductor film are sequentially removed by etching, so that the gate electrode 3g (word line WL) is formed in the memory cell region and the peripheral circuit region. ), 9
g, an insulating film 4 and a cap insulating film 5 are formed.

Thereafter, for example, phosphorus of an n-type impurity is introduced into the memory region by an ion implantation method or the like.
The semiconductor regions 3da and 3db1 of the selection MOSFET are formed.

In another impurity introducing step, for example, phosphorus of an n-type impurity is introduced into the peripheral circuit region by an ion implantation method or the like, so that the low impurity of the n-channel type MOS / FET of the peripheral circuit is introduced. Density region 9da1,
9 db1 is formed.

FIG. 14 is a plan view of a main part of the memory area after these steps. The word line WL is formed to extend in the vertical direction in FIG. In the word line WL, a portion crossing the active region D is a gate electrode 3g.

Next, as shown in FIG. 15, an insulating film 6 made of, for example, silicon nitride is formed on the semiconductor substrate 1 by CVD.
It is deposited by a method or the like. The insulating film 6 has a function of forming a connection hole for a plug and a connection hole for a bit line in a self-aligning manner, whereby the upper surface of the cap insulating film 5, the cap insulating film 5 and the gate electrode are formed. The side surface of 3 g and the flat surface of the semiconductor substrate 1 are covered.

FIG. 16 is a plan view of a main part of the memory area after this step. The width of the self-aligned pattern SA is formed by the width of the word line WL and the portion of the insulating film 6 covering both side surfaces thereof.

In the connection hole for the plug and the connection hole for the bit line, the width dimension (width dimension in FIG. 16) of the word line WL is defined by the interval between the self-aligned patterns SA adjacent to each other. Has become.

Next, as shown in FIG. 17, an interlayer insulating film 7a made of, for example, SiO ₂ is
After being formed by the OG (Spin On Glass) method or the like, an interlayer insulating film 7b made of, for example, SiO ₂ is formed on the upper surface thereof by CV.
It is formed by the D method or the like.

Subsequently, as shown in FIG. 18, after forming a photoresist pattern 13a by photolithography on the interlayer insulating film 7b so as to cover only the memory region, the photoresist pattern 13a is used as an etching mask. Then, the interlayer insulating films 7a and 7b (see FIG. 17) in the peripheral circuit region are removed by a wet etching method or the like.

After that, the photoresist pattern 13
The insulating film 6 (see FIG. 17) made of silicon nitride or the like in the peripheral circuit region is etched back by dry etching or the like while leaving
g and a side wall 6a made of silicon nitride or the like is formed on the side surface of the cap insulating film 5.

Then, as shown in FIG. 19, an insulating film 10 made of, for example, SiO _{2 is} formed on the semiconductor substrate 1 by CVD.
After the insulating film 10 is deposited by a dry etching method or the like,
As shown at 0, a sidewall 10a is formed on the side surface of the sidewall 6a in the peripheral circuit region.

Subsequently, using the gate electrode 9g and the side walls 6a and 10a as a mask, for example, As of an n-type impurity is introduced into the peripheral circuit region by an ion implantation method or the like, so that an n-channel impurity is formed as shown in FIG. Shape M
The hole impurity concentration regions 9da2 and 9db2 of the OS.FET Qn are formed.

Next, on the semiconductor substrate 1, for example, SiO 2
After forming by such an interlayer insulating film 7c of _two like the CVD method, on the interlayer insulating film 7c, for example, an interlayer insulating film 7d made of SiO ₂ or the like by a plasma CVD method or the like.

Subsequently, as shown in FIG. 22, after the upper surface of this interlayer insulating film 7d is formed flat by a CMP method or the like, as shown in FIG. 23, a connection for a plug is formed on the interlayer insulating film 7d. A photoresist pattern 13b exposing the hole PC is formed by photolithography.

At this time, in the first embodiment, since the upper surface of the interlayer insulating film 7d is flat, a sufficient photolithography margin can be secured, and good pattern transfer can be performed.

Then, the photoresist pattern 13
Using b as an etching mask, an etching process for drilling the plug connection hole PC is performed. Embodiment 1
In, the etching process is performed, for example, as follows.

That is, at first, as shown in FIG. 23, the SiO ₂ film is removed but the silicon nitride film is removed so that the etching is stopped when the insulating film 6 and the cap insulating film 5 are exposed. Etching is performed under conditions that are difficult to remove. As an etching gas at this time, for example, C ₄ F
₈ / A mixed gas such as argon (Ar) is used.

Subsequently, by changing the etching conditions to conditions in which the silicon nitride film is removed but the SiO ₂ film is difficult to remove, as shown in FIG. 24, a plug for exposing a part of the semiconductor substrate 1 is exposed. A connection hole PC for use.
As an etching gas at this time, for example, CHF ₃ / A
A mixed gas such as r / CF ₄ is used.

The reason for performing the etching process as described above is as follows.
Otherwise, the insulating film 2b in the isolation region S exposed from the plug connection hole PC is etched away by the etching process for forming the plug connection hole PC, thereby causing a defect. This is to prevent such a defect.

FIG. 25 is a plan view of a main portion of the memory area after the connection hole PC for a plug has been formed. FIG. 26 is a sectional view taken along line XXVI-XXVI of FIG. FIG. 27 shows a cross section at the same position as FIG. 26 when the above-described etching method is not used.

In the first embodiment, as shown in FIG. 25, the isolation region S is exposed from the plug connection hole PC as shown by a mesh-like hatching.

Therefore, when the connection holes PC for plugs are to be formed in the interlayer insulating films 7a to 7d made of SiO ₂ or the like, if the insulating film 6 made of silicon nitride or the like is not provided, the hole is to be formed by ordinary etching. Since the insulating film 2b of the isolation region S is also made of SiO ₂ or the like, as shown in FIG. 27, the portion of the insulating film 2b of the isolation region S exposed from the plug connection hole PC (the bottom of the connection hole PC) is also removed. Would.

Since the conductor film made of low-resistance polysilicon into which the n-type impurity is introduced is buried in the plug connection hole PC as described above, the semiconductor substrate 1 is formed therefrom.
The n-type impurity diffused in the substrate overlaps with the channel stopper CS to cause a failure.

However, in the first embodiment, when the connection hole PC for the plug is formed as described above, an insulating film 6 and the like are provided and the etching conditions are changed to obtain the structure shown in FIG.
As shown in FIG. 6, the insulating film 2b of the isolation region S exposed from the plug connection hole PC is also left without being removed much.
Therefore, it is possible to prevent the above-described failure.

Next, for example, phosphorus of an n-type impurity is introduced into the semiconductor substrate 1 through a connection hole PC for a plug by an ion implantation method or the like, and then a low-resistance containing, for example, an n-type impurity is formed on the semiconductor substrate 1. Polysilicon is deposited by a CVD method or the like.

Subsequently, the plug P is formed in the plug connection hole PC as shown in FIG. 28 by etching back the low-resistance polysilicon, and then, as shown in FIG. On top of this, an interlayer insulating film 7e made of, for example, SiO ₂ is deposited by a CVD method or the like, and a plug P
Cover the upper surface.

Thereafter, a photoresist pattern 13c such that the bit line connection hole STC is exposed is formed on the interlayer insulating film 7e by photolithography.

Next, the photoresist pattern 13
c as an etching mask, a connection hole BL for a bit line
An etching process for perforating C is performed. In the first embodiment, the etching process is performed, for example, as follows.

That is, initially, as shown in FIG. 29, the SiO ₂ film is removed but the silicon nitride film is removed so that the etching is stopped when the insulating film 6, the cap insulating film 5 and the like are exposed. Etching is performed under conditions that are difficult to remove. As an etching gas at this time, for example, C ₄ F
A mixed gas such as ₈ / Ar is used.

Subsequently, the etching conditions were changed to conditions in which the silicon nitride film was removed but the SiO ₂ film was difficult to remove, so that the bit was exposed so that a part of the semiconductor substrate 1 was exposed as shown in FIG. Drill a connection hole BLC for the wire. As an etching gas at this time, for example, CHF ₃
A mixed gas such as / Ar / CF ₄ is used.

The reason for performing the etching process as described above is as follows.
Otherwise, the insulating film 2b of the isolation region S exposed from the bit line connection hole BLC is etched away by the etching process for forming the bit line connection hole BLC, resulting in a defect. This is to prevent such a defect.

FIG. 31 is a plan view of the main part of the memory area after the connection hole BLC for the bit line has been formed. In the first embodiment, as shown in FIG. 31, the isolation region S is exposed from the connection hole BLC for the bit line as shown by a mesh-like hatching.

Therefore, when the connection holes BLC for bit lines are formed in the interlayer insulating films 7a to 7e made of SiO ₂ or the like, it is attempted to form the holes by ordinary etching without providing the insulating film 6 made of silicon nitride or the like. Then, since the insulating film 2b of the isolation region S is also made of SiO ₂ or the like, the insulating film 2 of the isolation region S exposed from the bit line connection hole BLC is formed.
b is also removed.

Since the conductor film made of low-resistance polysilicon into which the n-type impurity is introduced is buried in the bit line connection hole BLC as described above, the n-type impurity diffused into the semiconductor substrate 1 therefrom. And the channel stopper CS overlap to cause a failure.

However, in the first embodiment, when the connection hole BLC for the bit line is formed as described above,
By providing the insulating film 6 and the like and changing the etching conditions,
The insulating film 2b of the isolation region S exposed from the bit line connection hole BLC is also not removed so much. Therefore,
It is possible to prevent the above-described failure.

In the first embodiment, as described above, the shape of the connection hole BLC for the bit line is such that the width direction of the word line WL is longer than the extending direction of the word line WL. Shape.

As a result, the bit line BL and the selection MOS
It is possible to increase the contact area of the FET with the semiconductor region 3da. Also, a connection hole BL for a bit line is used.
It is possible to increase the alignment margin of C.

Furthermore, it is possible to increase the margin for opening the connection hole BLC for the bit line. Therefore, good drilling is possible. In addition, it is not always necessary to introduce a sophisticated and expensive technique using a phase shift mask.

[0192] Then, as shown in FIG. 32, on the semiconductor substrate 1, for example, phosphorus made of a conductor film BL1 and WSi ₂ made of low-resistance poly-silicon introduced conductive film BL
2 is sequentially deposited by a CVD method or the like.

Subsequently, the conductor films BL1 and BL2 are patterned by photolithography and dry etching to form bit lines BL as shown in FIGS. 33 and 34.

Thereafter, as shown in FIG. 35, an interlayer insulating film 7f made of, for example, SiO ₂ is
The bit line BL is covered by depositing by the VD method or the like.

Next, after an interlayer insulating film 7g made of, for example, SiO ₂ is deposited on the upper surface of the interlayer insulating film 7f by the CVD method, the upper surface of the interlayer insulating film 7g is formed flat by the CMP method or the like.

Subsequently, as shown in FIG. 36, an interlayer insulating film 7h made of, for example, silicon nitride is deposited on the upper surface of the interlayer insulating film 7g by a CVD method or the like.

In the first embodiment, interlayer insulating film 7
By providing g, the distance between the bit line BL and the interlayer insulating film 7h made of silicon nitride or the like can be increased, so that an increase in the bit line capacitance due to the interlayer insulating film 7h can be suppressed. I have.

Thereafter, an insulating film 14 made of, for example, SiO ₂ is deposited on the upper surface of the interlayer insulating film 7h by the CVD method, and then a conductive film made of, for example, low-resistance polysilicon doped with phosphorus is formed on the semiconductor substrate 1. Is deposited by a CVD method.

Next, in the conductive film, a connection hole forming region for a capacitor is opened by photolithography and dry etching to form a mask pattern of the conductive film 15.

Subsequently, a conductor film 16 made of, for example, low-resistance polysilicon doped with phosphorus is deposited on the semiconductor substrate 1 by a CVD method or the like so as to cover the conductor film 15. By performing the etch back, as shown in FIG. 37, a sidewall 16a is formed at the end of the opening region of the conductive film 15.

Thereafter, using the conductive film 15 and the side walls 16a as an etching mask, the insulating film 14 and the interlayer insulating film 7 in the regions exposed from the mask pattern are formed.
e to 7h are removed by a dry etching method or the like. In the etching process at this time, first, for example, CHF
₃ / Ar / CF ₄ carried out by a mixed gas, such as, subsequently, performed by switching, for example, in a mixed gas such as C ₄ F ₈ / Ar.

As a result, as shown in FIGS. 37 and 38, a connection hole STC for a capacitor in which a part of plug P is exposed is formed.

In FIG. 38, the plugs P and the connection holes STC for the capacitors are hatched in a net-like manner for easy viewing. Also, a line forming a substantially elliptical shape on the outer periphery of the capacitor connection hole STC indicates the outer periphery of the opening region of the conductor film 15 for the mask pattern, and the line between the line and the outer periphery of the capacitor connection hole STC is shown. Is formed with a sidewall 16a.

In the first embodiment, as described above, the shape of the connection hole STC for the capacitor is set such that the width direction of the word line WL is longer than the extending direction of the word line WL. Shaped.

As a result, it is possible to increase the contact area between the storage electrode of the capacitor and the plug P. Further, it is possible to increase the alignment margin of the connection hole STC for the capacitor.

Furthermore, it is possible to increase the margin for opening the connection hole STC for the capacitor.
Therefore, good drilling is possible. Also,
The introduction of advanced and expensive technology using a phase shift mask is not necessarily required.

Thereafter, a conductor film made of, for example, low-resistance polysilicon doped with phosphorus is deposited on the semiconductor substrate 1 by a CVD method or the like while the conductor film 15 and the sidewalls 16a are left. An insulating film made of SiO ₂ is deposited by a plasma CVD method or the like.

Next, as shown in FIG. 39, a photoresist pattern 13d for covering a capacitor connection hole STC and forming a pattern of a storage electrode of the capacitor is formed on the insulating film by photolithography.

Subsequently, the photoresist pattern 13
By using d as an etching mask, the underlying insulating film, conductive film and conductive film 15 for the mask are patterned by a dry etching method or the like.
As shown in the figure, the shaft 8a1 of the storage electrode 8a of the capacitor
, Bottom 8a2, bottom side wall 8a3 (sidewall 16
a) and an insulating film 17 are formed.

Thereafter, as shown in FIG. 41, a conductor film 18 made of low-resistance polysilicon is
After the deposition by the method D, the conductive film 18 is etched back by an anisotropic dry etching method such as RIE, so that the storage electrode 8a of the capacitor is formed as shown in FIG.
Is formed.

Thereafter, the insulating films 14 and 17 (see FIG. 41 and the like) are removed by, for example, wet etching using a hydrofluoric acid solution. At this time, since the interlayer insulating film 7h functions as a stopper for wet etching, the underlying interlayer insulating film 7g is not removed.

In the first embodiment, since the upper surface of the interlayer insulating film 7g is flat, the insulating film 14 can be uniformly etched, and the etching controllability can be improved.

Next, for example, S
After irradiating with i ₂ H ₆ gas, by performing a heat treatment,
As shown in FIG. 43, fine irregularities are formed on the surface of the storage electrode 8a.

Subsequently, after a silicon nitride film (not shown) is deposited on the semiconductor substrate 1 by the CVD method, the silicon nitride film is subjected to an oxidizing treatment, so that the surface of the storage electrode 8a of the capacitor is nitrided. A capacitor insulating film made of a silicon film and a SiO ₂ film is formed.

Thereafter, a conductor film made of, for example, low-resistance polysilicon is deposited on the semiconductor substrate 1 by the CVD method, and this conductor film is etched using a photoresist as a mask, thereby obtaining a structure shown in FIG. So, the capacitor C
Is formed.

Next, after removing the interlayer insulating film 7h in the peripheral circuit region, for example, SiO ₂
After depositing an interlayer insulating film 7i made of, for example, a CVD method, an interlayer insulating film 7j made of, for example, BPSG is deposited on the upper surface thereof, and the upper surface is formed flat by a CMP method or the like.

Subsequently, the plate electrode 8b of the capacitor C
Are formed by dry etching or the like so that the pad portion is exposed and the semiconductor region 9da of the n-channel type MOSFET Qn in the peripheral circuit region is exposed.

After that, for example, Al-
A conductor film formed by providing TiN or the like under the Si-Cu alloy or a lower layer thereof is deposited by a sputtering method or the like.

After that, the first layer wiring 11L1 is formed by patterning the conductor film by photolithography technology and dry etching technology, etc., and then an interlayer insulating film 7k made of, for example, SiO ₂ is formed on the semiconductor substrate 1. First layer wiring 11 deposited by CVD or the like
Coat L1.

According to the first embodiment, the following effects can be obtained.

(1) The plane shape of the connection hole BLC for the bit line is set in the extending direction of the bit line BL (the width direction of the word line WL).
Is longer than the dimension of the bit line BL in the width direction (the extending direction of the word line), so that the contact area between the bit line BL and the semiconductor region 3da of the selection MOS • FET Q is increased. Can be increased. This makes it possible to improve the electrical connection between the bit line BL and the selection MOS • FET Q, so that information can be read and written satisfactorily, and the DRA
The operation margin of M can be increased. Therefore, it is possible to improve the performance and operation reliability of the DRAM.

(2) The plane shape of the bit line connection hole BLC is determined by the extending direction of the bit line BL (the width direction of the word line WL).
Is longer than the dimension of the bit line BL in the width direction (the extending direction of the word line), so that the contact area between the bit line BL and the semiconductor region 3da of the selection MOS • FET Q is increased. Can be sufficiently ensured even if some misalignment occurs between them. Therefore, the connection hole BLC for the bit line and the selection MOS / FE
It is possible to increase the margin for positioning the TQ with the semiconductor region 3da.

(3) According to the above (2), it is possible to easily form the connection hole BLC for the bit line without increasing the chip size or reducing the degree of integration.

(4) The plane shape of the bit line connection hole BLC is determined by the extending direction of the bit line BL (the width direction of the word line WL).
Is made longer than the width of the bit line BL in the width direction (the extending direction of the word line), thereby improving the opening processing margin of the connection hole BLC for the bit line. It becomes possible.

(5) According to the above (4), it is possible to prevent a defective opening of the connection hole BLC for the bit line. Therefore, the yield and reliability of the DRAM can be improved.

(6) According to the above (4), it is not always necessary to introduce a sophisticated and expensive exposure technique using a phase shift mask in order to satisfactorily open the connection hole BLC for the bit line. Therefore, the development period of the DRAM can be reduced. Further, cost reduction of the DRAM can be promoted.

(7). The planar shape of the capacitor connection hole STC is such that the dimension in the extending direction of the bit line BL (the width direction of the word line WL) is greater in the width direction of the bit line BL (extending of the word line WL). The contact area between the capacitor connection hole STC and the plug P can be increased by making the shape longer than the dimension of the current direction). This makes it possible to improve the electrical connection between the capacitor C and the selection MOSFET Q, so that information can be read and written satisfactorily and the operation margin of the DRAM can be increased. Become. Therefore, DR
It is possible to improve the performance and operation reliability of the AM.

(8) The shape of the connection hole STC for the capacitor is determined by the extending direction of the bit line BL (the width direction of the word line WL).
Is longer than the dimension of the bit line BL in the width direction (the extending direction of the word line), so that the contact area between the storage electrode 8a of the capacitor C and the plug P is reduced. Even if there is some misalignment between them, it is possible to sufficiently secure them. Therefore, it is possible to increase the alignment margin between the connection hole STC for the capacitor and the plug P.

(9) According to the above (8), it is possible to easily form the connection hole STC for the capacitor without increasing the chip size or reducing the degree of integration.

(10). The planar shape of the capacitor connection hole STC is such that the dimension in the direction in which the bit line BL extends (the width direction of the word line WL) is greater in the width direction of the bit line BL (extension of the word line WL). In this case, it is possible to improve the processing margin of the connection hole STC for the capacitor.

(11) According to the above (10), it is possible to prevent a defective opening of the connection hole STC for the capacitor. Therefore, the yield and reliability of the DRAM can be improved.

(12) According to the above (10), it is not always necessary to introduce a sophisticated and expensive exposure technique using a phase shift mask in order to satisfactorily open the connection hole STC for the capacitor. Therefore, the development period of the DRAM can be reduced. Further, cost reduction of the DRAM can be promoted.

(13). When the connection hole PC for the plug and the connection hole BLC for the bit line are formed, the etching process is performed separately to insulate the isolation region S exposed from the connection holes PC and BLC. It is possible to prevent a problem that the film 2b is removed by etching. Therefore,
It is possible to improve the operational reliability of the DRAM.

(14) According to the above (13), the alignment margin of the connection hole PC for the plug and the connection hole BLC for the bit line can be increased, so that the chip size can be increased and the degree of integration can be reduced. Even if it is not reduced, it is possible to easily form the connection hole PC for the plug and the connection hole BLC for the bit line.

(Embodiment 2) FIG. 44 is a plan view of a main part of a semiconductor integrated circuit device according to another embodiment of the present invention.
5A is a cross-sectional view taken along the line XXXXV-XXXXV in FIG.
FIG. 46B is a sectional view of a principal part in a peripheral circuit region of a semiconductor integrated circuit device according to another embodiment of the present invention, and FIG.
FIG. 47 is a cross-sectional view taken along line XXXVI-XXXVI of FIG.
FIGS. 48 to 56 are cross-sectional views taken along the line VII-XXXXVII. FIGS.

In the second embodiment, FIGS.
As shown in FIG. 7, the structure does not include the plug P described in the first embodiment (see FIGS. 1 and 8).

That is, in the second embodiment, the storage electrode 8a of the capacitor C is connected to the connection hole S for the capacitor.
The semiconductor region 3db of the selection MOSFET Q through the TC
And is electrically connected to the device.
Otherwise, the structure is the same as that of the first embodiment.

Therefore, the same effects as in the first embodiment can be obtained in the second embodiment.

In particular, in the second embodiment, the connection hole STC for the capacitor is formed by the selection MOS.
Is formed so that the semiconductor region 3da is directly exposed, so that the alignment is performed between multiple layers.

Therefore, in the case of the technique in which the shape of the connection hole is circular, alignment is difficult, and the exposed area of the semiconductor region 3da of the selection MOS • FET Q becomes small due to misalignment. 8a may not be able to secure a sufficient contact area.

However, in the second embodiment, similar to the first embodiment, the planar shape of the connection hole STC for the capacitor is formed so that the width direction of the word line WL becomes longer. , The alignment margin can be increased, and the connection hole STC for the capacitor can be formed.
Can be easily formed.

For example, FIG. 48 shows a technique studied by the inventor, in which the connection hole 52 for a capacitor described in the first embodiment is a technique of a circular shape, and its position and the position of the active region D. Shows a case in which is relatively shifted.

In the case of this technique, as shown by fine hatching, the semiconductor region of the selection MOS • FET Q exposed from the connection hole 52 for the capacitor becomes very small.

On the other hand, FIG. 49 shows the case of the second embodiment, in which the connection hole STC for the capacitor is well aligned with another layer. The semiconductor region of the selection MOS • FET Q exposed from the capacitor connection hole STC is hatched.

FIG. 50 shows a connection hole S for a capacitor.
49 shows a case where TC has shifted as in FIG. In the second embodiment, the planar shape of the connection hole STC for the capacitor is made longer in the width direction of the word line WL, so that it can be understood from the comparison with FIG. It is possible to sufficiently secure the exposed area of the semiconductor region of the selection MOSFET Q exposed from the connection hole STC.

Next, a method of manufacturing the semiconductor integrated circuit device according to the second embodiment will be described with reference to FIGS. In the second embodiment, since the steps up to the steps described with reference to FIGS. 11 to 22 in the method of manufacturing the semiconductor integrated circuit device according to the first embodiment are the same, the description thereof will be omitted, and the following steps will be described. .

First, as shown in FIG. 51, bit line connection holes BLC are formed in insulating film 6 and interlayer insulating films 7a to 7d.
Is perforated in the same manner as in the first embodiment.

Subsequently, as shown in FIG. 52, a conductor film B made of, for example, low-resistance polysilicon is formed on the semiconductor substrate 1.
L1 and BL2 are sequentially deposited from the lower layer by a CVD method or the like.

Thereafter, the conductor films BL1 and BL2 are patterned by photolithography and dry etching as shown in FIG. 53 to form bit lines BL, and then the interlayer insulating film is formed in the same manner as in the first embodiment. Films 7f and 7g are deposited.

Next, after the upper surface of the interlayer insulating film 7g is formed flat, an interlayer insulating film 7h made of silicon nitride or the like and an insulating film 14 made of SiO ₂ or the like are formed thereon as in the first embodiment. It is deposited in order from.

Subsequently, after a pattern of the conductor film 15 serving as a mask pattern is formed on the upper surface of the insulating film 14 in the same manner as in the first embodiment, a conductor film 16 is formed so as to cover the pattern.

Thereafter, the conductive film 16 is etched back, so that the side wall 1 is formed on the side surface of the opening of the conductive film 15.
After the formation of 6a, using the conductor film 15 and the side walls 16a as an etching mask, a connection hole STC for a capacitor is formed in the same manner as in the first embodiment.

Therefore, also in the second embodiment,
As shown in FIG. 55, even if the position of the capacitor connection hole STC is displaced upward in FIG. 55 with respect to the active region S, the insulation of the isolation region S exposed from the connection hole STC is prevented. The film is left less removed.

In FIG. 55, in order to make the drawing easy to see, the isolation region S exposed from the capacitor connection hole STC is hatched.

Next, a conductor film made of, for example, low-resistance polysilicon is deposited on the semiconductor substrate 1 by a CVD method or the like, and SiO ₂ is deposited on the upper surface in the same manner as in the first embodiment.
Is formed and patterned by photolithography and dry etching.

Subsequently, as in the first embodiment, a conductor film made of, for example, low-resistance polysilicon is deposited on the semiconductor substrate 1 and is etched back.
As shown in FIG. 56, the side wall 8a4 of the storage electrode 8a of the capacitor is formed.

After that, the insulating film on the storage electrode 8a of the capacitor and the underlying insulating film 14 (see FIG. 54) are removed by wet etching. Also in the second embodiment, since the base of the insulating film 14 is flat, the thickness of the insulating film 14 is uniform, and the insulating film 14 and the like can be uniformly removed by etching. Subsequent steps are the same as those in the first embodiment, and a description thereof will be omitted.

As described above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist thereof. Needless to say,

For example, as shown in FIGS. 57 and 58,
The plug P is extended in the width direction of the word line WL in the same manner as the extension direction of the connection hole STC for the capacitor, so that the word line WL
May be formed in a substantially rectangular shape so as to cover the upper part of the frame. In this case, it is possible to increase the allowable dimension when the connection hole STC for the capacitor is shifted in the width direction of the word line WL (the horizontal direction in FIG. 57).

In the case of drilling a connection hole for a bit line, a conductive film mask made of low-resistance polysilicon or the like is used similarly to the case of forming a connection hole for a capacitor.
It may be a part of the bit line.

In Embodiments 1 and 2,
The case where the film made of silicon nitride for forming the connection hole in a self-aligned manner is also provided on the flat surface of the semiconductor substrate has been described. However, the present invention is not limited thereto. May be provided with an insulating film made of silicon nitride and not provided on the flat surface of the semiconductor substrate.

In this case, an insulating film made of silicon nitride is deposited on a semiconductor substrate so as to cover a word line provided with a cap insulating film made of silicon nitride on the upper portion, and then this is etched back. Sidewalls made of silicon nitride are formed on side surfaces of the word lines and the cap insulating film.

In Embodiments 1 and 2,
Although the case where the isolation region has the groove-shaped buried structure has been described, the invention is not limited to this, and various modifications can be made. For example, a field insulating film may be used.

Further, in the first and second embodiments,
Although the case where the insulating film is embedded in the isolation groove of the isolation region has been described, for example, a structure in which polysilicon or the like is embedded in the isolation groove may be adopted.

In Embodiments 1 and 2,
A capacitor is arranged above the bit line, so-called C
The case where the present invention is applied to the DRAM having the OB structure has been described. However, the present invention is not limited to this, and the present invention is also applicable to a structure in which a capacitor is arranged below a bit line.

In the above description, the invention made mainly by the inventor has been described in terms of the DRA which is the application field in the background.
Although the description has been given of the case where the present invention is applied to M, the present invention is not limited to this. For example, the present invention can be applied to a semiconductor integrated circuit device technology such as a DRAM with logic provided by providing a DRAM and a logic circuit on the same substrate.

[0267]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the method of manufacturing a semiconductor integrated circuit device of the present invention, the shape of the connection hole is made longer in the direction intersecting the wirings adjacent to each other. Even if it is shifted, it is possible to ensure a sufficient contact area at the bottom.

(2) According to the above (1), the contact area between the conductor embedded in the connection hole and the semiconductor substrate can be increased, so that the electrical connection between the conductor and the semiconductor substrate can be improved. It becomes possible to make it good. Therefore, the performance and operation reliability of the semiconductor integrated circuit device can be improved.

(3) If the present invention is applied to a connection hole for a capacitor of a DRAM, for example, the contact area between the capacitor and the semiconductor region of the selection MOS / FET can be increased by the above (1). Reading and writing can be performed favorably, and the operating margin of the DRAM can be increased. Therefore, it is possible to improve the performance and operation reliability of the DRAM.

(4) According to the method of manufacturing a semiconductor integrated circuit device of the present invention, the area of the connection hole is increased by extending the shape of the connection hole in a direction intersecting the wirings adjacent to each other. Therefore, the processing margin of the connection hole can be improved. For this reason, the processing of the connection hole can be facilitated, and it is possible to prevent a defective opening of the connection hole. Therefore, it is possible to improve the yield of the semiconductor integrated circuit device.

(5) According to the method of manufacturing a semiconductor integrated circuit device of the present invention, the area of the connection hole is increased by extending the shape of the connection hole in the direction intersecting the wirings adjacent to each other. Therefore, the processing margin of the connection hole can be improved. For this reason, the connection hole can be formed without introducing a sophisticated and expensive photolithography technique such as a phase shift technique. Therefore, the development period of the semiconductor integrated circuit device can be shortened. Further, cost reduction of the semiconductor integrated circuit device can be promoted.

[Brief description of the drawings]

FIG. 1 is a plan view of a main part in a memory area of a semiconductor integrated circuit device according to an embodiment of the present invention;

FIG. 2 is a plan view of a main part in a memory area of the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 3 is a plan view of a main part of the memory area for describing misalignment of a pattern in the memory area of the semiconductor integrated circuit device of FIGS. 1 and 2;

FIG. 4 is a plan view of a main part of the memory area for describing misalignment of a pattern in the memory area of the semiconductor integrated circuit device of FIGS. 1 and 2;

FIG. 5 is a plan view of a memory area for explaining misalignment of a pattern in the memory area studied by the inventor;

FIG. 6 is a plan view of a memory area for explaining misalignment of a pattern in the memory area studied by the inventor;

FIG. 7 is a plan view of a main portion of a memory area for comparing the case of the semiconductor integrated circuit device of FIG. 1 with a technique studied by the present inventors.

8A is a sectional view taken along line VIII-VIII in FIG.
FIG. 2B is a cross-sectional view of a main part of a peripheral circuit region in the semiconductor integrated circuit device according to the present embodiment.

FIG. 9 is a sectional view taken along line IX-IX in FIG. 1;

FIG. 10 is a sectional view taken along line XX of FIG. 1;

11 is an explanatory diagram of the method for manufacturing the semiconductor integrated circuit device in FIG.

12 is an explanatory diagram of the method for manufacturing the semiconductor integrated circuit device in FIG.

13 is an explanatory diagram of the method for manufacturing the semiconductor integrated circuit device in FIG.

14 is an explanatory diagram of the method for manufacturing the semiconductor integrated circuit device in FIG.

15 is an explanatory diagram of the method for manufacturing the semiconductor integrated circuit device in FIG.

16 is an explanatory diagram of the method for manufacturing the semiconductor integrated circuit device in FIG.

17 is an explanatory diagram of the method for manufacturing the semiconductor integrated circuit device in FIG.

18 is an explanatory diagram of the method for manufacturing the semiconductor integrated circuit device in FIG.

19 is an explanatory diagram of the method for manufacturing the semiconductor integrated circuit device in FIG.

20 is an explanatory diagram of the method for manufacturing the semiconductor integrated circuit device in FIG.

21 is an explanatory diagram of the method for manufacturing the semiconductor integrated circuit device in FIG.

FIG. 22 is an explanatory diagram of the method for manufacturing the semiconductor integrated circuit device in FIG.

23 is an explanatory diagram of the method for manufacturing the semiconductor integrated circuit device in FIG.

24 is an explanatory diagram of the method for manufacturing the semiconductor integrated circuit device in FIG.

25 is an explanatory diagram of the method for manufacturing the semiconductor integrated circuit device in FIG.

26 is an explanatory diagram of the method for manufacturing the semiconductor integrated circuit device in FIG.

FIG. 27 is a cross-sectional view of a semiconductor integrated circuit device during a manufacturing step in a technique studied by the present inventors.

28 is an explanatory diagram of the method for manufacturing the semiconductor integrated circuit device in FIG.

FIG. 29 is an illustrative diagram of the method for manufacturing the semiconductor integrated circuit device in FIG. 1;

30 is an explanatory diagram of the method for manufacturing the semiconductor integrated circuit device in FIG.

FIG. 31 is an explanatory diagram of the method for manufacturing the semiconductor integrated circuit device in FIG.

FIG. 32 is an illustrative diagram of the method for manufacturing the semiconductor integrated circuit device in FIG. 1;

FIG. 33 is an explanatory diagram of the method for manufacturing the semiconductor integrated circuit device in FIG. 1.

FIG. 34 is an explanatory diagram of the method for manufacturing the semiconductor integrated circuit device in FIG.

FIG. 35 is an illustrative diagram of the method for manufacturing the semiconductor integrated circuit device in FIG. 1;

FIG. 36 is an illustrative diagram of the method for manufacturing the semiconductor integrated circuit device in FIG. 1;

FIG. 37 is an illustrative diagram of the method for manufacturing the semiconductor integrated circuit device in FIG. 1;

FIG. 38 is an explanatory diagram of the method for manufacturing the semiconductor integrated circuit device in FIG.

FIG. 39 is an illustrative diagram of the method for manufacturing the semiconductor integrated circuit device in FIG. 1;

FIG. 40 is an explanatory diagram of the method for manufacturing the semiconductor integrated circuit device in FIG. 1.

FIG. 41 is an explanatory diagram of the manufacturing method of the semiconductor integrated circuit device in FIG. 1;

FIG. 42 is an explanatory diagram of the method for manufacturing the semiconductor integrated circuit device in FIG.

FIG. 43 is an explanatory diagram of the method for manufacturing the semiconductor integrated circuit device in FIG.

FIG. 44 is a plan view of relevant parts of a semiconductor integrated circuit device according to another embodiment of the present invention;

45A is a sectional view taken along line XXXXV-XXXXV in FIG. 44, and FIG. 45B is a sectional view of a principal part in a peripheral circuit region of a semiconductor integrated circuit device according to another embodiment of the present invention; .

FIG. 46 is a sectional view taken along the line XXXVI-XXXVI of FIG. 44;

FIG. 47 is a cross-sectional view taken along the line XXXXVII-XXXXVII of FIG. 44.

FIG. 48 is a plan view of a semiconductor integrated circuit device of a technique studied by the present inventors.

FIG. 49 is an explanatory diagram of the method for manufacturing the semiconductor integrated circuit device in FIG. 44.

50 is an explanatory diagram of the method for manufacturing the semiconductor integrated circuit device in FIG. 44.

FIG. 51 is an explanatory diagram of the method for manufacturing the semiconductor integrated circuit device in FIG. 44.

FIG. 52 is an explanatory diagram of the method for manufacturing the semiconductor integrated circuit device in FIG. 44.

FIG. 53 is an explanatory diagram of the method for manufacturing the semiconductor integrated circuit device in FIG. 44.

FIG. 54 is an explanatory diagram of the method for manufacturing the semiconductor integrated circuit device in FIG. 44.

FIG. 55 is an explanatory diagram of the method for manufacturing the semiconductor integrated circuit device in FIG. 44.

56 is an explanatory diagram of the method for manufacturing the semiconductor integrated circuit device in FIG. 44.

FIG. 57 is a plan view of relevant parts of a semiconductor integrated circuit device according to another embodiment of the present invention;

FIG. 58 is a sectional view taken along line AA of FIG. 57;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2a Separation groove 2b Insulating film 3da, 3db, 3db1,3db2 Semiconductor region 3i Gate insulating film 3g Gate electrode 3g1,3g2 Conductive film 4 Insulating film 5 Cap insulating film 6 Insulating film 6a Side wall 7a-7k Interlayer insulating film 8a Storage electrode 8a1 Shaft 8a2 Bottom 8a3 Bottom side wall 8a4 Side wall 8b Plate electrode 9da, 9db Semiconductor region 9da1, 9db1 Low impurity concentration region 9da2, 9db2 High impurity concentration region 9i Gate insulating film 9g Gate electrode 9g1, 9g Film 10a Side wall 11L1 First layer wiring 12 Connection hole 13a to 13d Photoresist pattern 14 Insulating film 15 Conductive film 16 Conductive film 16a Side wall D Active region DW Deep n well Wpm, Wpp p well CS Channel stopper S Separation region WL word Line MC memory cell Q selection MOS • FET Qn n-channel type MOS • FET SA self-aligned pattern P plug PC plug connection hole for BL bit line BLC connection hole for bit line C capacitor STC connection hole for capacitor

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shunichi Hashimoto 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo In the Semiconductor Division, Hitachi, Ltd. (72) Inventor Norio Hasegawa Kamisuihoncho, Kodaira-shi, Tokyo Gochome No. 20, No. 1 Semiconductor Division, Hitachi, Ltd.

Claims (29)

[Claims] (A) forming a plurality of wirings on a semiconductor substrate; (b) covering the surfaces of the plurality of wirings with a nitride film; and (c) forming a semiconductor after the nitride film covering step. Depositing an insulating film made of a material different from the nitride film on the substrate; and (d) in the insulating film, in a region between adjacent ones of the plurality of wirings,
When drilling a connection hole that exposes a part of the semiconductor substrate, the connection hole is formed in a self-aligned manner by performing an etching process in a state where an etching selectivity between the insulating film and the nitride film is increased. And a step of piercing the
(E) The planar shape of the connection hole is formed so that the length in the direction intersecting with the adjacent wiring is longer than the length in the extending direction of the adjacent wiring. A method for manufacturing a semiconductor integrated circuit device. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein a length / short dimension ratio in a plane dimension of said connection hole is larger than 1. (A) depositing a conductor film and a first nitride film for forming a wiring on a semiconductor substrate in that order from a lower layer, and patterning the conductor film and the first nitride film to form a first nitride film on the upper portion; Forming a plurality of wirings provided with a cap film made of one nitride film; and (b) depositing a second nitride film on the semiconductor substrate after the wiring forming step, thereby forming a plurality of wirings. Covering the side surface, the surface of the cap film, and the flat surface on the semiconductor substrate with a second nitride film; and (c) forming the first nitride film on the semiconductor substrate after the step of covering the second nitride film. Depositing an insulating film made of a material different from the above, and (d) in the insulating film, in a region between adjacent ones of the plurality of wirings,
By performing an etching process in a state where the etching selectivity between the insulating film and the first nitride film and the second nitride film is increased in order to form a connection hole that exposes a part of the semiconductor substrate. When the connection holes are formed in a self-aligned manner, the etching process is performed under such a condition that the etching rate of the insulating film is faster than the etching rates of the first nitride film and the second nitride film. After exposing the second nitride film on the flat surface of the semiconductor substrate, the etching rates of the first nitride film and the second nitride film are higher than the etching rate of the insulating film. Performing an etching process under such conditions to form the connection holes in a self-aligned manner. , Said each other The method of manufacturing a semiconductor integrated circuit device, which comprises forming into a shape longer than the extending length of the wire adjacent to. 4. A step of: (a) forming a separation groove in a semiconductor substrate, and then forming a groove-shaped buried separation region in the semiconductor substrate by burying a separation film in the separation groove; After a conductor film and a first nitride film for forming a wiring are sequentially deposited from a lower layer on a semiconductor substrate, the conductor film and the first nitride film are patterned to form a cap film made of a first nitride film on an upper portion. Forming a plurality of wirings provided with: (c) depositing a second nitride film on the semiconductor substrate after the wiring forming step, thereby forming a side surface of the plurality of wirings, a surface of a cap film, and a semiconductor; And (d) an insulating film made of a material different from the first nitride film on the semiconductor substrate after the step of coating the second nitride film. Depositing (e) In the edge film, etching selection of the insulating film and the nitride film is performed so as to form a connection hole exposing a part of the semiconductor substrate in a region between adjacent ones of the plurality of wirings. When the connection hole is formed in a self-aligned manner by performing an etching process in a state where the ratio is increased, the etching rate of the insulating film is higher than the etching rate of the first nitride film and the second nitride film. After performing an etching process under a condition that the speed is higher than the speed, and exposing the second nitride film on the flat surface of the semiconductor substrate, the etching speed of the first nitride film and the second nitride film is increased. Performing an etching process under conditions such that the etching speed is higher than the etching rate of the insulating film, and drilling the connection holes in a self-aligned manner. That the direction of the length crossing the wires, a method of manufacturing a semiconductor integrated circuit device, characterized in that the forming into a shape longer than the extending length of the adjacent wires to each other. 5. A plurality of word lines forming a gate electrode of a memory cell selection MIS • FET formed on a semiconductor substrate, and a plurality of word lines extending above the word lines so as to be orthogonal to the extending direction of the word lines. A method of manufacturing a semiconductor integrated circuit device having a DRAM provided with
Forming the plurality of word lines on a semiconductor substrate;
(B) a step of covering the surfaces of the plurality of word lines with a nitride film; and (c) depositing an insulating film made of a material different from the nitride film on the semiconductor substrate after the nitride film covering step. (D) forming a connection hole between the word lines adjacent to each other in the insulating film such that a part of the semiconductor region of the memory cell selection MIS • FET is exposed; By performing the etching process in a state where the etching selectivity with respect to the contact hole is increased, the connection hole is formed in a self-aligned manner, and the plane shape of the connection hole has a length in a direction crossing the word line. Forming the semiconductor device into a shape that is longer than the length of the word line in the extending direction. 6. The method for manufacturing a semiconductor integrated circuit device according to claim 5, wherein said connection hole is a capacitor connection hole for electrically connecting a capacitor of a memory cell and a semiconductor region of a memory cell selection MIS • FET. A method of manufacturing a semiconductor integrated circuit device. 7. The method of manufacturing a semiconductor integrated circuit device according to claim 5, wherein said connection hole electrically connects each of said plurality of bit lines to a semiconductor region of a memory cell selection MIS • FET. A method for manufacturing a semiconductor integrated circuit device, characterized in that the connection hole is for use in a semiconductor integrated circuit device. 8. The method of manufacturing a semiconductor integrated circuit device according to claim 5, wherein said connection hole comprises: (a) a memory cell capacitor and a memory cell selection MIS.
A connection hole for a capacitor for electrically connecting the semiconductor region of the FET to a semiconductor region; and (b) a memory cell selection MI for each of the plurality of bit lines.
A method for manufacturing a semiconductor integrated circuit device, comprising: a connection hole for a bit line for electrically connecting an S • FET to a semiconductor region. 9. A step of: (a) forming a plurality of first wirings on a semiconductor substrate; (b) covering a surface of each of the plurality of first wirings with a nitride film; Depositing a first insulating film made of a material different from the nitride film on the semiconductor substrate after the film covering process;
Forming a plurality of second wirings extending in a direction intersecting with a direction in which the plurality of first wirings extend on the insulating film, and (e) forming a same material on the first insulating film as the second wiring. By depositing a second insulating film made of
(F) in the first insulating film and the second insulating film, in a region between the first wirings adjacent to each other and between the second wirings adjacent to each other;
When drilling a connection hole that exposes a part of the semiconductor substrate, performing an etching process in a state where an etching selectivity between the first insulating film and the second insulating film and the nitride film is increased. Drilling the connection holes in a self-aligned manner, and (g) changing the planar shape of the connection holes in the direction intersecting the first wirings adjacent to each other so as to be adjacent to each other. A method of manufacturing a semiconductor integrated circuit device, wherein the first wiring is formed in a shape longer than a length of the first wiring in an extending direction. 10. The method of manufacturing a semiconductor integrated circuit device according to claim 9, wherein:
A method of manufacturing a semiconductor integrated circuit device, wherein a short dimension ratio is larger than 1. 11. A step of: (a) forming a plurality of first wirings on a semiconductor substrate; (b) covering a surface of each of the plurality of first wirings with a nitride film; Depositing a first insulating film made of a material different from the nitride film on the semiconductor substrate after the film covering step; and (d) forming a region between the first wirings adjacent to each other in the first insulating film. In the case where a connection hole for a plug such that a part of the semiconductor substrate is exposed is formed, an etching process is performed in a state where an etching selectivity between the first insulating film and the nitride film is increased. Forming a connection hole for the plug in a self-aligned manner, (e) embedding a conductor film for the plug in the connection hole for the plug, and (f) forming a conductive film on the first insulating film. Depositing a second insulating film made of the same material as the first insulating film; (G) covering the second insulating film with a plurality of second wirings extending in a direction intersecting the extending direction of the plurality of first wirings. (H) depositing a third insulating film made of the same material as the second insulating film on the second insulating film, thereby covering the plurality of second wirings; In the second insulating film and the third insulating film, a connection hole such that a part of the conductive film for the plug is exposed is formed in a region between the second wirings adjacent to each other. A hole is formed by etching in a state where the etching selectivity between the film and the third insulating film and the nitride film is increased, and the plane shape of the connection hole intersects with the first wiring adjacent to each other. Direction length of the first wiring adjacent to each other The method of manufacturing a semiconductor integrated circuit device characterized by a step of forming into a shape longer than the length of the extending direction. 12. (a) After a conductor film for forming a wiring and a first nitride film are sequentially deposited from a lower layer on a semiconductor substrate, the conductor film and the first nitride film are patterned to form a first film on the upper portion. Forming a plurality of wirings provided with a cap film made of one nitride film; and (b) depositing a second nitride film on the semiconductor substrate after the wiring forming step, thereby forming a plurality of wirings. Covering the side surface, the surface of the cap film, and the flat surface on the semiconductor substrate with a second nitride film; and (c) forming the first nitride film on the semiconductor substrate after the step of covering the second nitride film. (D) depositing a first insulating film made of a material different from the first insulating film; and (d) forming a plurality of first insulating films on the first insulating film in a direction intersecting an extending direction of the plurality of first wirings. Forming a second wiring;
(E) depositing a second insulating film made of the same material as the first insulating film on the first insulating film to cover the plurality of second wirings; and (f) depositing the second insulating film on the first insulating film. In the second insulating film, a connection hole is formed in a region between the first wirings adjacent to each other and between the second wirings adjacent to each other so that a part of the semiconductor substrate is exposed. When the connection hole is formed in a self-aligned manner by performing an etching process while increasing an etching selectivity between the first insulating film and the second insulating film and the nitride film, An etching process is performed under such a condition that the etching rates of the insulating film and the second insulating film are faster than the etching rates of the first nitride film and the second nitride film. After exposing the second nitride film Performing an etching process under such a condition that the etching rates of the first nitride film and the second nitride film are faster than the etching rates of the first insulating film and the second insulating film; The hole is formed in a self-aligned manner, and the plane shape of the connection hole is set so that the length in the direction intersecting the first wiring adjacent to each other is equal to the length in the extending direction of the first wiring adjacent to each other. Forming the semiconductor integrated circuit device into a shape longer than the length. 13. A step of: (a) forming a separation groove in a semiconductor substrate and then forming a groove-shaped buried separation region in the semiconductor substrate by burying a separation film in the separation groove;
(B) After a conductor film and a first nitride film for wiring formation are sequentially deposited from the lower layer on the semiconductor substrate, the conductor film and the first nitride film are patterned to form a first nitride film on the upper portion. (C) depositing a second nitride film on the semiconductor substrate after the wiring formation step, thereby forming a plurality of wirings provided with a cap film comprising: Covering the surface of the semiconductor substrate and the flat surface on the semiconductor substrate with a second nitride film;
(D) depositing a first insulating film made of a material different from that of the first nitride film on the semiconductor substrate after the second nitride film covering process; and (e) forming the first insulating film. Forming a plurality of second wirings extending in a direction intersecting the extending direction of the plurality of first wirings on the film; and (f) forming the same material on the first insulating film as the first wirings Depositing a second insulating film to cover the plurality of second wirings; and (g) between the first wirings adjacent to each other in the first insulating film and the second insulating film. Yes, and
In the region between the second wirings adjacent to each other, the first hole is formed so as to expose a connection hole such that a part of the semiconductor substrate is exposed.
When the connection hole is formed in a self-aligned manner by performing an etching process in a state where the etching selectivity between the insulating film, the second insulating film, and the nitride film is increased, the first insulating film and Etching is performed under such a condition that the etching rate of the second insulating film is higher than the etching rate of the first nitride film and the second nitride film, and the second insulating film is formed on the flat surface of the semiconductor substrate. After exposing the nitride film, the conditions are such that the etching rates of the first nitride film and the second nitride film are faster than the etching rates of the first insulating film and the second insulating film. The connection hole is formed in a self-aligned manner, and the plane shape of the connection hole is changed so that the length in the direction intersecting the first wiring adjacent to each other is equal to the length of the adjacent first wiring. Arrangement of 1 The method of manufacturing a semiconductor integrated circuit device characterized by a step of forming the extending direction of the shape is longer than the length. 14. A plurality of word lines forming a gate electrode of a memory cell selection MIS • FET formed on a semiconductor substrate, and a plurality of word lines extending above the word lines so as to be orthogonal to the extending direction of the word lines. DRAM with bit lines
A method for manufacturing a semiconductor integrated circuit device having
(A) forming the plurality of word lines on a semiconductor substrate; (b) covering the surfaces of the plurality of word lines with a nitride film; and (c) on the semiconductor substrate after the nitride film covering step. Depositing a first insulating film made of a material different from the nitride film, (d) forming the plurality of bit lines on the first insulating film, and (e) forming the first insulating film.
Covering the plurality of bit lines by depositing a second insulating film made of the same material as the second insulating film on the insulating film, and (f) in the first insulating film and the second insulating film, The memory cell selection MIS • F is between word lines adjacent to each other and between bit lines adjacent to each other.
When drilling a connection hole for a capacitor such that the semiconductor region of ET is exposed, an etching process is performed in a state where the etching selectivity between the first insulating film and the second insulating film and the nitride film is increased. Accordingly, the connection hole for the capacitor is formed in a self-aligned manner, and the plane shape of the connection hole is such that the length in the direction crossing the word line is longer than the length in the extending direction of the word line. A method for manufacturing a semiconductor integrated circuit device, comprising: forming a semiconductor integrated circuit device into a shape that is also long. 15. A plurality of word lines forming a gate electrode of a memory cell selection MIS • FET formed on a semiconductor substrate, and a plurality of word lines extending above the word lines so as to be orthogonal to the extending direction of the word lines. DRAM with bit lines
A method for manufacturing a semiconductor integrated circuit device having
(A) forming the plurality of word lines on a semiconductor substrate; (b) covering the surfaces of the plurality of word lines with a nitride film; and (c) on the semiconductor substrate after the nitride film covering step. Depositing a first insulating film made of a material different from the nitride film; and (d) forming a semiconductor of the memory cell selection MIS • FET between word lines adjacent to each other in the first insulating film. When drilling a connection hole for a bit line such that a part of the region is exposed, by performing an etching process in a state where an etching selectivity between the first insulating film and the nitride film is increased, The connection hole for the bit line is formed in a self-aligned manner, and the length of the connection hole in the direction crossing the word line is longer than the length of the word line in the extending direction. To form (E) forming the plurality of bit lines on the first insulating film after the formation of the connection holes for the bit lines; and (f) forming the same material on the first insulating film. (G) covering the plurality of bit lines by depositing a second insulating film made of: (g) between the word lines adjacent to each other in the first insulating film and the second insulating film; In the case where a connection hole for a capacitor is formed between adjacent bit lines so that a semiconductor region of the memory cell selection MIS • FET is exposed, the first insulating film and the second insulating film are By performing an etching process in a state where the etching selectivity with respect to the nitride film is increased, the connection hole for the capacitor is formed in a self-aligned manner, and its planar shape is elongated in a direction intersecting the word line. Saga, The method of manufacturing a semiconductor integrated circuit device characterized by a step of forming into a shape longer than the extending length of the serial word line. 16. A plurality of word lines forming a gate electrode of a memory cell selection MIS • FET formed on a semiconductor substrate, and a plurality of word lines extending above the word lines so as to be orthogonal to the extending direction of the word lines. DRAM with bit lines
A method for manufacturing a semiconductor integrated circuit device having
(A) forming the plurality of word lines on the semiconductor substrate; (b) covering the surfaces of the plurality of word lines with a first nitride film; and (c) after the nitride film covering step. Depositing a first insulating film made of a material different from the first nitride film on the semiconductor substrate, and (d) forming the plurality of bit lines on the first insulating film. (E) depositing a second insulating film made of the same material as the first insulating film on the first insulating film to cover the plurality of bit lines; and (f) forming a second insulating film on the first insulating film. (G) depositing a second nitride film on the flattened second insulating film;
(H) depositing a third insulating film made of the same material as the first insulating film on the second nitride film; and (i) depositing a third insulating film, a second insulating film, Third insulating film and second insulating film
Between the adjacent word lines in the nitride film of
In the case where a connection hole for a capacitor is formed between adjacent bit lines so that a semiconductor region of the memory cell selection MIS • FET is exposed, the first insulating film and the first nitride film are formed. The etching process is performed in a state where the etching selectivity of the capacitor is increased, so that the connection hole for the capacitor is formed in a self-aligned manner, and the plane shape of the connection hole is made longer in the direction intersecting the word line. Forming a shape longer than the length of the word line in the extending direction, and (j) storing the capacitor on the third insulating film after forming the connection hole for the capacitor. Forming an electrode; and (k) after forming the storage electrode of the capacitor, removing the third insulating film by etching using the second nitride film as an etching stopper. The method of manufacturing a semiconductor integrated circuit device according to claim. 17. A plurality of word lines constituting a gate electrode of a memory cell selection MIS • FET formed on a semiconductor substrate, and a plurality of word lines extending above the word lines so as to be orthogonal to the extending direction of the word lines. DRAM with bit lines
A method for manufacturing a semiconductor integrated circuit device having
(A) forming the plurality of word lines on a semiconductor substrate; (b) covering the surfaces of the plurality of word lines with a nitride film; and (c) on the semiconductor substrate after the nitride film covering step. Depositing a first insulating film made of a material different from the nitride film, and (d) forming a part of the semiconductor substrate in a region between the word lines adjacent to each other in the first insulating film. When the connection hole for the plug is exposed so as to be exposed, an etching process is performed in a state where the etching selectivity between the first insulating film and the nitride film is increased, so that the connection hole for the plug is formed by itself. (E) embedding a conductive film for a plug in the connection hole for the plug; and (f) forming a conductive film on the first insulating film.
Depositing a second insulating film of the same material as the first insulating film to cover the conductor film for the plug; and (g) forming the plurality of bit lines on the second insulating film. And (h) depositing a third insulating film made of the same material as the second insulating film on the second insulating film,
Covering the plurality of bit lines; and (i) forming the second
In the insulating film and the third insulating film, a connection hole for a capacitor such that a part of the conductor film for the plug is exposed is formed in a region between the bit lines adjacent to each other. Drilling is performed by performing an etching process in a state where the etching selectivity with respect to the nitride film is increased, and the plane shape of the connection hole is set so that the length in the direction intersecting the word line is equal to the extension of the word line. Forming the semiconductor integrated circuit device into a shape longer than the existing direction. 18. A semiconductor device comprising: (a) a plurality of wirings provided on a semiconductor substrate; (b) a nitride film covering surfaces of the plurality of wirings; and (c) a material different from the nitride film, (D) an insulating film deposited on the semiconductor substrate so as to cover the nitride film and the plurality of wirings; and (d) in the insulating film, a region between the adjacent wirings of the plurality of wirings. A connection hole formed so that a part of the substrate is exposed, and a connection hole formed in a self-aligned manner by an etching process in a state where an etching selectivity between the insulating film and the nitride film is increased. (E) the planar shape of the connection hole is such that the length in the direction intersecting with the mutually adjacent wiring is longer than the length in the extending direction of the mutually adjacent wiring. Semiconductor integrated circuit characterized by the following apparatus. 19. The semiconductor integrated circuit device according to claim 18, wherein a length / short dimension ratio in a planar dimension of said connection hole is larger than 1. 20. A plurality of word lines forming a gate electrode of a memory cell selection MIS • FET formed on a semiconductor substrate, and a plurality of word lines extending above the word lines so as to be orthogonal to the extending direction of the word lines. DRAM with bit lines
(A) a nitride film covering surfaces of the plurality of word lines, and (b) a nitride film made of a material different from the nitride film, covering the nitride film and the plurality of word lines. (C) in the insulating film, the memory cell selection MIS • FE is formed in a region between the adjacent word lines in the insulating film.
A connection hole drilled so that the semiconductor region of T is exposed, wherein the connection hole is formed in a self-aligned manner by an etching process in a state where an etching selectivity between the insulating film and the nitride film is increased. (D) the planar shape of the connection hole is such that the length in the direction intersecting with the word line is longer than the length in the extending direction of the word line. Semiconductor integrated circuit device. 21. The semiconductor integrated circuit device according to claim 20, wherein said connection hole is a connection hole for a capacitor for electrically connecting a capacitor of a memory cell and a semiconductor region of a memory cell selection MIS • FET. A semiconductor integrated circuit device characterized by the above-mentioned. 22. The semiconductor integrated circuit device according to claim 20, wherein said connection hole electrically connects each of said plurality of bit lines to a semiconductor region of a memory cell selection MIS • FET. A semiconductor integrated circuit device comprising a hole. 23. The semiconductor integrated circuit device according to claim 20, wherein said connection hole is: (a) a connection hole for a capacitor for electrically connecting a capacitor of a memory cell and a semiconductor region of a memory cell selection MIS • FET. (B) each of the plurality of bit lines and a memory cell selection MIS • FE
A semiconductor integrated circuit device, which is a connection hole for a bit line for electrically connecting a semiconductor region of T. 24. (a) a plurality of first wirings provided on a semiconductor substrate; (b) a nitride film covering surfaces of the plurality of first wirings; and (c) the nitride film. A first insulating film made of a different material and deposited on the semiconductor substrate so as to cover the nitride film and the plurality of first wirings;
(D) a plurality of second wirings formed on the first insulating film so as to extend in a direction intersecting an extending direction of the plurality of first wirings; A second insulating film made of the same material as the first insulating film and deposited on the first insulating film so as to cover the second wiring; and (f) the first insulating film and the second insulating film. A connection hole formed between the first wirings adjacent to each other, and in a region between the second wirings adjacent to each other, such that a part of the semiconductor substrate is exposed; A connection hole formed in a self-aligned manner by an etching process in a state where an etching selectivity between the first insulating film and the nitride film is increased; and (g) changing a planar shape of the connection hole to each other. The length in the direction intersecting the adjacent wiring is the direction in which the adjacent wiring extends The semiconductor integrated circuit device being characterized in that the longer becomes such a shape than the length of the. 25. The semiconductor integrated circuit device according to claim 24, wherein a length / short dimension ratio in a planar dimension of said connection hole is larger than 1. 26. A semiconductor device comprising: (a) a plurality of first wirings provided on a semiconductor substrate; (b) a nitride film covering surfaces of the plurality of first wirings; and (c) the nitride film. A first insulating film made of a different material and deposited on the semiconductor substrate so as to cover the nitride film and the plurality of first wirings;
(D) In the first insulating film, the first insulating films adjacent to each other
Etching process in a state where the etching selectivity between the first insulating film and the nitride film is increased in a connection hole formed so that a part of the semiconductor substrate is exposed in a region between the wirings. (E) a plug embedded in the plug connection hole, and (f) a plug made of the same material as the first insulating film. A second insulating film deposited on the first insulating film so as to cover an upper surface; and (g) intersecting the extending direction of the plurality of first wirings on the second insulating film. And (h) the second insulating film is made of the same material as the first insulating film, and covers the second wiring. A third insulating film deposited thereon, and (i) the first insulating film,
A connection hole formed so that a part of the plug is exposed in a region where a plug is formed in the insulating film and the third insulating film, wherein the etching selection between the first insulating film and the nitride film is performed. And (j) a length of a direction in which the plane shape of the connection hole intersects with the first wiring adjacent to each other is set to be equal to the length of the connection hole. A semiconductor integrated circuit device having a shape longer than a length of a first wiring adjacent to each other in an extending direction. 27. A plurality of word lines forming a gate electrode of a memory cell selection MIS • FET formed on a semiconductor substrate, and a plurality of word lines extending above the word lines so as to be orthogonal to the extending direction of the word lines. DRAM with bit lines
(A) a nitride film covering surfaces of the plurality of word lines, and (b) a nitride film made of a material different from the nitride film, covering the nitride film and the plurality of word lines. A first insulating film deposited on the semiconductor substrate, (c) the plurality of bit lines formed on the first insulating film, and (d) a first insulating film on the first insulating film. (E) in the first insulating film and the second insulating film, between the word lines adjacent to each other and adjacent to each other in the second insulating film deposited so as to cover the plurality of bit lines; A connection hole formed so that a semiconductor region of the memory cell selection MIS • FET is exposed in a region between the bit lines to be formed. Etching process with large etching selectivity A connection hole for a capacitor formed in a self-aligned manner, and (f) changing a plane shape of the connection hole for the capacitor so that a length in a direction crossing the word line is equal to an extension of the word line. A semiconductor integrated circuit device having a shape that is longer than the length in the direction of presence. 28. A plurality of word lines constituting a gate electrode of a memory cell selection MIS • FET formed on a semiconductor substrate, and a plurality of word lines extending above the word lines so as to be orthogonal to the extending direction of the word lines. DRAM with bit lines
(A) a nitride film covering surfaces of the plurality of word lines, and (b) a nitride film made of a material different from the nitride film, covering the nitride film and the plurality of word lines. And (c) a semiconductor region of the memory cell selection MIS • FET in a region between adjacent word lines in the first insulating film. A connection hole for a bit line which is formed so as to be exposed and which is formed in a self-aligned manner by an etching process in a state where an etching selectivity between the first insulating film and the nitride film is increased. When,
(D) the plurality of bit lines formed on the first insulating film and electrically connected to a semiconductor region of the memory cell selection MIS • FET through the bit line connection hole; A second insulating film deposited on the first insulating film so as to cover the plurality of bit lines; and (f) between the word lines adjacent to each other in the first insulating film and the second insulating film. A connection hole formed in a region between bit lines adjacent to each other so that a semiconductor region of the memory cell selection MIS • FET is exposed, wherein the first insulation film and the second insulation film are formed. And (g) a connection hole for the bit line and a connection for the capacitor, the holes being formed in a self-aligned manner by an etching process in a state where the etching selectivity between the film and the nitride film is increased. Hole shape A length in a direction intersecting the word lines, a semiconductor integrated circuit device being characterized in that the shape is longer than the extending direction of the length of the word line. 29. A plurality of word lines forming a gate electrode of a memory cell selection MIS • FET formed on a semiconductor substrate, and a plurality of word lines extending above the word lines so as to be orthogonal to the extending direction of the word lines. DRAM with bit lines
(A) a nitride film covering surfaces of the plurality of word lines, and (b) a nitride film made of a material different from the nitride film, covering the nitride film and the plurality of word lines. And (c) a semiconductor region of the memory cell selection MIS • FET in a region between adjacent word lines in the first insulating film. A connection hole drilled so as to be exposed, wherein the connection hole for the plug is formed in a self-aligned manner by etching in a state where an etching selectivity between the first insulating film and the nitride film is increased. ,
(D) a plug embedded in the plug connection hole, and (e) the same material as the first insulating film, deposited on the first insulating film so as to cover an upper surface of the plug. (F) covering the plurality of bit lines formed on the second insulating film, and (g) covering the plurality of bit lines on the second insulating film. And (h) in the first insulating film, the second insulating film, and the third insulating film, a portion of the plug is exposed in a region where the plug is formed. The first insulating film, the second insulating film, and the third insulating film in a self-aligned manner by an etching process in a state where an etching selectivity between the nitride film and the first insulating film is increased. And (i) a connection hole for the capacitor. The surface shape, length in a direction intersecting the word lines, a semiconductor integrated circuit device being characterized in that the shape is longer than the extending direction of the length of the word line.