JP2718756B2 - Semiconductor integrated circuit and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a semiconductor integrated circuit in which a conductive layer of a conductivity type opposite to that of a substrate is provided in a substrate for wiring connection, and manufacturing thereof. About the method.

(Prior Art) In a semiconductor integrated circuit, for example, a MOS type integrated circuit, a base conductive layer is formed on a part of the substrate surface in order to extract an electrode from a source or drain region of the MOS transistor. At the same time, a wiring conductive layer pattern made of the same material as the gate electrode may be formed so as to be connected to the base conductive layer. FIG. 8 shows a partial configuration of a conventional integrated circuit formed by such a process. FIG. 8 (a) is a plan view of the pattern, and FIG. 8 (b) is a cross-sectional view taken along the line AA 'in FIG. 8 (a). In the figure, 31 is a semiconductor substrate,
32 is an isolation insulating film, 33 is a source region of a MOS transistor, 34 is a drain region, 35 is a gate insulating film, 36
Is a gate electrode of the MOS transistor, 37 is a source region of another MOS transistor, and 38 is formed on the substrate surface between the source region 37 and the element isolation insulating film 32, and is provided for extracting an electrode from the source region 37. The underlying conductive layer 39, 39 is a contact hole opened in the gate insulating film 35, and 40 is a wiring conductive layer connected to the underlying conductive layer 38 through the contact hole 39.

Here, the gate electrode 36 and the conductive layer 40 for wiring are made of the same electrode material, for example, a polycrystalline silicon layer, and an impurity such as phosphorus is introduced into the polycrystalline silicon layer to reduce resistance. ing.

Next, a conventional manufacturing method for manufacturing such an integrated circuit will be described. First, after opening the contact hole 39,
A polycrystalline silicon layer is deposited over the entire surface of the substrate, and phosphorus is diffused into the polycrystalline silicon layer to simultaneously form a base conductive layer. Next, selective etching for patterning the polycrystalline silicon layer is performed. At this time, in order to prevent the element isolation insulating film 32 and the gate insulating film 35 from being etched, an etching process is performed so that the polycrystalline silicon layer and the insulating film have a selectivity. Thereafter, source and drain regions of each MOS transistor including the source region 33, 37 and the drain region 34 are formed by performing ion implantation using the patterned gate electrode 36 and conductive layer 40 for wiring as a mask. .

By the way, when the underlying conductive layer 38 is formed by diffusing phosphorus into the polycrystalline silicon layer, if the depth of the diffusion layer is small, the underlying conductive layer 38 is less likely to spread in the lateral direction, and There is a possibility that the source region 37 will not come into contact with 38. For this reason, conventionally, diffusion is performed so that the diffusion layer of the underlying conductive layer 38 is formed deep, and conduction with the source region 37 is ensured by the accompanying lateral diffusion.

However, in the case where the width of the isolation insulating film 32 is reduced due to the miniaturization of the element, if the diffusion is performed so as to increase the junction depth of the underlying conductive layer 38, the following problem occurs. That is, as shown in the cross-sectional view of FIG. 9, a state occurs in which the underlying conductive layer 38 contacts the source region 33 of the MOS transistor on the opposite side beyond the region of the element isolation insulating film 32 having a small width.

(Problems to be Solved by the Invention) The present invention is to increase the bonding depth of the base conductive layer in order to make the base conductive layer formed on a part of the substrate surface conductive with another conductive layer around the base conductive layer. The purpose of the present invention is to solve the problem that high integration becomes difficult, and the purpose is to increase the junction depth of the underlying conductive layer even with other conductive layers separated by the element isolation insulating film. An object of the present invention is to provide a semiconductor integrated circuit which can be made non-conductive and is suitable for high integration and a method for manufacturing the same.

[Structure of the Invention] (Means for Solving the Problems) A semiconductor integrated circuit according to the present invention includes a semiconductor substrate, an element isolation insulating film selectively formed on the surface of the substrate, and a semiconductor integrated circuit formed on the surface of the substrate. A gate insulating film, a first opening formed in the gate insulating film at a position adjacent to the element isolating insulating film, and formed in the substrate located below the first opening. A first conductive layer of a conductivity type opposite to that of the substrate, a wiring layer connected to the first conductive layer through the first opening, and an insulating film for element isolation with respect to the first conductive layer. A second conductive layer formed in the substrate at an interval and opposite in conductivity to the substrate, and formed in a position in contact with the element isolation insulating film in the first opening;
The first conductive layer is separated into two parts by penetrating the conductive layer, and a second opening formed so that the bottom thereof reaches the substrate.

Further, the method for manufacturing a semiconductor integrated circuit according to the present invention includes a step of selectively forming an element isolation insulating film on a surface of a semiconductor substrate; a step of forming a gate insulating film on the surface of the substrate; Forming a first opening in the gate insulating film at a position adjacent to the element isolation insulating film, and depositing a polycrystalline silicon layer over the entire surface;
Forming a first conductive layer by introducing an impurity of a conductivity type opposite to that of the substrate into the polycrystalline silicon layer and introducing the impurity into the substrate through the first opening; As a result, the polycrystalline silicon layer is left at least in and around the first opening and penetrates through the first conductive layer at a position in contact with the element isolation insulating film in the first opening and the bottom thereof is Forming a second opening so as to reach the substrate.

(Function) In the present invention, the first conductive layer is separated into two parts by penetrating the first conductive layer at a position in contact with the element isolation insulating film in the first opening, and the bottom is formed on the substrate. By providing the second opening reaching the first conductive layer, even if the first conductive layer and the second conductive layer are formed in contact with each other, the first conductive layer is formed by the second opening. Separated into two parts. As a result, the first conductive layer and the second conductive layer are separated from each other.

Hereinafter, the present invention will be described with reference to the drawings. 1 (a), (b) to 5 (a), (b)
3A and 3B are views showing a manufacturing process of the semiconductor integrated circuit according to the present invention, wherein each figure (a) is a plan view of a pattern and each figure (b) is a cross-sectional view taken along the line AA '.

First, as shown in FIG. 1, a P-type silicon semiconductor substrate
A 500 angstrom thick silicon oxide film (not shown) is formed on the substrate 11 by hydrogen combustion oxidation at 950 ° C, and a silicon nitride film (not shown) is further deposited thereon to a thickness of 1500 angstrom. I do. Next, the silicon nitride film on the area where the element isolation area is to be formed is selectively removed by photolithography using a chemical vapor isotropic etching technique. A 8000 angstrom silicon oxide film 12 for element isolation is formed on the surface. Thereafter, the remaining silicon nitride film is removed by a chemical vapor isotropic etching technique, and the silicon oxide film remaining on the region where the element is to be formed is removed using an NH ₄ F solution.

Next, as shown in FIG. 2, a 300 Å thick silicon oxide film 13 for a gate insulating film is formed on the surface of the substrate by a dry oxygen oxidation method at 900 ° C. Subsequently, the silicon oxide film 13 is selectively etched by a photolithography technique and an NH ₄ F solution, and a contact hole 14 is opened adjacent to the silicon oxide film 12 for element isolation.

Next, as shown in FIG. 3, a polycrystalline silicon layer 15 for wiring is formed on the substrate 11 by CVD (chemical vapor deposition).
Poc at 900 ° C
performing heat treatment for 40 minutes in an atmosphere of l ₃ by introducing phosphorus as an impurity in the polycrystalline silicon layer 15, a low resistance. At this time, at the same time, phosphorus is diffused from the polycrystalline silicon layer 15 in the contact hole 14 into the substrate 11 to form an N-type underlying conductive layer.
16 are formed.

Next, a photoresist film 17 is deposited and then patterned, and as shown in FIG. 4, the contact hole is partially overlapped with the element isolation silicon oxide film 12.
14 and on the periphery thereof, and also on the region where the gate electrode is to be formed.

Subsequently, as shown in FIG.
The polycrystalline silicon layer 15 is selectively etched by an anisotropic etching technique using as a mask, thereby forming a wiring conductive layer 18 and a gate electrode 19 made of the polycrystalline silicon layer 15. During this etching, over-etching is performed. During this over-etching, the silicon substrate 11
Since the selectivity between the silicon oxide film 13 and the silicon oxide film 13 is sufficiently large, for example, the etching rate between the silicon substrate 11 and the silicon oxide film 13 is about 1: 1/7,
The silicon oxide film 13 is hardly etched even after the polycrystalline silicon layer 15 is completely removed in a portion where the polycrystalline silicon layer 15 is present as a base film, while the polycrystalline silicon layer 15 is completely removed in a portion where the silicon oxide film 13 is not present. After the substrate 11
Is etched a lot. Therefore, after this over-etching, a silicon oxide film
An opening 20 is opened adjacent to 12, and the bottom of the opening 20 penetrates the N-type underlying conductive layer 16 and reaches the inside of the substrate 11. Subsequently, after the photoresist film 17 is removed, arsenic ions (As) are accelerated at an acceleration voltage of 60 keV and a dose of 5 × 10 ¹⁵ (atoms / cm ² ) using the conductive layer for wiring 18 and the gate electrode 19 as a mask. By implanting ions into the substrate and then activating, source and drain regions including the N-type source region 21, drain region 22 and drain or source region 23 are formed. At this time, an N-type diffusion region 24 is also formed at the bottom of the opening 20. Thereafter, an interlayer insulating film is formed by a well-known technique, flattened, a contact hole is opened, and a wiring is formed by performing sputtering and patterning of a metal wiring film.

In the integrated circuit manufactured as described above, the underlying conductive layer 16 connected to the wiring conductive layer 18 through the contact hole 14 is formed by the opening 20 such that the lower portion of the silicon oxide film 12 and the drain or source region 23 And the connected part is separated into two parts. For this reason, the width of the element isolation silicon oxide film 12 is reduced due to the miniaturization of the element, and even if the underlying conductive layer 16 is in contact with the source region 21, it is connected to the drain or source region 23 of the underlying conductive layer 16. Of the source and drain regions as in the prior art, the underlying conductive layer 16 and the source region 21 can be prevented.
Can also be kept low.

FIG. 6 is a circuit diagram of a measuring circuit for measuring a leak current in the semiconductor integrated circuit of the above embodiment, and FIG. 7 is a characteristic diagram showing the measurement result. The width (Y in the figure) of the silicon oxide film 12 for element isolation is set to 0.8 μm, and the width of the opening 20 (X in the figure: unit is μm) is set variously to form a base conductive film. The leakage current between the layer 16 and the source region 21 was measured. In FIG. 7, X = 0 μm is a conventional case in which the opening 20 is not provided, and when a very small voltage is applied to the wiring conductive layer 18, a large leak current flows. In contrast, it can be seen that the leak current decreases as the width X of the opening 20 increases.

[Effects of the Invention] As described above, according to the present invention, even if the junction depth of the underlying conductive layer is increased, it is possible to prevent conduction with other conductive layers separated by the element isolation insulating film. It is possible to provide a semiconductor integrated circuit suitable for high integration and a method for manufacturing the same.

[Brief description of the drawings]

FIGS. 1 (a) and (b) to FIGS. 5 (a) and (b) are diagrams showing a manufacturing process of a semiconductor integrated circuit according to the present invention. FIG. 6B is a sectional view, FIG. 6 is a circuit diagram of a measuring circuit for measuring a leak current in the semiconductor integrated circuit of the above embodiment, and FIG. 7 shows a measurement result using the measuring circuit of FIG. 8A and 8B show a partial configuration of a conventional integrated circuit. FIG. 8A is a pattern plan view, FIG. 8B is a sectional view, and FIG.
FIG. 1 is a sectional view of a conventional integrated circuit. 11 ... P-type silicon semiconductor substrate, 12 ... Silicon oxide film for element isolation, 13 ... Silicon oxide film for gate insulating film, 14 ... Contact hole, 15 ... Polycrystalline silicon layer, 16 ... Underlying conductive layer, 17 Photoresist film, 18
... conductive layer for wiring, 19 ... gate electrode, 20 ... opening, 21
... source region, 22 ... drain region, 23 ... drain or source region, 24 ... N-type diffusion region.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H01L 29/78

Claims (2)

(57) [Claims] A semiconductor substrate; an element isolation insulating film selectively formed on a surface of the substrate; a gate insulating film formed on a surface of the substrate; and a position adjacent to the element isolation insulating film. A first opening formed in the gate insulating film, a first conductive layer formed in the substrate located below the first opening and having a conductivity type opposite to that of the substrate, A wiring layer connected to the first conductive layer through an opening formed in the substrate; a conductive layer having a reverse conductivity type formed in the substrate at a position separated from the first conductive layer by the element isolation insulating film; A second conductive layer, formed at a position in contact with the element isolation insulating film in the first opening, penetrating the first conductive layer, and separating the first conductive layer into two portions; And a second opening having a bottom formed to reach the substrate. Semiconductor integrated circuit to be butterflies. A step of selectively forming an element isolation insulating film on the surface of the semiconductor substrate; a step of forming a gate insulating film on the surface of the substrate; and a step of selectively etching the element insulating film on the gate insulating film by a selective etching method. Forming a first opening at a position adjacent to the insulating film for use; forming a polycrystalline silicon layer on the entire surface; introducing impurities of a conductivity type opposite to that of the substrate into the polycrystalline silicon layer; A step of forming a first conductive layer by introducing the impurity into the substrate through the first opening, and leaving the polycrystalline silicon layer at least in and around the first opening by a selective etching method And forming a second opening through the first conductive layer at a position in contact with the element isolation insulating film in the first opening so that the bottom reaches the substrate. The method of manufacturing a semiconductor integrated circuit, characterized in that Bei was.