JPH03276755A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03276755A JPH03276755A JP7810490A JP7810490A JPH03276755A JP H03276755 A JPH03276755 A JP H03276755A JP 7810490 A JP7810490 A JP 7810490A JP 7810490 A JP7810490 A JP 7810490A JP H03276755 A JPH03276755 A JP H03276755A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- deposited
- metal
- tin
- barrier metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 3
- 229910052751 metal Inorganic materials 0.000 claims abstract description 21
- 239000002184 metal Substances 0.000 claims abstract description 21
- 230000004888 barrier function Effects 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 abstract description 10
- 238000001259 photo etching Methods 0.000 abstract description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract description 6
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 abstract description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052786 argon Inorganic materials 0.000 abstract description 2
- 229910001873 dinitrogen Inorganic materials 0.000 abstract description 2
- 229910018182 Al—Cu Inorganic materials 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- DYRBFMPPJATHRF-UHFFFAOYSA-N chromium silicon Chemical compound [Si].[Cr] DYRBFMPPJATHRF-UHFFFAOYSA-N 0.000 description 1
- QKJXFFMKZPQALO-UHFFFAOYSA-N chromium;iron;methane;silicon Chemical compound C.[Si].[Cr].[Fe] QKJXFFMKZPQALO-UHFFFAOYSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に抵抗の形成
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to the formation of a resistor.
従来、この種の抵抗は半導体基板に不純物イオンを注入
して形成する拡散抵抗又は半導体基板上にポリシリを堆
積し不純物イオンを注入して形成するポリシリ抵抗又は
半導体基板上に絶縁膜を堆積しさらにシリコンクロム、
窒化タンタルなどの金属を堆積し金属抵抗として使用す
るとなっていた。Conventionally, this type of resistor has been formed by either a diffused resistor formed by implanting impurity ions into a semiconductor substrate, a polysilicon resistor formed by depositing polysilicon on the semiconductor substrate and implanting impurity ions, or a resistor formed by depositing an insulating film on the semiconductor substrate. silicon chrome,
Metals such as tantalum nitride were to be deposited and used as metal resistors.
上述した従来の半導体装置の拡散およびポリシリ抵抗の
場合は、半導体基板又は半導体基板上にポリシリを堆積
し抵抗形成部のみに不純物イオンを注入するため単独の
形成工程を必要とし且つイオン注入量のバラツキにより
抵抗精度が悪いという欠点がある。In the case of the conventional diffusion and poly-silicon resistor of the semiconductor device described above, a single formation process is required because poly-silicon is deposited on the semiconductor substrate or on the semiconductor substrate and impurity ions are implanted only into the resistor forming portion, and the amount of ion implantation varies. This has the disadvantage of poor resistance accuracy.
同様に金属抵抗の場合も半導体基板上に絶縁物を堆積し
抵抗形成部のみにシリコンクロム、窒化タンタルなどの
金属を堆積し形成するために単独の形成工程を必要とす
る欠点がある。Similarly, in the case of metal resistors, there is a drawback in that an insulator is deposited on a semiconductor substrate and a metal such as silicon chromium or tantalum nitride is deposited and formed only on the resistor forming portion, so a single formation process is required.
本発明の半導体装置は、コンタクト部に形成するバリア
メタルを抵抗として使用している。The semiconductor device of the present invention uses a barrier metal formed in the contact portion as a resistor.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ） 、 （ｂ）は、本発明の一実施例を示す
工程順の縦断面図である。FIGS. 1(a) and 1(b) are vertical cross-sectional views showing the steps of an embodiment of the present invention.
第１図（ａ）に示すように、半導体基板１に絶縁膜２を
堆積しコンタクト部３上の前記絶縁膜２を除去し、さら
にＴｉＮなどのバリアメタル４を堆積する。この際Ｔｉ
Ｎはアルゴンおよび窒素ガス圧を制御し、シート抵抗を
１２０〜１４０Ω／口とし堆積する。As shown in FIG. 1(a), an insulating film 2 is deposited on a semiconductor substrate 1, the insulating film 2 on the contact portion 3 is removed, and a barrier metal 4 such as TiN is further deposited. At this time, Ti
N is deposited by controlling the argon and nitrogen gas pressures and setting the sheet resistance to 120 to 140 Ω/port.
次に第１図（ｂ）に示すようにバリアメタル４をホトエ
ツチングにより所定の抵抗形状に加工しＡ４又はＡ Ｉ
！ −Ｃｕなどの配線金属５を堆積しホトエツチングに
より加工し形成する。ここで、ＴｉＮのシート抵抗が精
度よく形成できるため高精度の抵抗を得ることができる
。Next, as shown in FIG. 1(b), the barrier metal 4 is processed into a predetermined resistance shape by photo-etching.
! - A wiring metal 5 such as Cu is deposited and processed by photoetching. Here, since the sheet resistance of TiN can be formed with high accuracy, a highly accurate resistance can be obtained.
第２図は、本発明の実施例２の縦断面図である。FIG. 2 is a longitudinal sectional view of Example 2 of the present invention.
半導体基板１は、実施例１の方法で形成された絶縁膜２
．第１層配線６と抵抗７を備えている。A semiconductor substrate 1 includes an insulating film 2 formed by the method of Example 1.
．． It includes a first layer wiring 6 and a resistor 7.
次にＳｉＮなどの層間絶縁膜８を堆積しホトエツチング
によりスルーホール９を設け、ＴｉＮなどのバリアメタ
ル１０を層間絶縁膜８とスルーホール９上に堆積する。Next, an interlayer insulating film 8 such as SiN is deposited and through holes 9 are formed by photoetching, and a barrier metal 10 such as TiN is deposited on the interlayer insulating film 8 and the through holes 9.
さらにホトエツチングにより抵抗１１とスルーホール９
部以外のバリアメタル１０を除去する。最後にＡｕなど
の第１層金属と異る第２層配線１２に堆積しホトエツチ
ングにより加工し所定のパターンを形成する。これによ
り抵抗７と抵抗１１は、スルーホール９にヨリ接続され
た並列抵抗となる。この実施例では並列抵抗を形成でき
るため上層の抵抗値を変更するだけで任意の抵抗値を得
られる利点がある。Furthermore, resistor 11 and through hole 9 are formed by photo-etching.
The barrier metal 10 other than the part is removed. Finally, it is deposited on the second layer wiring 12, which is different from the first layer metal such as Au, and processed by photoetching to form a predetermined pattern. As a result, the resistor 7 and the resistor 11 become parallel resistors connected to the through hole 9. This embodiment has the advantage that any resistance value can be obtained simply by changing the resistance value of the upper layer since parallel resistances can be formed.
以上説明したように本発明は、バリアメタルを抵抗とし
て使用することにより配線形成工程で抵抗を形成できる
効果がある。As explained above, the present invention has the advantage that the resistor can be formed in the wiring forming process by using the barrier metal as the resistor.
第１図（ａ） 、 （ｂ）は、本発明の一実施例を示す
工程順の抵抗素子の縦断面図、第２図は実施例２の縦断
面図である。
１・・・・・・半導体基板、２・・・・・・絶縁膜、３
・・・・・・コンタクト部、４・・・・・・バリアメタ
ル、訃・・・・・配線金属、６・・・・・・第１層配線
、７・・・・・・抵抗、８・・・・・・層間絶縁膜、９
・・・・・・スルーホール、１０・・・・・・バリアメ
タル、■
・・・・・抵抗、
■
２・・・・・・第２層配線。FIGS. 1(a) and 1(b) are longitudinal cross-sectional views of a resistance element in the order of steps showing one embodiment of the present invention, and FIG. 2 is a longitudinal cross-sectional view of a second embodiment. 1... Semiconductor substrate, 2... Insulating film, 3
...Contact part, 4...Barrier metal, Death...Wiring metal, 6...First layer wiring, 7...Resistance, 8・・・・・・Interlayer insulating film, 9
...Through hole, 10...Barrier metal, ■...Resistor, ■2...Second layer wiring.
Claims (1)
於いて前記バリアメタルを抵抗として使用することを含
むことを特徴とする半導体装置の製造方法。1. A method of manufacturing a semiconductor device, comprising using the barrier metal as a resistor in a semiconductor device in which a barrier metal is formed in a contact portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7810490A JPH03276755A (en) | 1990-03-27 | 1990-03-27 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7810490A JPH03276755A (en) | 1990-03-27 | 1990-03-27 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03276755A true JPH03276755A (en) | 1991-12-06 |
Family
ID=13652579
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7810490A Pending JPH03276755A (en) | 1990-03-27 | 1990-03-27 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03276755A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6466124B1 (en) | 1999-04-08 | 2002-10-15 | Nec Corporation | Thin film resistor and method for forming the same |
| US6696733B2 (en) | 1997-10-27 | 2004-02-24 | Seiko Epson Corporation | Semiconductor devices including electrode structure |
| DE102012207311B4 (en) * | 2011-07-25 | 2018-11-08 | Mitsubishi Electric Corporation | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE |
-
1990
- 1990-03-27 JP JP7810490A patent/JPH03276755A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6696733B2 (en) | 1997-10-27 | 2004-02-24 | Seiko Epson Corporation | Semiconductor devices including electrode structure |
| US6466124B1 (en) | 1999-04-08 | 2002-10-15 | Nec Corporation | Thin film resistor and method for forming the same |
| DE102012207311B4 (en) * | 2011-07-25 | 2018-11-08 | Mitsubishi Electric Corporation | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE |
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