JPH04359559A - Formation of resistance element - Google Patents

Abstract

PURPOSE:To reduce the relative errors of resistance elements by a method wherein the first resistance layer comprising a polycrystalline silicon layer with an insulating film provided on the surface thereof and the second resistance layer with the surface exposed are simultaneously implanted with impurity ions. CONSTITUTION:An insulating layer 2 is provided on a semiconductor substrate 1 and then polycrystalline silicon layer is deposited on the insulating layer 2 while this polycrystalline silicon layer is selectively etched away so as to form the first and second resistance layers 3a, 3b. Next, a silicon oxide film 4 is deposited on the surface including the resistance layers 3a, 3b and then the film 4 is selectively etched away to expose the resistance layer 3b. Next, boron ions are implanted in the surface using the silicon oxide film 4 as a mask so that the boron ions implanted in the resistance layer 3a by the silicon oxide film 4 may be controlled to adjust the layer resistance of the resistance layers 3a, 3b. Through these procedures, the relative errors of the resistance elements can be reduced.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a resistive element, and more particularly to a method of forming a resistive element of a semiconductor integrated circuit.

0002

[Prior Art] First resistor element of conventional semiconductor integrated circuit
As shown in FIGS. 3A and 3B, a polycrystalline silicon layer is deposited to a thickness of 0.3 μm on an insulating film 2 provided on a semiconductor substrate 1. Next, boron ions are implanted into the polycrystalline silicon layer at an acceleration energy of 50 keV and a dose of 5.0×10 14 cm −2 and heat treated. Next, the polycrystalline silicon layer is patterned using photolithography technology to form resistance layers 3d and 3e. Next, an interlayer insulating film 5 is deposited on the surface including the resistance layers 3a and 3b, and a contact hole 6 is provided by opening the interlayer insulating film 5 on the resistance layers 3d and 3e. 3e
An electrode 7 connected to each is provided.

[0003] Here, the layer resistance of the resistance layers 3d and 3e is set to 1k.
Ω/□, and the ratio of the length L to the width W of the resistance layer 3d (hereinafter L/
) is 1/6, and the L/W ratio of the resistance layer 3e is 5.5/
2, resistance value = (layer resistance) x L/W, resistance layer 3
d resistance R1 = 167Ω, resistance layer 3e resistance R2 = 2
．． It becomes 75KΩ.

[0004] In this way, in order to obtain different resistance values in resistance layers with the same layer resistance, it is necessary to change the L/W ratio of the resistance layer. It is known that when the L/W ratio differs by one order of magnitude or more, dimensional accuracy deteriorates due to manufacturing variations, and resistance value fluctuates due to heat treatment or stress. To solve this problem, there is a method of forming resistance layers having different layer resistances.

FIGS. 4A to 4C are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a second method of forming a conventional resistance element.

As shown in FIG. 4(a), a polycrystalline silicon layer 3 is formed on an insulating film 2 provided on a semiconductor substrate 1 with a thickness of 0.3
Deposited to a thickness of μm, boron ions are deposited on the polycrystalline silicon layer 3 at an energy of 50 keV and a dose of 2×10 14
Ion implantation is performed at cm-2.

Next, as shown in FIG. 4(b), the polycrystalline silicon layer 3 is patterned by photolithography to form resistance layers 3a and 3b. Next, the resistance layer 3a
, 3b is coated with a photoresist film 8 and patterned to expose the resistive layer 3b. Next, boron ions are implanted using the photoresist film 8 as a mask.

Next, as shown in FIG. 4C, after removing the photoresist film 8, heat treatment is performed, and an interlayer insulating film 5 is deposited on the surface including the resistance layers 3a and 3b to form a contact hole 6. An electrode 7 is provided to connect to the resistance layers 3a, 3b of the contact hole 6.

As described above, by changing the layer resistances of the resistance layers 3a and 3b, it is possible to form resistance elements having greatly different resistance values without significantly changing the dimensions of the resistance layers.

0010

[Problem to be Solved by the Invention] In the conventional method of forming a resistor element, the dose of ions implanted to adjust the layer resistance of the resistor layer has no correlation between each resistor layer, so the relative error between resistors is large. There is a problem with that. In semiconductor integrated circuits, it is expected that a set of resistors will have a small relative error compared to the absolute error in resistor manufacturing, but if the layer resistance is determined only by the magnitude of the resistance value, this expectation will not be fulfilled. There is a problem.

[0011]

[Means for Solving the Problems] A method for forming a resistance element of the present invention includes depositing a polycrystalline silicon layer on a semiconductor substrate, selectively etching the polycrystalline silicon layer, and forming first and second resistance layers. a step of depositing an insulating film on the surface including the first and second resistance layers and selectively etching it to expose the second resistance layer; ions are implanted into the first and second
and introducing impurities at different concentrations into the resistance layer.

0012

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIGS. 1A to 1C are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a first embodiment of the present invention.

First, as shown in FIG. 1(a), an insulating film 2 is provided on a semiconductor substrate 1, and a polycrystalline silicon layer is deposited to a thickness of 0.3 μm on the insulating film 2 using a photolithography technique. selectively etching is performed to form first and second resistance layers 3a and 3b.

Next, as shown in FIG. 1(b), the resistive layer 3
A silicon oxide film 4 is deposited to a thickness of 0.3 μm on the surface including layers a and 3b and selectively etched to expose the resistive layer 3b. Next, using the silicon oxide film 4 as a mask, boron ions are accelerated at an energy of 50 keV and a dose of 5×10
Ions are implanted at a depth of 15 cm<-2>, and the boron ions implanted into the resistive layer 3a are controlled by the silicon oxide film 4 to adjust the layer resistance between the resistive layers 3a and 3b.

Next, as shown in FIG. 1C, the silicon oxide film 4 is etched and removed, and after heat treatment, an interlayer insulating film 5 is deposited on the surface including the resistance layers 3a and 3b. Next, contact holes 6 are formed by selectively opening the interlayer insulating film 5 on the resistance layers 3a and 3b, and a metal layer is deposited on the surface including the contact holes 6 and selectively etched. Electrodes 7 are formed to connect to the resistance layers 3a and 3b, respectively.

Here, the layer resistances of the resistance layers 3a and 3b are several kΩ/□ and several hundred kΩ/□, respectively, and even when forming resistance elements whose resistance values differ by more than one digit, L/□ is not much different.
It can be formed with a W ratio. Moreover, since the resistance value changes due to variations in ion implantation show the same tendency between the resistance layers 3a and 3b, it is possible to keep the relative error small.

FIGS. 2A to 2C are cross-sectional views of a semiconductor chip shown in order of steps for explaining a second embodiment of the present invention.

As shown in FIG. 2(a), a polycrystalline silicon layer 3 is deposited on an insulating film 2 provided on a semiconductor substrate 1, and a thick layer is selectively formed on the polycrystalline silicon layer 3. Sa0.3
A silicon oxide film 4a with a thickness of μm and a silicon oxide film 4b with a thickness of 0.2 μm are provided, respectively.

Next, as shown in FIG. 2B, boron ions are implanted into the polycrystalline silicon layer 3 using the silicon oxide films 4a, 4b as masks, and the silicon oxide films 4a, 4b are implanted into the polycrystalline silicon layer 3.
Boron ions are implanted at different doses into the polycrystalline silicon layer 3 in the portion where 4b is present and the portion where the surface is exposed. Next, after removing the silicon oxide films 4a, 4b, the polycrystalline silicon layer 3 is selectively etched to form resistance layers 3a, 3b, 3c.

Next, as shown in FIG. 2(c), the resistive layer 3
A contact hole 6 is provided by forming an interlayer insulating film 5 on the surface including layers a, 3b, and 3c, and the resistance layer 3a, 3b of the contact hole is
, 3c are formed.

[0022]

Effects of the Invention As explained above, the present invention simultaneously ions impurities into each of a first resistance layer made of a polycrystalline silicon layer and having an insulating film on its surface, and a second resistance layer whose surface is exposed. By increasing the conductivity of the first and second resistive layers through injection, it is possible to correlate changes in the layer resistance of the first resistive layer and the second resistive layer, thereby reducing the relative error of the resistive element. It has the effect of being able to be made smaller.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a semiconductor chip shown in the order of steps for explaining a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of a semiconductor chip shown in the order of steps for explaining a second embodiment of the present invention.

FIG. 3 is a plan view and a cross-sectional view taken along line A-A' of a semiconductor chip showing a first example of a conventional resistance element.

FIG. 4 is a cross-sectional view of a semiconductor chip shown in order of steps for explaining a second example of a conventional resistance element.

[Explanation of symbols]

1 Semiconductor substrate 2 Insulating film 3 Polycrystalline silicon layers 3a, 3b, 3c Resistance layers 4, 4a, 4b Silicon oxide film 5 Interlayer insulating film 6 Contact hole 7 Electrode 8 Photoresist film

Claims (1)

[Claims] 1. A step of depositing a polycrystalline silicon layer on a semiconductor substrate and selectively etching the polycrystalline silicon layer to form first and second resistance layers; depositing an insulating film on the surface including the layer and selectively etching it to expose the second resistive layer; implanting impurity ions using the insulating film as a mask;
and introducing impurities of different concentrations into the second resistance layer.