JPH02199865A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH02199865A
JPH02199865A JP1910489A JP1910489A JPH02199865A JP H02199865 A JPH02199865 A JP H02199865A JP 1910489 A JP1910489 A JP 1910489A JP 1910489 A JP1910489 A JP 1910489A JP H02199865 A JPH02199865 A JP H02199865A
Authority
JP
Japan
Prior art keywords
film
polycrystalline silicon
silicon film
insulating film
value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1910489A
Other languages
Japanese (ja)
Inventor
Tomonori Sawano
沢野 知紀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1910489A priority Critical patent/JPH02199865A/en
Publication of JPH02199865A publication Critical patent/JPH02199865A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To correct a resistance value formed off a design value to a value close to the design value in a posterior process by a method wherein, after impurity ions have been implanted into a polycrystalline silicon film, the polycrystalline silicon film is etched when a measured resistance value is lower than the design value and the ions are implanted again when the value is higher. CONSTITUTION:An oxide film 2 is formed on a semiconductor substrate 1; a polycrystalline silicon film 3 is deposited on it; after that, this film is patterned. Then, impurities are introduced into the silicon film 3; after that, a first interlayer insulating film 4 such as a silicon dioxide film or the like is deposited. A resistance value of the silicon film 3 is measured in a state that opening parts 5 have been formed in the insulating film 4 on both end parts of the silicon film 3. When the resistance value is off a design value toward a smaller value, a photoresist is formed on the whole surface; the photoresist at an upper layer in the central part of the silicon film 3 is removed; after that, the insulating film 4 at the upper layer of the silicon film 3 and the surface of the silicon film 3 are removed partly. Then, the photoresist 6 is removed; after that, a second interlayer insulating film 7 is deposited; a contact hole 8 is formed in the insulating film 7; a prescribed connection is executed by using a wiring part 9; this device is completed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特に多結晶シリ
コン抵抗の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a polycrystalline silicon resistor.

〔従来の技術〕[Conventional technology]

従来、この種の多結晶シリコン抵抗は、第3図に示すよ
うに半導体基板1表面に形成された酸化膜2上に多結晶
シリコンを堆積し、抵抗形成領域以外の多結晶シリコン
をエツチング除去した後、たとえばイオン注入法により
多結晶シリコン膜3に不純物を導入する。続いて全面を
シリコン酸化膜あるいはシリコン窒化膜等の第1の層間
絶縁膜で覆い、多結晶シリコン膜3の両端の配線取付部
に開口部を設けた後、第2の層間絶縁膜7を上層に形成
し、開口部にコンタクト孔を設け、アルミニウム等の配
線9をパターニング形成する。このようにして所定の抵
抗値の多結晶シリコン抵抗が実現されると共に配線9と
の良好なコンタクトが得られる。
Conventionally, this type of polycrystalline silicon resistor was produced by depositing polycrystalline silicon on an oxide film 2 formed on the surface of a semiconductor substrate 1, as shown in FIG. Thereafter, impurities are introduced into the polycrystalline silicon film 3 by, for example, ion implantation. Next, the entire surface is covered with a first interlayer insulating film such as a silicon oxide film or a silicon nitride film, and openings are provided at both ends of the polycrystalline silicon film 3 for wiring attachment parts, and then a second interlayer insulating film 7 is formed as an upper layer. A contact hole is provided in the opening, and a wiring 9 made of aluminum or the like is patterned. In this way, a polycrystalline silicon resistor having a predetermined resistance value is realized and good contact with the wiring 9 is obtained.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の多結晶シリコン抵抗の製造方法では、多
結晶シリコン膜の形成工程における膜厚のバラツキ、多
結晶シリコン膜のパターニング工程における長さ1幅の
寸法のバラツキ、さらにはパターニングされた多結晶シ
リコン膜へのイオン注入工程における不純物濃度のバラ
ツキ等、抵抗値が設計値から外れてしまう要因が数多く
存在していた。しかしながら、従来の一連の製造方法に
おいては、設計値を外れた抵抗値を補正する手段を有し
ていなかった。そのため、回路設計時に想定された電気
的特性等が十分得られない欠点があった。
In the conventional manufacturing method of polycrystalline silicon resistors described above, variations in film thickness in the process of forming the polycrystalline silicon film, variations in length and width in the patterning process of the polycrystalline silicon film, and even variations in the length and width of the patterned polycrystalline silicon film occur. There are many factors that cause the resistance value to deviate from the designed value, such as variations in impurity concentration during the ion implantation process into the silicon film. However, in a series of conventional manufacturing methods, there was no means for correcting a resistance value that deviated from a designed value. Therefore, there was a drawback that the electrical characteristics etc. that were assumed at the time of circuit design could not be obtained sufficiently.

〔目的〕〔the purpose〕

本発明の目的は、製造工程中に設計値を外れて形成され
た抵抗の値を後工程で、設計値近傍へ補正できる半導体
装置の製造方法を提供するものである。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device in which the value of a resistor formed outside the design value during the manufacturing process can be corrected to be close to the design value in a subsequent process.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の多結晶シリコン抵抗の製造方法は、半導体基板
上に多結晶シリコンを堆積し、パターニングする工程と
、パターニングされた多結晶シリコン膜に不純物を導入
する工程と、全面に第1の絶縁膜を形成する工程と、多
結晶シリコン膜の所定の領域上の第1の絶縁膜に開口部
を形成し、多結晶シリコン膜を露出する工程と、開口部
を介して多結晶シリコン膜の抵抗値を測定する工程と、
多結晶シリコン膜上の少なくとも一部が除去されたフォ
トレジスト膜を形成する工程と、測定された抵抗値が所
定値より小さい場合、フォトレジスト膜をマスクとして
第1の絶縁膜及び多結晶シリコン膜の一部を工、チング
除去し、測定された抵抗値が所定値より大きい場合、フ
ォトレジスト膜をマスクとして第1の絶縁膜をエツチン
グ除去し、多結晶シリコン膜を露出させ、不純物を導入
する工程と、フォトレジスト膜除去後全面に第2の絶縁
膜を形成する工程と、開口部上の第2の絶縁膜にコンタ
クト孔を設け、コンタクト孔を介して多結晶シリコン膜
と接続するように配線を形成する工程とを有している。
The method for manufacturing a polycrystalline silicon resistor of the present invention includes a step of depositing polycrystalline silicon on a semiconductor substrate and patterning it, a step of introducing impurities into the patterned polycrystalline silicon film, and a step of depositing a first insulating film on the entire surface. forming an opening in the first insulating film on a predetermined region of the polycrystalline silicon film to expose the polycrystalline silicon film; and forming a resistance value of the polycrystalline silicon film through the opening. a step of measuring
A step of forming a photoresist film from which at least a portion of the polycrystalline silicon film is removed, and if the measured resistance value is smaller than a predetermined value, the photoresist film is used as a mask to form a first insulating film and the polycrystalline silicon film. If the measured resistance value is larger than a predetermined value, the first insulating film is removed by etching using the photoresist film as a mask to expose the polycrystalline silicon film and introduce impurities. a step of forming a second insulating film on the entire surface after removing the photoresist film, and forming a contact hole in the second insulating film over the opening so that it is connected to the polycrystalline silicon film through the contact hole. and a step of forming wiring.

そのため、本発明では多結晶シリコン膜への不純物の導
入により得られる抵抗値の設計値からのバラツキを後の
工程で補正することができる。
Therefore, in the present invention, variations in the resistance value from the designed value obtained by introducing impurities into the polycrystalline silicon film can be corrected in a later process.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図(a)〜(d)は本発明の第1の実施例の工程断
面図である。半導体基板1上に酸化−2が形成され、そ
の上に多結晶シリコン膜3を堆積した後パターニングす
る。次に多結晶シリコン膜3に不純物を、たとえばイオ
ン注入により導入した後、シリコン酸化膜等の第1の層
間絶縁膜4を堆積する。第1図(a)のように多結晶シ
リコン膜3の両端部上の第1の層間絶縁膜4に開口部5
を形成した状態で多結晶シリコン膜3の抵抗値を測定す
る。
FIGS. 1(a) to 1(d) are process cross-sectional views of a first embodiment of the present invention. Oxide-2 is formed on a semiconductor substrate 1, and a polycrystalline silicon film 3 is deposited thereon and then patterned. Next, after impurities are introduced into the polycrystalline silicon film 3 by, for example, ion implantation, a first interlayer insulating film 4 such as a silicon oxide film is deposited. As shown in FIG. 1(a), openings 5 are formed in the first interlayer insulating film 4 on both ends of the polycrystalline silicon film 3.
The resistance value of the polycrystalline silicon film 3 is measured in the state in which the polycrystalline silicon film 3 is formed.

抵抗値が設計値より小さい方に外れている場合には、フ
ォトレジスト6を全面に形成し、第1図(b)のように
多結晶シリコン膜3中央部上層のフォトレジストを除去
するようにパターニングした後、これをマスクとして多
結晶シリコン膜3上層の絶縁膜4及び多結晶シリコン膜
3表面を一部除去する。次に第1図(c)に示すように
フォトレジスト6を除去後、第2の層間絶縁膜7を堆積
し、配線取付用のコンタクト孔8を開口部5上層の第2
の層間絶縁膜7に形成し、アルミニウム等の配線9によ
り所定の接続を行ない、第1図(d)の構成を得る。こ
のようにして、多結晶シリコン抵抗の製造工程中に抵抗
値の測定を行ない、その結果に応じて多結晶シリコン抵
抗の一部をエッチング除去することにより多結晶シリコ
ン膜の断面積を小さくし、抵抗値を高くするように制御
することができる。
If the resistance value deviates from the designed value, a photoresist 6 is formed on the entire surface, and the photoresist at the upper center of the polycrystalline silicon film 3 is removed as shown in FIG. 1(b). After patterning, using this as a mask, the insulating film 4 on the upper layer of the polycrystalline silicon film 3 and the surface of the polycrystalline silicon film 3 are partially removed. Next, as shown in FIG. 1(c), after removing the photoresist 6, a second interlayer insulating film 7 is deposited, and a contact hole 8 for wiring is formed in the second layer above the opening 5.
The structure shown in FIG. 1(d) is obtained by forming an interlayer insulating film 7 and making predetermined connections using wiring 9 made of aluminum or the like. In this way, the resistance value is measured during the manufacturing process of the polycrystalline silicon resistor, and depending on the result, a part of the polycrystalline silicon resistor is etched away to reduce the cross-sectional area of the polycrystalline silicon film. The resistance value can be controlled to be high.

本実施例では多結晶シリコン膜による抵抗値が設計値よ
り小さく形成された場合の補正方法を示したため、多結
晶シリコン膜の一部をエツチング除去することにより、
断面積を小さくした。しかし、実際には抵抗値のバラツ
キの方向は不定であるので、抵抗値が設計値より大きく
形成された場合には、第1図(b)に示すようにフォト
レジスト6をパターニングした後、第1の層間絶縁膜4
のみエツチング除去し、多結晶シリコン膜4を露出させ
、再び不純物をイオン注入する。こうして多結晶シリコ
ン膜4中の不純物濃度を高くし、抵抗値を小さくするこ
とが可能となる。以後第1図(C)、 (d)の工程に
従う。
This example shows a correction method when the resistance value due to the polycrystalline silicon film is formed smaller than the design value. Therefore, by etching away a part of the polycrystalline silicon film,
Reduced cross-sectional area. However, in reality, the direction of the variation in resistance value is uncertain, so if the resistance value is larger than the designed value, after patterning the photoresist 6 as shown in FIG. 1(b), 1 interlayer insulating film 4
After removing the polycrystalline silicon film 4 by etching, the polycrystalline silicon film 4 is exposed, and impurity ions are implanted again. In this way, it is possible to increase the impurity concentration in the polycrystalline silicon film 4 and reduce the resistance value. Thereafter, the steps shown in FIGS. 1(C) and 1(d) are followed.

また、本実施例では、フォトレジスト6をマスクにした
多結晶シリコン膜3のエツチングあるいは露出工程にお
いて、多結晶シリコン膜3の中央部付近をエツチング、
露出したが、これに限定されるものではない。
Further, in this embodiment, in the etching or exposing process of the polycrystalline silicon film 3 using the photoresist 6 as a mask, the vicinity of the center of the polycrystalline silicon film 3 is etched,
Exposed, but not limited to.

第2図は本発明の第2の実施例の縦断面図である。アル
ミニウム等の配線9が多結晶シリコン膜3上部に延在し
て形成されている。そのため、第3図に示した従来例に
比べ多結晶シリコン膜3と配線9との距離が小さくなり
、多結晶シリコン膜と配線間の容量が大きくなる。これ
は例えばメモリセル内に使用する抵抗で耐α線容量を増
加させるために抵抗に容量が必要とされる場合に有効で
ある。
FIG. 2 is a longitudinal sectional view of a second embodiment of the invention. A wiring 9 made of aluminum or the like is formed extending over the polycrystalline silicon film 3 . Therefore, compared to the conventional example shown in FIG. 3, the distance between the polycrystalline silicon film 3 and the wiring 9 becomes smaller, and the capacitance between the polycrystalline silicon film and the wiring becomes larger. This is effective, for example, when a resistor used in a memory cell requires a capacitance in order to increase the alpha ray resistance capacity.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は多結晶シリコン膜への不純
物のイオン注入後、抵抗値を測定した設計値より低い場
合には、多結晶シリコン膜をエツチングし、高い場合に
は露出させ、再びイオン注入を行なうことにより、設計
値近傍の抵抗値を持った多結晶シリコン抵抗を実現でき
る。
As explained above, in the present invention, after impurity ion implantation into a polycrystalline silicon film, if the measured resistance value is lower than the designed value, the polycrystalline silicon film is etched, and if it is higher, it is exposed and ionized again. By performing implantation, a polycrystalline silicon resistor having a resistance value close to the design value can be realized.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(d)は本発明の第1の実施例の断面図
、第2図は第2の実施例の縦断面図、第3図は従来例の
断面図である。 1・・・・・・半導体基板、2・・・・・・酸化膜、3
・・・・・・多結晶シリコン膜、4・・・・・・第1の
層間絶縁膜(第1絶縁膜)、5・・・・・・開口部、6
・・・・・・フォトレジスト、7・・・・・・第2の層
間絶縁膜(第2絶縁膜)、8・・・・・・コンタクト孔
、9・・・・・・アルミニウム配線。 代理人 弁理士  内 原   晋 薔 l 図
1(a) to (d) are sectional views of a first embodiment of the present invention, FIG. 2 is a longitudinal sectional view of the second embodiment, and FIG. 3 is a sectional view of a conventional example. 1... Semiconductor substrate, 2... Oxide film, 3
...Polycrystalline silicon film, 4...First interlayer insulating film (first insulating film), 5...Opening, 6
... Photoresist, 7 ... Second interlayer insulating film (second insulating film), 8 ... Contact hole, 9 ... Aluminum wiring. Agent: Patent Attorney Shinsuke Uchihara

Claims (1)

【特許請求の範囲】 1、半導体基板上に多結晶シリコンを堆積し、パターニ
ングする工程と、該パターニングされた多結晶シリコン
膜に不純物を導入する工程と、全面に第1の絶縁膜を形
成する工程と、前記多結晶シリコン膜の所定の領域上の
該第1の絶縁膜に開口部を形成し、前記多結晶シリコン
膜を露出する工程と、前記多結晶シリコン膜上の少なく
とも一部が除去されたフォトレジスト膜を形成する工程
と、該フォトレジスト膜をマスクとし前記第1の絶縁膜
及び前記多結晶シリコン膜の一部をエッチング除去する
工程と、前記フォトレジスト膜除去後、全面に第2の絶
縁膜を形成する工程と、前記開口部上の該第2の絶縁膜
にコンタクト孔を設け、該コンタクト孔を介して前記多
結晶シリコン膜と接続するように配線を形成する工程と
を有することを特徴とする半導体装置の製造方法。 2、前記フォトレジスト膜をマスクとし、前記第1の絶
縁膜及び前記多結晶シリコン膜の一部をエッチング除去
する工程に代わり、前記フォトレジスト膜をマスクとし
、前記第1の絶縁膜をエッチング除去し、前記多結晶シ
リコン膜を露出させる工程と、該多結晶シリコン膜に不
純物を導入する工程とを有することを特徴とする特許請
求の範囲第1項記載の半導体装置の製造方法。
[Claims] 1. Depositing and patterning polycrystalline silicon on a semiconductor substrate, introducing impurities into the patterned polycrystalline silicon film, and forming a first insulating film on the entire surface. forming an opening in the first insulating film on a predetermined region of the polycrystalline silicon film to expose the polycrystalline silicon film; and removing at least a portion on the polycrystalline silicon film. forming a photoresist film, using the photoresist film as a mask, etching away a portion of the first insulating film and the polycrystalline silicon film, and etching a photoresist film over the entire surface after removing the photoresist film. a step of forming a second insulating film over the opening, and a step of forming a contact hole in the second insulating film over the opening and forming a wiring to connect to the polycrystalline silicon film through the contact hole. A method for manufacturing a semiconductor device, comprising: 2. Using the photoresist film as a mask, instead of etching away part of the first insulating film and the polycrystalline silicon film, using the photoresist film as a mask, removing the first insulating film by etching. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the steps of exposing the polycrystalline silicon film and introducing impurities into the polycrystalline silicon film.
JP1910489A 1989-01-27 1989-01-27 Manufacture of semiconductor device Pending JPH02199865A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1910489A JPH02199865A (en) 1989-01-27 1989-01-27 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1910489A JPH02199865A (en) 1989-01-27 1989-01-27 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH02199865A true JPH02199865A (en) 1990-08-08

Family

ID=11990173

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1910489A Pending JPH02199865A (en) 1989-01-27 1989-01-27 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH02199865A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH098063A (en) * 1995-06-23 1997-01-10 Nec Corp Manufacture of semiconductor integrated device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH098063A (en) * 1995-06-23 1997-01-10 Nec Corp Manufacture of semiconductor integrated device

Similar Documents

Publication Publication Date Title
CA1085969A (en) Semiconductor devices and method of manufacturing the same
JP2519819B2 (en) Contact hole forming method
JPH06216125A (en) Method of forming contact hole of high integrity semiconductor device
JPH02199865A (en) Manufacture of semiconductor device
JPH03263330A (en) Semiconductor device
JPH10326864A (en) Manufacture of analog semiconductor device
JPH10163430A (en) Semiconductor device and manufacture thereof
KR0137850B1 (en) Forming method of semiconductor device
JP2901262B2 (en) Manufacturing method of polysilicon resistance element
JP3521061B2 (en) Method for manufacturing semiconductor device
EP0053484B1 (en) A method for fabricating semiconductor device
KR0134859B1 (en) Fabrication method of contact hole in semiconductor device
KR100253344B1 (en) Manufacturing method for contact hole of semiconductor memory
JPS63278256A (en) Semiconductor device and its manufacture
KR0147485B1 (en) Method of making a gate electrode for rom
JPS63202953A (en) Manufacture of semiconductor device
JPH04359559A (en) Formation of resistance element
JPH03165516A (en) Manufacture of semiconductor device
JPS63207180A (en) Semiconductor device
JPH0420256B2 (en)
JPS59130469A (en) Semiconductor device and manufacture thereof
JPS59964A (en) Manufacture of semiconductor device
JPH05198750A (en) Semiconductor device
JPH03132021A (en) Manufacture of semiconductor device
JPS58197853A (en) Manufacture of semiconductor device