JP3521061B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field programmable gate array (FPGA) semiconductor device in which a program can be written by a user.
The present invention relates to a method of manufacturing an antifuse structure of an FPGA having an antifuse structure.

[0002]

2. Description of the Related Art As an antifuse element of this type,
For example, US Pat. No. 5,351,810 and JP-A-6-850.
The structure described in Japanese Patent No. 68 has been proposed. Hereinafter, a general method of manufacturing such a conventional antifuse structure will be described.

First, as shown in FIG. 3B, a first insulating film 32 is deposited on the semiconductor substrate 31 shown in FIG. Next, as shown in FIG. 3C, a first metal film 33 serving as a lower electrode is deposited on the first insulating film 32, and then, as shown in FIG. An antifuse film 34 serving as an antifuse is formed on the first metal film 33.
Deposit. The antifuse film 34 has a lower layer, which is a silicon nitride layer 341, and an upper layer, which is an amorphous silicon film 3 formed by a CVD method using Ar and SiH ₄ as raw materials.
42 has a two-layer structure.

Next, as shown in FIG. 3E, after a resist 35 is applied on the antifuse film 34 to form a desired pattern, the first metal film 33 and the antifuse film 34 are etched. To do. After removing the resist 35, as shown in FIG. 3F, the first metal film (hereinafter,
A second insulating film 36 is deposited so as to cover the lower electrode 33 and the antifuse film 34. Next, FIG.
As shown in (g), a resist 37 is applied on the second insulating film 36 to form a window at a desired position, and then a contact hole 38 reaching the antifuse film is formed in the second insulating film 36. Open by dry etching. On the surface of the antifuse film 34 exposed by the dry etching of the contact hole 38, oxygen ions in the gas used for the dry etching are implanted into the antifuse film, so that an oxide layer 39 is formed on the surface. afterwards,
The resist 37 is removed, and as shown in FIG. 3H, a second metal film 40 to be an upper electrode is deposited on the second insulating film 36. Finally, as shown in FIG. 3I, a resist 41 is applied to form a desired pattern, and a second metal film (hereinafter referred to as an upper electrode) 40 is etched to complete an antifuse structure. .

As is apparent from the above description, the antifuse of this type of structure is characterized in that the antifuse film 34 is sandwiched between the upper electrode 40 and the lower electrode 33 through the contact hole 38. . Here, various dielectric materials have been studied as the material of the antifuse film 34, but the silicon nitride layer 3
41 or a silicon oxide film as a lower layer and an amorphous silicon film 342 as an upper layer, a two-layer structure is often used. It is easy to control and set the film thickness with respect to the set target program voltage required to apply a voltage to the upper electrode 40 and the lower electrode 33 and break the antifuse film 34 to make it conductive. Because.

Specifically, a voltage of up to about 10 V is applied stepwise in time to the antifuse portion, and the program is completed when a prescribed current flows due to the dielectric breakdown of the antifuse film 34. . When a current starts flowing due to dielectric breakdown, at the bottom end of the hole where the electric field is concentrated,
The metal forming the lower electrode 33, which is melted by Joule heat, migrates into the anti-fuse film to form a portion called a fuse link, which is electrically connected to the upper electrode 40 with low resistance.

[0007]

However, in the above-mentioned conventional structure, the uneven shape existing on the surface of the amorphous silicon is formed in the step of opening the contact hole connecting the anti-fuse film 34 and the upper electrode 40 by dry etching. Oxygen ions enter the film along with, so that the surface of the amorphous silicon film 342 forming the upper portion of the antifuse film 34 is unevenly oxidized, and the oxide film formed there is likely to be uneven.

If the oxide film at the end of the bottom surface of the contact is thick and the oxide film at the center of the bottom surface of the contact is thin locally, dielectric breakdown of amorphous silicon occurs from the end portion of the contact bottom surface where the electric field of the contact is concentrated. It won't always happen. That is, not only the end portions but also the portions of the non-uniform oxide film having a low withstand voltage will be destroyed. In such a state, the withstand voltage of the anti-fuse film 34 varies finally for each contact hole 38 within the wafer surface, and in some cases, exceeds the maximum applied voltage of about 10 V, or less than the program voltage. However, even if the voltage is low, it may be programmed, so that there is a problem that accurate programming cannot be performed.

An object of the present invention is to provide a method of manufacturing a semiconductor device that solves the problems of the prior art.

[0010]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises forming a first conductive layer on a substrate and then sequentially depositing an insulating layer and an amorphous silicon layer. Forming an antifuse film, forming an insulating film on the amorphous silicon layer, forming an etching mask having an opening pattern on the insulating film, and insulating the insulating film using the etching mask. A step of selectively removing the film to form an opening reaching the surface of the amorphous silicon layer; a step of removing the etching mask by oxygen plasma treatment; and a step of forming a second conductive film on the opening and the insulating film. and forming a layer, to form the amorphous silicon layer with He and SiH ₄ or N ₂ and the CVD method as a raw material of SiH _4, It is characterized in this way, the amorphous silicon layer He and SiH _4, or N ₂ and SiH ₄ by forming a CVD method using a raw material, compared with the conventional manufacturing method, the silicon layer The surface irregularities of are reduced to several nm, which allows the thickness of the surface oxide layer to be 3 nm or less.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a process cross-sectional view of a portion of a semiconductor device in which an antifuse is formed in Reference Example 1 for explaining an embodiment of the present invention. Figure 1 (a)
In FIG. 1, 11 is a semiconductor substrate.
As shown in, the first insulating film 12 is formed on the semiconductor substrate 11.
Deposit. The first insulating film 12 corresponds to an interlayer insulating film or a protective film formed on the transistors, wirings, and the like that form the internal circuit of the semiconductor device.

Next, as shown in FIG. 1C, a first metal film 13 to be a lower electrode is deposited on the first insulating film 12. Subsequently, as shown in FIG. 1D, an antifuse film 14 serving as an antifuse is formed on the first metal film 13.
Deposit. The anti-fuse film 14 is a two-layer film composed of a silicon nitride film 141 and an amorphous silicon film 142 deposited at a low temperature by plasma CVD or the like using Ar and SiH ₄ as source gases.

Next, as shown in FIG. 1E, a resist film 15 is applied on the antifuse film 14 to form a desired pattern, and then the resist 15 is used as an etching mask by dry etching. 1 metal film 13
Then, the antifuse film 14 is patterned. The remaining first metal film 13 is hereinafter referred to as a lower electrode. After removing the resist 15, as shown in FIG.
A second insulating film 16 is deposited so as to cover the antifuse film 14 and the lower electrode 13.

Then, as shown in FIG. 1G, a resist 17 is applied to form a window at a desired position, and the second insulating film 16 is dry-etched using the resist 17 as a mask to form a contact hole. Open 18 (also called fuse opening). After that, the resist 17 is removed by oxygen plasma treatment. The surface of the anti-fuse film 14 is oxidized by the gas used for dry etching when opening the contact hole 18 and by oxygen plasma when removing the resist 17 to form a surface oxide layer 19. RF power applied to the processing equipment during oxygen plasma treatment is 3.5 W / cm
By limiting the number to ² , the oxide film thickness on the antifuse film surface can be limited to 3 nm or less.

Further, as shown in FIG. 1 (h), after depositing a second metal film 20 serving as an upper electrode of the anti-fuse structure, a resist 21 is applied as shown in FIG. 1 (i). Then, a desired pattern is formed and the second metal film 20 is etched using the resist 21 as a mask. The remaining second metal film 20 is hereinafter referred to as an upper electrode. This completes the antifuse structure.

The reference example 1 is characterized in that the contact hole 18 is formed so that the surface oxide film of the amorphous silicon film 142 of the anti-fuse film 14 is 3 nm or less. By setting the thickness of the oxide film to 3 nm or less, the voltage at which the antifuse film 14 is destroyed becomes about 10 V or less, which is almost no problem when it is normally applied to a semiconductor device, and the variation of the withstand voltage of the antifuse film 14 is reduced. Is also improved. It is considered that this is because the oxide film thickness became as thin as 3 nm and had almost no effect on the dielectric breakdown.

In FIG. 1 (g), the second insulating film 16 was etched under the conventional dry etching conditions to open the contact hole 18, and the resist 17 was removed by using oxygen plasma. In the first method, the exposed surface of the amorphous silicon film 142 is immersed in an extremely dilute aqueous solution of hydrofluoric acid for a few seconds at room temperature, for example. After that, the second metal film 20 serving as the upper electrode is formed.

As described above, the surface oxide layer 19 can be easily removed even by a simple method of treating with a hydrofluoric acid-based solution before forming the upper electrode 20. After the treatment with the hydrofluoric acid solution, it is common to wash with pure water. At this time, an oxide film grows again on the surface of the amorphous silicon, but the thickness is about 1 to 2 nm at most, and 3 nm or less is also satisfactory. Will result. However, compared with Reference Example 1, although the steps of treatment with an aqueous solution of hydrofluoric acid and cleaning increase, the variation in withstand voltage can be suppressed.

FIG. 2 shows a cross section of an anti-fuse structure of a semiconductor device according to an embodiment of the present invention.
The same parts as those in FIG. 1 are designated by the same reference numerals. In the reference example, the antifuse film 14 has two layers of the silicon nitride film 141 and the amorphous silicon film 142, but in the present embodiment, the antifuse film 24 is formed on the silicon nitride film 141 and the amorphous silicon film 142. In addition, an amorphous silicon film 143 formed by plasma CVD using He and SiH ₄ as source gases
Is deposited to form a three-layer structure.

CV using He and SiH ₄ as source gases
By depositing the D amorphous silicon film 143, it becomes possible to suppress the unevenness of the surface, which was conventionally several tens of nm, to several nm. After that, even if the contact hole 18 is opened in the second insulating film 16 with a resist mask under the conventional dry etching condition and the resist is removed with oxygen plasma, the surface oxide layer grown on the surface of the amorphous silicon film 143 is 3 nm as in the case of FIG.
It has the following thickness.

From this, the amorphous silicon film 1
It is considered that since the surface irregularities of 43 are reduced, oxygen ions in the gas used for dry etching are less likely to enter the irregularities. In this way, the withstand voltage of the anti-fuse film 24 can be made substantially constant, and the original bottom end of the contact hole can be broken.

In this embodiment, in the antifuse film 24, the amorphous silicon film 143 is formed by the CVD method using He and SiH ₄ as the source gas. However, instead of this film, N ₂ and SiH ₄ are used as the source materials. Plasma C as gas
It is also possible to deposit an amorphous silicon film by the VD method. It was confirmed that the unevenness of the surface can be suppressed to several nm by this as well. However, in this case, since nitrogen is taken into the amorphous silicon film, it is considered necessary to carefully select the forming conditions. From this point, the CVD method using He gas is preferable.

Needless to say, the amorphous silicon layer forming the anti-fuse film 24 is not limited to the two layers 142 and 143 but only the film 143 may be formed if necessary.

[0025]

As described above, according to the present invention,
By setting the surface oxide layer of amorphous silicon in the antifuse film to 3 nm or less, it is possible to easily realize a method for manufacturing an FPGA device in which variations in withstand voltage of the antifuse film, that is, variations in programming are suppressed.

[Brief description of drawings]

FIG. 1 is a process cross-sectional view showing a method for manufacturing an anti-fuse structure of a semiconductor device in Reference Example 1 for explaining an embodiment of the present invention.

FIG. 2 is a sectional view of an antifuse structure of a semiconductor device according to an embodiment of the present invention.

3A to 3C are process cross-sectional views showing a method of manufacturing an FPGA antifuse structure in a conventional example.

[Explanation of symbols]

11 Semiconductor substrate 12 First insulating film 13 First metal film (lower electrode) 14,24 Anti-fuse film 141 Silicon nitride film 142,143 Amorphous silicon film 15,17,21 resist 16 Second insulating film 18 contact holes 19 Surface oxide layer 20 Second metal film (upper electrode)

Claims (2)

(57) [Claims] 1. A first conductive layer is formed on a substrate and then
Insulating layer and amorphous silicon layer should be deposited in sequence.
Forming a that antifuse layer, the amorpha
Forming an insulating film on the scan silicon layer, wherein forming an etching mask having an opening pattern on the insulating film, the insulating film is selectively removed by using the etching mask, the amorphous silicon layer acid and step, said etching mask to form an opening reaching the surface of the
A step of removing the amorphous silicon layer by He and SiH ₄ , or N ₂ and SiH ₄ as a raw material, including a step of removing the amorphous silicon layer by an elementary plasma treatment and a step of forming a second conductive layer on the opening portion and the insulating film. A method for manufacturing a semiconductor device, characterized in that it is formed by a CVD method. 2. The step of selectively removing the insulating film comprises :
Must be a process of dry etching with a gas containing oxygen
The method for manufacturing a semiconductor device according to claim 1, wherein