JPH03241831A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable the first and second wiring layers to be stably brought into contact with each other by a method wherein an intermediate layer and a conductive layer are successively formed on an underneath layer and after forming an opening part by selectively etching away the conductive layer and the intermediate layer, the underneath layer in the opening part is sputter-etched away and so forth. CONSTITUTION:The title manufacturing process of semiconductor device shall include a process to successively form an intermediate layer 4 and a conductive layer 5 or a layer comprising the same material as that of an underneath layer 3 on the underneath layer 3, another process to form an opening part 8 by etching away the conductive layer 5 or the layer comprising the same material as that of the underneath layer 3 and the intermediate layer 4 and the other process to sputter-etch the whole surface later. For example, the first wiring layer 3, the insulating layer 4 and the conductive layer 5 are formed on the insulating layer 2 on a substrate 1. Next, a resist film 6 is formed to form another opening part 7 and then the conductive layer 5 and the insulating layer 4 in the opening part 7 are selectively etched away to form the contact hole 8. Finally, after removing the resist film 6, the first wiring layer 3 in the contact hole 8 is cleaned up by sputter-etching process to form the second wiring layer 9.

Description

[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing a semiconductor device, when cleaning a first wiring layer in a contact hole by sputter etching, S is deposited on the first wiring layer.
It is an object of the present invention to provide a method for manufacturing a semiconductor device that can hardly cause re-deposition of an insulating film such as i02 and can stably contact a first wiring layer and a second wiring layer. and a step of sequentially forming an intermediate layer and a conductive layer or a layer made of the same material as the base layer on the base layer, and selecting a layer made of the same material as the conductive layer or the base layer and a cough intermediate layer. The structure includes a step of selectively etching to form an opening, and then a step of sputter etching the entire surface.

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, the present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a substrate such as Si or an AI in a contact hole! The present invention relates to a method for manufacturing a semiconductor device that can perform a cleaning process for wiring layers such as the above in a good manner.

Recently, in multilayer wiring technology, contact between a substrate such as Si and a wiring layer such as Ae, and lower layer AI! It is possible to reliably form contacts between wiring layers such as A1 and the upper layer A1, etc.
This is becoming increasingly important as miniaturization progresses.

[Conventional technology]

FIGS. 8(a) to 8(e) are diagrams illustrating a conventional method of manufacturing a semiconductor device.

In FIG. 8, 31 is a substrate made of, for example, Si;
2 is an example lol! An insulating film made of S10□, 33 a first wiring layer made of, for example, WchAl, and 34, for example, a P
An insulating film made of SG, 35 a resist film, 36 an opening formed in the resist film 35, 37 a contact hole formed in the insulating film 34, and 38 a second wiring layer made of Aff, for example.

Note that 1, the first wiring layer 33 and the second wiring layer 3 here
8 is a wiring layer for wiring active elements such as transistors constituting an integrated circuit; and 5. can be applied.

Next, the manufacturing method will be explained.

First, as shown in FIG. 8(a), an insulating film 32 is formed by depositing 5 in 2 on a substrate 31 by, for example, a CVD method, and A1 is deposited on the insulating film 32 by, for example, a sputtering method to form a first insulating film. After forming the wiring layer 33, PSG is deposited on the first wiring layer 33 by, for example, a CVD method to form an insulating film 34.

Next, as shown in FIG. 8(b), a resist is applied on the insulating film 34 to form a resist film 35, and then exposed to light.
A region of the resist film 35 corresponding to the contact hole is patterned by development to form an opening 36 in the resist film 35.
form.

Next, as shown in FIG. 8C, a contact hole 37 is formed by selectively etching the insulating film 34 within the opening 36 using the resist film 35 as a mask by RIB using a fluorine-based gas such as CHF3 gas. do. At this time, A I! is placed on the first wiring 1'i33 in the contact hole 37.
z A high resistance layer is formed due to the generation of a thin layer of O3 (natural oxide film) or the precipitation of impurities. Since the presence of this high resistance layer increases the contact resistance, it is necessary to remove the high resistance layer generated on the first wiring layer 33 in the contact hole 37 in order to reduce the contact resistance. For this reason, as shown in FIG. 8(d), after removing the two resist films 35 by, for example, 02 affing, sputter etching by Ar ion irradiation is performed as a cleaning process for the first wiring Ji33 in the contact hole 37. conduct.

Then, the contact hole 37 is formed by sputtering, for example.
By depositing Al to form a second wiring layer 38 so as to make contact with the first wiring layer 33 in the eighth wiring layer 38,
A wiring structure as shown in Figure (c) can be obtained.

In the conventional method for manufacturing a semiconductor device as described in L.
The contact hole 37 is formed before forming the wiring layer 38 of
The i-th wiring layer 33 is cleaned by sputter etching using Ar ion irradiation, and a high-resistance layer such as AIZO3 that is formed on the first wiring layer 33 when the contact hole 37 is formed in the insulating film 34 is removed. It has the advantage that it can be easily removed.

[Problem to be solved by the invention]

However, in the conventional semiconductor device manufacturing method described above, the first wiring layer 33 in the contact hole 37
When performing sputter etching using Ar ion irradiation,
As shown in FIGS. 9(a) and 9(b), the corner portion X of the insulating film 34 above the contact hole 37 is quickly etched, and the 5in2 etc. forming the insulating film 34 are removed from the first corner of the insulating film 34 at the bottom of the contact hole 37. It was redeposited on the wiring layer 33. For this reason, etching and redeposition are performed simultaneously at the bottom of the contact hole 37, resulting in insufficient cleaning. As a result, the first wiring layer 33 and the second
There is a problem in that the contact resistance with the wiring layer 38 increases, making it impossible to stably contact the first wiring layer 33 and the second wiring layer 38. The reason for this is that as the diameter of the contact hole becomes smaller (particularly submicron), the rate of redeposition at the bottom of the contact hole 37 increases and the contact resistance increases.

Furthermore, since the second wiring layer 38 is difficult to deposit on the side wall of the contact hole, there is a problem in that the electrical connection between the first wiring layer 33 and the second wiring layer 38 is interrupted.

Therefore, the present invention makes it possible to substantially prevent redeposition of an insulating film such as 5i02 on the first wiring layer when cleaning the ml wiring layer in the contact hole by suba-vine etching. and (2) to easily attach the wiring material to the side wall of the contact hole.
The purpose of the present invention is to provide a method for manufacturing a semiconductor device that can stably contact an interconnection layer with a second interconnection layer.
There are 2.

[Means to solve the problem]

In order to achieve the above object, the method for manufacturing a semiconductor device O according to the present invention includes the steps of sequentially forming an intermediate layer, a thin conductive layer, or a layer of the same material as the base layer on the base layer, and a step of sequentially forming the conductive N or The method includes a step of selectively etching a layer of the same material as the underlying layer and the intermediate layer to form an opening, and a step of sputter etching the underlying layer within the opening.

The base layer according to the present invention includes a semiconductor layer made of Si or the like, a metal layer such as A or f, W S l % Ti
Metal silicide layer made of Si, etc., W, Ta, Mo, T
High melting point metal layer such as i, nitride metal layer such as T i N, S
Examples include an insulating layer made of i02, PSG, or the like.

Examples of the intermediate layer according to the present invention include an insulating layer made of SiO□, PSG, etc., and a conductive layer made of AN, etc.

The conductive layer according to the present invention includes 1. Semiconductor layer made of polysilicon etc., metal layer made of A1 etc., WSi, TiS
Metal silicide layer consisting of i, etc., high melting point metal layer, TiN
Examples include metal nitride layers such as.

[Effect]

The present invention is shown in FIGS. 1(a) to (e)-C1. child,
An insulating layer 4 (intermediate layer) and a conductive layer 5 (here made of the same material as the base layer 3) are sequentially formed on the first wiring layer 3 (base layer) L, and the conductive layer 5 and The insulating layer 4 is selectively etched to form an opening 8, and a contact hole 8 (opening) is formed before depositing the second wiring M9.
The first wiring layer 3 inside is sputter etched.

Therefore, when the first wiring layer in the contact hole 8 is subjected to the one-noting process by sputter etching, redeposition of an insulating film such as SiO,+ on the first wiring layer 3 should be hardly caused. Therefore, the first wiring layer 3 and the second wiring layer 9 can be stably contacted.

Specifically, as shown in FIG. 7, in the conventional method, 00. It can be seen that while the contact resistance increases as the contact hole diameter becomes smaller because Si is poured into the contact hole, this is improved by the method of the present invention. Details will be explained in Examples.

〔Example〕 Hereinafter, the present invention will be explained based on the drawings.

FIGS. 1(a) to 1(e) are diagrams illustrating an embodiment of a method for manufacturing a semiconductor device according to the present invention.

In FIG. 1, 1 is a substrate made of, for example, Si, 2 is an insulating layer having a through hole for connection with a substrate l made of, for example, PSG (SiOz, etc.), and 3
is a first wiring layer made of (for example, A, IC polysilicon, etc.) and corresponds to a base layer according to the present invention. Reference numeral 4 denotes an insulating layer made of, for example, PSG (which may also be SiO2, etc.), which corresponds to the intermediate layer according to the present invention. 5 is, for example, Aff(
6 is a resist film, 7 is an opening formed in the resist film 6, 8 is a contact hole formed in the conductive layer 5 and the insulation N4,
This corresponds to the opening according to the present invention. Reference numeral 9 denotes a second wiring layer made of Al (or polysilicon or the like), for example.

Note that the first wiring layer 3 and the second wiring layer 9 can be used as wiring layers for wiring active elements such as transistors constituting an integrated circuit, for example.

Next, the manufacturing method will be explained.

First, as shown in FIG. 1(a), PSG is deposited on a substrate 1 by, for example, the CVD method to a film thickness of, for example, 7000 Å.
An insulating layer 2 is formed, and AI! A first wiring layer 3 with a thickness of, for example, 1 μm is formed by depositing PSG, and an insulating layer 4 with a thickness of, for example, 0.7 μm is formed by depositing PSG on the first wiring layer 3 by, for example, the CVD method. After that, for example 4
Perform annealing treatment at 50°C. At this time, the gas trapped in the insulating layer 4 is generated and exhausted to the outside of the vacuum chamber.

Next, without breaking the vacuum, Al2 is deposited on the insulating layer 4 by, for example, a sputtering method (CVD method may also be used) to form a conductive layer 5 having a film thickness of, for example, 1000 Å. in this way,
After preheating and exhausting the gas contained in the insulating layer 4, AI! Since the conductive layer 5 made of You can prevent this from happening.

Next, as shown in FIG. 1(b), after coating a resist on the conductive layer 5 to form a resist M6, the resist film 6 is patterned in areas corresponding to the contact holes by exposure and development. An opening 7 is formed in the membrane 6.

Next, as shown in FIG. 1(c), the conductive layer 5 and the insulating layer 4 within the opening 7 are selectively etched by, for example, RIE using the resist film 6 as a mask to form a contact hole 8.
form. Note that the conductive layer 5 made of A1 here is made of C
Etching can be performed by RIE using a chlorine-based gas such as Cl4 gas, and the insulating layer 4 made of PSG is etched by C
HF.

Etching can be performed by RIE using a fluorine gas such as gas.

Next, as shown in FIG. 1(d), after removing the resist film 6 by, for example, 02 ansing, a high resistance layer made of A1201 etc. is formed thinly on the first wiring layer 3 in the contact hole 8. In order to remove the first wiring layer 3 within the contact hole 8, sputter etching is performed using Ar ion irradiation to clean the first wiring layer 3 within the contact hole 8. The acceleration voltage at this time is 1KV.

Then, as in the formation of the first wiring layer 3, A/ is deposited to make contact with the first wiring layer 3 in the contact hole 8 by, for example, sputtering method (CVD method may also be used) without breaking the vacuum. By forming the second wiring layer 9,
A wiring structure as shown in FIG. 1(e) can be obtained.

That is, in the above embodiment, as shown in FIGS. 1C and 1D, the conductive layer 5 made of Al is formed on the insulating layer 4, and then the contact hole 8 is formed. With the conductive layer 5 on top, the first wiring layer 3 in the contact hole 8 is sputter etched by Ar ion irradiation. Therefore, the high-resistance layer made of Altos or the like generated after the formation of the contact hole 8 is removed, and the 5 corner portions of the conductive layer above the contact hole 8 are quickly etched to form the conductive layer 5.
I! is poured onto the first wiring layer 3 at the bottom of the contact hole 8 at a certain rate. However, instead of depositing the conventional Sing, etc., the conductive layer 5 is deposited using AI! is deposited, so that the contact resistance between the first wiring layer 3 and the second wiring layer 9 does not increase, and the contact resistance between the first wiring layer 3 and the second wiring layer 9 does not increase.
The wiring layer 9 can be stably contacted.

In the above embodiment, the accelerating voltage for cleaning inside the contact hole 8 is IKV (preferably 700 V or more) for a short time, and the side wall of the insulating film 4 is coated with AI! , but the present invention is not limited to this, and the acceleration voltage is set to 500
It is also possible to conduct the treatment for a long time at a voltage of V or less. Here, the accelerating voltage may be either DC bias or RF bias.

In this case, as shown in FIG. 2(a), when the first wiring layer 3 in the contact hole 8 is sputter etched by Ar ion irradiation, a high concentration of Af, O, etc. is generated after the contact hole 8 is formed. As the resistive layer is removed, the five corners of the conductive layer above the contact hole 8 are quickly etched and fall onto the bottom of the contact hole 8, but since it is made of the same Al as the first wiring layer 3, there is no problem in electrical contact. Furthermore, at the same time, Af from the bottom of contact hole 8
is scattered, and a sidewall film 12 made of Al is formed on the sidewall of the insulating layer 4. Therefore, as shown in FIG. 2(b), as in the above embodiment, the first wiring layer 3 and the second wiring layer 9 can be stably contacted, and the side wall of the insulating film 4 can be
Since the second wiring layer 9 made of Al is formed with the sidewall film 11 made of ffi formed, reliable and stable contact can be made even if the wiring layer 9 is deposited by a formation method with poor coverage. Further, the gas taken into the insulating film 4 (even in the insulating film with SOG as an intermediate layer) during film formation is hardly generated outside, and almost no gas is taken into the second wiring layer 9. Therefore, deterioration of the film quality of the second wiring layer 9 can be prevented from occurring.

When forming the second wiring layer 9 by heating the substrate 1 and depositing Al by sputtering, conventionally it was necessary to use Ti as an underlayer. This is to improve the wettability of the upper layer Aj2, but if the method of the present invention is used, /l can be embedded without any problem since Al is the underlying layer. The step of forming 9 is changed. Then, the substrate 1 is heated to 550° C. and Al is deposited by DC magnetron sputtering. As a result, the contact hole 8 is filled with AA.

Further, in each of the above embodiments, a case has been described in which the first wiring layer 3 is used as the base layer, and the insulating layer 4 and the conductive layer 5 are used as the intermediate layer, but the present invention is not limited to this. The present invention can also be applied to a case where an insulating layer is used as the base layer, a conductive layer is used as the intermediate layer, and a layer made of the same material as the base layer is used. Hereinafter, this will be explained in detail with reference to the drawings.

FIGS. 3(a) to 3(C) illustrate another embodiment of the method for manufacturing a semiconductor device according to the present invention.

In this figure, the same reference numerals as in FIG. 1 indicate the same or corresponding parts, and 21 is, for example, Sin, (PSG, etc.)
This is an insulating layer consisting of the following, and corresponds to the base layer according to the present invention.

Reference numeral 22 denotes a conductive layer made of /l, for example, which can function as a wiring layer, and corresponds to an intermediate layer according to the present invention. For example, 23 is 5
This is an insulating layer made of iOz (PSG or the like may be used), and corresponds to a layer made of the same material as the underlying layer according to the present invention. 24 is an opening formed in the insulating layer 23 and the conductive layer 22, and corresponds to the opening according to the present invention.

Next, the manufacturing method will be explained.

First, as shown in FIG. 3(a), SiOz is deposited on a substrate l by, for example, the CVD method, and the film thickness is, for example, 1 μm.
After forming the insulating layer 21 with a thickness of, for example, 450" in vacuum,
Perform C annealing treatment. At this time, the gas trapped in the insulating layer 21 is generated and exhausted to the outside of the reaction chamber. Next, without breaking the vacuum, A1 is deposited on the insulating layer 21 by, for example, a sputtering method (CVD method may also be used) to form a conductive layer 22 having a film thickness of, for example, 1 μm (before this, a through hole is formed in the insulating layer 21). ). In this way, since the conductive N22 made of Al is formed as the bottom film after the gas contained in the insulating layer 21 is exhausted by heat treatment in advance, almost no gas is taken into the conductive layer 22 during film formation. Therefore, deterioration of the film quality (voids, hillocks, etc.) of the conductive layer 22 can be almost prevented from occurring. Next, S is deposited on the conductive layer 22 by, for example, the CVD method.
iOz is deposited to form an insulating layer 23 having a thickness of, for example, 1 μm, a resist is applied on the insulating layer 1!123 to form a resist film 6, and a region of the resist film 6 corresponding to the contact hole is patterned. Then, an opening 7 is formed in the resist film 6.

Next, as shown in FIG. 3(b), the insulating layer 23 and conductive layer 22 within the opening 7 are selectively etched by, for example, RIE using the resist film 6 as a mask to form an opening 24.

After removing the resist film 6 by, for example, 02 ashes, the insulating layer 21 within the opening 24 is sputter-etched by Ar ion irradiation. In this case, in Figure 3 (C
), when the insulating layer 21 in the opening 24 is sputter-etched, the insulating layer 23 above the opening 24 is etched quickly, and the 5iOz constituting the insulating layer 23 is etched onto the insulating layer 21 at the bottom of the opening 24. At the same time, Sin is deposited from the bottom of the opening 24.

is scattered on the side wall of the conductive layer 22 and the side wall film 2 consisting of 5 ift is scattered on the side wall of the conductive layer 22.
5 is formed.

In this way, if the side wall film 25 consisting of 5 in 2 is formed on the side wall of the conductive layer 22 by sputter etching and insulated, C
Even if the width of the opening 24 becomes smaller than when insulating the opening 24 by filling it with the VD method, insulation can be easily achieved.

Further, the present invention can also be applied to the case of performing Ar ion vanter cleaning on a Si substrate (semiconductor). Specifically, as shown in FIG.
The insulation N4 made of SG and the conductive layer 5 made of polySi are R
This is a case where the contact hole 8 is formed by etching by IE, and after the resist is removed, Ar ion etching is performed. In FIG. 4, 51 is a diffusion layer into which As'' or P'' is introduced. In this case, there is a drawback that damage is easily introduced into the Si substrate 1. Therefore, the thermal wave method is used to prevent damage. As a result of investigating the relationship between introduction and RF power, we obtained Figure 5.As we experimentally found that there is no problem with contact as long as the amount of damage is 800 or less, the preferred RF power and processing time are shown in Figure 5. As shown, 100 seconds or less at 25W, 15 seconds or less at 50W, 1.
The OOW time is 1.5 seconds or less, and in these cases, the depth of damage to the substrate 1 can be suppressed to 50 Å or less. A
The process other than the r-ion cleaning conditions is the same as the other examples.

Note that the conductive layer 5 made of polysilicon is formed by depositing, for example, 2000 Å by CVD.

Furthermore, the present invention can also be applied to a method of forming a capacitor, as shown in FIGS. 6(a) to 6(C). Specifically, as shown in FIG. 6(a), first, an insulating layer 4 made of PSG on a Si substrate 1 and a conductive layer 5 made of Si with about 3,000 pores are etched by RIE to form openings 2.
form 4. Next, as shown in FIG. 6(b), the Si substrate 1 within the opening 24 is etched with Ar ions. At this time, the conductive layer 5 above the opening 24 is quickly etched, and the poly-Si constituting the conductive layer 5 is replaced by the Si at the bottom of the opening 24.
S is deposited on the substrate 1 and S is deposited from the bottom of the opening 24.
i is scattered, and a sidewall film 25 made of Si is formed on the sidewall of the insulating layer 4. Next, ions of As or the like are implanted and annealing is performed to form a lower electrode 61 of the capacitor made of a diffusion layer. Next, as shown in FIG. 1C, the insulating layer 4 made of PSG is etched using HF, and the surface is thermally oxidized to form a dielectric film 62 made of 5 in 2 . At this time, the -1 oxide film thickness is appropriately determined based on the desired capacity. Then, a polysilicon film is formed so as to cover the dielectric film 62 by the CVD method.
t is deposited to form the upper electrode 63 of the capacitor. In this way, the present invention can also be applied to a method of forming a capacitor.

[Effects of the Invention] According to the present invention, when cleaning the first wiring layer in the contact hole by sputter etching, redeposition of an insulating film such as 5in2 on the first wiring layer is hardly caused. This has the effect that the first wiring layer and the second wiring layer can be stably contacted.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining one embodiment of the method for manufacturing a semiconductor device according to the present invention, FIGS. 2 to 4, and 6 are diagrams for explaining the method for manufacturing other embodiments, and FIG. A diagram showing the relationship between the sputtering time and the amount of damage in other embodiments, FIG. 7 is a diagram explaining the present invention in detail, FIG. 8 is a diagram explaining the manufacturing method of the conventional example, and FIG. 9 is the conventional example. FIG. DESCRIPTION OF SYMBOLS 1... Substrate, 2... Insulating film, 3... First wiring layer, 4... Insulating film, 5... Conductive layer, 6...resist film, 7...opening, 8...contact hole, 9...second wiring layer, 21... ... Insulating layer, 22 ... Conductive layer, 23 ... Insulating layer, 24 ... Opening. 9: Second arrangement JiIN - How to make 110 alliances, Yo 1 Theory 4: 1st figure Explaining the b-poem of the real mating sequence of the pond Figure 1 While explaining the manufacturing method of other embodiments 210- Figure 8 Explaining the problem of following 1j Figure 8

Claims (1)

[Claims] An intermediate layer (4, 22) and a conductive layer (5) or a layer (23) made of the same material as the underlying layer (3, 21) are sequentially formed on the underlying layer (3, 21). a layer (23) of the same material as the conductive layer (5) or the underlying layer (3, 21);
and a step of selectively etching the intermediate layer (4, 22) to form an opening (8, 24), and then sputter etching the entire surface. .