JPH098063A - Manufacture of semiconductor integrated device - Google Patents

Abstract

PURPOSE: To enable using gate metal material and ohmic electrode material as the material of a resistance element, in order to realize a resistance element of high precision, by forming through holes on resistance element metal by simultaneous etching them to form wiring. CONSTITUTION: A second through hole 13 part is continuously exposed to light by using a mask different from a mask which has been used for exposing a first through hole 12 part. At the time of exposure of the second through hole 13 part, offset is applied to an aligner, and the deviation of resistance value of a resistance element is corrected by the distance between the first through hole 12 and the second through hole 13. After metal for electrolytic plating path is deposited on the whole surface by a sputtering method, resist is patterned, and selective plating is performed. The plating is used as a mask, and wiring 11 is formed by anisotropically etching the metal for electrolytic plating path.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated device, and more particularly to a method for manufacturing a semiconductor integrated device including a highly accurate resistance element.

[0002]

20 to 26 are sectional views for explaining a conventional method of manufacturing a semiconductor integrated device including a resistance element in the order of steps.

The conventional example shown in FIGS. 20 to 26 is a semi-insulating substrate 1.
It includes a step of forming a gate electrode 6 and a semiconductor element composed of two ohmic electrodes so as to sandwich the gate electrode 6, and a step of forming a resistance element.

First, on the semi-insulating GaAs substrate 1, a buffer layer 2, a first n-type GaAs layer 3 serving as a conductive layer, and the first n-type GaAs in order to reduce the ohmic contact resistance of the ohmic electrode. The second n-type GaAs layer 4 having a carrier concentration higher than that of the layer 3 is continuously grown by the molecular beam epitaxial growth method.

Next, as shown in FIG. 20, the second n-type GaAs layer of the gate electrode 6 and a part of the first GaAs layer are etched.

Next, electrical element isolation is performed by selective boron ion implantation, and the gate electrode 6 is formed on the first n-type GaAs layer and the second n-type GaAs is formed on the second n-type GaAs layer as shown in FIG. An ohmic electrode is formed in sequence to form an ohmic contact with the GaAs layer.

Next, the first insulating film 5 in the region where the resistance element is formed is selectively etched by the anisotropic dry etching method similarly to the method of forming the gate electrode 6, and the WSiN film 7 is formed.
After being deposited by sputtering, patterning is performed with a resist and processing is performed by reactive dry etching to form a resistance element as shown in FIG.

Next, as shown in FIG. 23, the first insulating film 5 is etched by wet etching to obtain AuGe.
Ni is vapor-deposited and processed by the lift-off method to form the ohmic electrode 8.

Next, as shown in FIG. 24, a second insulating film 9 is grown and flattened. Next, as shown in FIG. 25, the photosensitive material 10 is applied on the second insulating film 9, the first through-hole 12 is exposed, and the through-hole is collectively exposed to perform anisotropic dry etching. A through hole is formed by the method.

Finally, after depositing a metal for an electrolytic plating pass on the entire surface by sputtering, patterning with a resist is performed and selective plating is performed. Using the plating as a mask, the metal for an electrolytic plating pass is anisotropically etched. Then, the wiring 11 is formed and the semiconductor integrated device as shown in FIG. 26 is manufactured.

[0011]

In the conventional method of manufacturing a semiconductor integrated device including a resistance element, when the resistance element is formed, there is a variation in low efficiency per unit area due to a variation in the film thickness of the material used for the resistance element. There is a problem in that the resistance value of the resistance element cannot be stably obtained due to a large influence. The permissible range of the film thickness in manufacturing is ± 10%, and there is a problem that the resistance value varies in that range, which reduces the yield.

The present invention has been made in view of the above points, and in order to realize a highly accurate resistance element, a semiconductor integrated circuit in which a gate metal material and an ohmic electrode material can be used as the material of the resistance element. An object is to provide a method for manufacturing a device.

[0013]

In order to achieve the above object, the present invention has two ohmic electrodes, a source electrode and a drain electrode, which have a conductive layer on a semi-insulating GaAs substrate and form an ohmic contact with the conductive layer. And a step of forming a semiconductor element composed of a gate electrode sandwiched between the ohmic electrodes, a step of depositing a metal to become a resistance element on the semi-insulating GaAs substrate, a step of processing the metal to become the resistance element, A step of measuring a resistance value of the used resistance element, a step of continuously exposing two or more through holes different from the two or more through holes for electrically connecting the resistance element and the outside, and performing continuous exposure; The method is characterized by including a step of simultaneously etching and forming all the through holes formed on the resistance element metal and a step of forming wiring.

The present invention is also characterized in that the material used for the resistance element is the same as the material for the gate electrode of the semiconductor element, or the material used for the resistance element is the same as the material for the ohmic electrode of the semiconductor element. And

[0015]

The present invention makes it possible to adjust the resistance variation of the deposited metal by changing the resistance element length after measuring the resistance value of the resistance element formed of a metal provided on the semi-insulating substrate. The central value of variation is stable, and a semiconductor integrated device including a highly accurate resistance element can be realized with high yield. In addition, in the present invention, a metal whose shape changes when subjected to a high-temperature heating process such as ohmic electrode and has a large variation in resistance value can be used as the material of the resistance element, so that the step of forming the resistance element is not necessary. Since the resistance element can be formed simultaneously with the semiconductor element, the process can be shortened and an inexpensive semiconductor integrated device can be realized.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a semiconductor integrated device according to the present invention will be described below with reference to the drawings.

1 to 7 are sectional views for explaining a schematic structure of a first embodiment of the present invention in the order of steps.

On the semi-insulating GaAs substrate 1, a buffer layer 2 for reducing the influence of the semi-insulating GaAs substrate 1,
The first n-type GaAs layer 3 serving as a conductive layer and the second n-type GaAs layer 4 serving as an ohmic contact layer are continuously grown by a molecular beam epitaxial growth method. This continuous growth is the same when the metal vapor deposition method is used. Next, as shown in FIG. 1, the second n-type GaA of the gate electrode portion is formed.
A part of the s layer 4 and the first n-type GaAs layer 3 is etched to form a recess.

Next, electrical isolation is performed by selective boron ion implantation, the first insulating film 5 is grown on the entire surface of 5000 Å, and the first insulating film 5 in the gate electrode portion is anisotropically dried. Selectively etched by the etching method. Further, after WSi / Au is continuously deposited by sputtering, patterning is performed with a resist and the WSi / Au is processed by anisotropic dry etching to form the gate electrode 6 as shown in FIG.

Next, the first insulating film 5 in the region where the resistance element is formed is selectively etched by the anisotropic dry etching method similarly to the method of forming the gate electrode 6, and the WSiN film 7 is formed.
Is deposited by a sputtering method, patterned by a resist, and processed by a reactive dry etching method to form a resistance element as shown in FIG.

Next, as shown in FIG. 4, the first insulating film 5 is etched by wet etching to obtain AuGeN.
i is vapor-deposited and processed by the lift-off method to form the ohmic electrode 8. At this time, the resistance value of the resistance element or the sheet resistance using a TEG prepared in advance is measured to obtain the resistance value of the resistance element. The resistance value deviation amount is calculated by comparing the obtained actual resistance value of the resistance element with the designed resistance value used for the design in advance.

Next, as shown in FIG. 5, a second insulating film 9 is grown and flattened. Next, as shown in FIG. 6, a photosensitive material 10 is applied on the second insulating film 9, and the first through holes 12 are formed.
Then, the second through-hole 13 is exposed using a mask different from that used for exposing the first through-hole 12 part. When exposing the second through-hole 13 part, offset is applied on the exposure machine,
The deviation amount of the resistance value of the resistance element is corrected by the distance between the first through hole 12 and the second through hole 13.

Finally, a metal for electrolytic plating pass is deposited on the entire surface by sputtering, patterning is performed with a resist, selective plating is performed, and the metal for electrolytic plating pass is etched by anisotropic etching using the plating as a mask. Then, the wiring 11 is formed and the semiconductor integrated device as shown in FIG. 7 is manufactured.

8 to 13 are sectional views for explaining the schematic structure of the second embodiment of the present invention in the order of steps.

On the semi-insulating GaAs substrate 1, a buffer layer 2 for reducing the influence of the semi-insulating GaAs substrate 1,
The first n-type GaAs layer 3 serving as a conductive layer and the second n-type GaAs layer 4 serving as an ohmic contact layer are continuously grown by a molecular beam epitaxial growth method. This continuous growth is the same when the metal vapor deposition method is used. Next, as shown in FIG. 8, the second n-type GaAs layer 4 and the first n-type GaAs in the gate electrode section and the resistance element section are formed.
A portion of layer 3 is etched to form a recess.

Next, electrical element isolation is performed by selective boron ion implantation, the first insulating film 5 is grown on the entire surface of 5000 Å, and the first insulating film 5 of the gate electrode portion and the resistance element portion is formed. Selective etching is performed by anisotropic dry etching. Further, after WSi / Au is continuously deposited by a sputtering method, patterning is performed by a resist and the WSi / Au is subjected to an anisotropic dry etching method.
Are processed to form the gate electrode 6 and the resistance element as shown in FIG.

Next, as shown in FIG. 10, the first insulating film 5 is etched by wet etching to obtain AuGe.
Ni is vapor-deposited and processed by the lift-off method to form the ohmic electrode 8. After the ohmic electrode 8 is formed, the resistance value of the resistance element or the sheet resistance using a TEG prepared in advance is measured to obtain the resistance value of the resistance element. The resistance value deviation amount is calculated by comparing the obtained actual resistance value of the resistance element with the designed resistance value used for the design in advance.

Next, as shown in FIG. 11, a second insulating film 9 is grown and flattened. Next, as shown in FIG. 12, the photosensitive material 10 is applied on the second insulating film 9, the first through hole 12 is exposed, and the first through hole 12 is used for exposure. Then, the second through hole 13 is exposed by using a different mask. When the second through hole 13 is exposed, an offset is applied on the exposure machine so that the amount of deviation of the resistance value of the resistance element can be adjusted by the first through hole 1.
2 and the distance between the second through holes 13 are used for correction.

Finally, a metal for electrolytic plating pass is deposited on the entire surface by sputtering, patterning is performed with a resist, selective plating is performed, and the metal for electrolytic plating pass is etched by anisotropic etching using the plating as a mask. Then, the wiring 11 is formed and the semiconductor integrated device as shown in FIG. 13 is manufactured.

14 to 19 are sectional views for explaining the schematic structure of the third embodiment of the present invention in the order of steps.

On the semi-insulating GaAs substrate 1, a buffer layer 2 for reducing the influence of the semi-insulating GaAs substrate 1,
The first n-type GaAs layer 3 serving as a conductive layer and the second n-type GaAs layer 4 serving as an ohmic contact layer are continuously grown by a molecular beam epitaxial growth method. This continuous growth is the same when the metal vapor deposition method is used. Next, as shown in FIG. 14, the second n-type Ga of the gate electrode portion is formed.
A recess is formed by etching part of the As layer 4 and the first n-type GaAs layer 3.

Next, electrical isolation is performed by selective boron ion implantation, the first insulating film 5 is grown on the entire surface of 5000 Å, and the first insulating film 5 in the gate electrode portion is anisotropically formed. Selective etching is performed by a dry etching method. Further, after WSi / Au is continuously deposited by the sputtering method, patterning is performed with a resist and the WSi / Au is processed by the anisotropic dry etching method to form the gate electrode 6 as shown in FIG.

Next, as shown in FIG. 16, the ohmic electrode 8 is formed.
The first insulating film 5 in the formation portion and the resistance element portion is etched by wet etching to obtain AuGeNi.
Is vapor-deposited and processed by a lift-off method to form an ohmic electrode 8 and a resistance element. The resistance value of the resistance element after formation of the ohmic electrode 8 or TE prepared in advance
Sheet resistance measurement using G is performed to obtain the resistance value of the resistance element. The resistance value deviation amount is calculated by comparing the obtained actual resistance value of the resistance element with the designed resistance value used for the design in advance.

Next, as shown in FIG. 17, a second insulating film 9 is grown and flattened. Next, as shown in FIG. 18, the photosensitive material 10 is applied on the second insulating film 9, the first through-hole 12 part is exposed, and then the first through-hole 12 part is used for exposure. Then, the second through hole 13 is exposed by using a different mask. When the second through hole 13 is exposed, an offset is applied on the exposure machine so that the amount of deviation of the resistance value of the resistance element can be adjusted by the first through hole 1.
2 and the distance between the second through holes 13 are used for correction.

Finally, a metal for electrolytic plating pass is deposited on the entire surface by sputtering, patterning with a resist is performed, selective plating is performed, and the metal for electrolytic plating pass is etched by anisotropic etching using the plating as a mask. Then, the wiring 11 is formed and the semiconductor integrated device as shown in FIG. 19 is manufactured.

[0036]

INDUSTRIAL APPLICABILITY The present invention relates to a semiconductor integrated device including a resistance element, which is used for the resistance element because the resistance value of the resistance element is measured, the deviation amount of the resistance value is measured in advance, and the distance between the resistance elements can be changed. Since the variation in the film thickness of the material can be absorbed, the highly accurate resistance element can be realized within the variation in the film thickness in the process, and the semiconductor integrated device having the highly accurate resistance element can be realized at a high yield.

[Brief description of drawings]

FIG. 1 is a sectional view illustrating a schematic configuration of a first step of Example 1 of the present invention.

FIG. 2 is a sectional view illustrating a schematic configuration of a second step of Example 1 of the present invention.

FIG. 3 is a sectional view illustrating a schematic configuration of a third step of Example 1 of the present invention.

FIG. 4 is a sectional view illustrating a schematic configuration of a fourth step of Example 1 of the present invention.

FIG. 5 is a sectional view illustrating a schematic configuration of a fifth step of Example 1 of the present invention.

FIG. 6 is a sectional view illustrating a schematic configuration of a sixth step of Example 1 of the present invention.

FIG. 7 is a cross-sectional view illustrating the schematic configuration of a seventh step of Example 1 of the present invention.

FIG. 8 is a sectional view illustrating a schematic configuration of a first step of Example 2 of the present invention.

FIG. 9 is a sectional view illustrating a schematic configuration of a second step of Example 2 of the present invention.

FIG. 10 is a sectional view illustrating a schematic configuration of a third step of Example 2 of the present invention.

FIG. 11 is a cross-sectional view illustrating the schematic structure of a fourth step of Example 2 of the present invention.

FIG. 12 is a sectional view illustrating a schematic configuration of a fifth step of Example 2 of the present invention.

FIG. 13 is a sectional view illustrating a schematic configuration of a sixth step of Example 2 of the present invention.

FIG. 14 is a sectional view illustrating a schematic configuration of a first step of Example 3 of the present invention.

FIG. 15 is a sectional view illustrating a schematic configuration of a second step of Example 3 of the present invention.

FIG. 16 is a sectional view illustrating a schematic configuration of a third step of Example 3 of the present invention.

FIG. 17 is a sectional view illustrating a schematic configuration of a fourth step of Example 3 of the present invention.

FIG. 18 is a sectional view illustrating a schematic configuration of a fifth step of Example 3 of the present invention.

FIG. 19 is a sectional view illustrating a schematic configuration of a sixth step of Example 3 of the present invention.

FIG. 20 is a cross-sectional view illustrating a first step of a method for manufacturing a semiconductor integrated device including a conventional resistance element.

FIG. 21 is a cross-sectional view illustrating a second step of the method for manufacturing the semiconductor integrated device including the conventional resistance element.

FIG. 22 is a cross-sectional view illustrating the third step of the method for manufacturing the semiconductor integrated device including the conventional resistance element.

FIG. 23 is a cross-sectional view illustrating the fourth step of the method for manufacturing the semiconductor integrated device including the conventional resistance element.

FIG. 24 is a cross-sectional view illustrating the fifth step of the method for manufacturing the semiconductor integrated device including the conventional resistance element.

FIG. 25 is a sectional view illustrating a sixth step of the method for manufacturing a semiconductor integrated device including a conventional resistance element.

FIG. 26 is a cross-sectional view illustrating the seventh step of the method for manufacturing the semiconductor integrated device including the conventional resistance element.

[Explanation of symbols]

 1 semi-insulating GaAs substrate 2 buffer layer 3 first n-type GaAs layer 4 second n-type GaAs layer 5 first insulating film 6 gate electrode 7 WSiN film 8 ohmic electrode 9 second insulating film 10 photosensitive material 11 Wiring 12 First through hole 13 Second through hole

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 27/04 21/822

Claims (3)

[Claims] 1. A semiconductor device comprising a conductive layer on a semi-insulating GaAs substrate, two ohmic electrodes, a source electrode and a drain electrode, which are in ohmic contact with the conductive layer, and a gate electrode sandwiched between the ohmic electrodes. Forming step, depositing a metal forming a resistance element on the semi-insulating GaAs substrate, processing the metal forming the resistance element, measuring the resistance value of the resistance element using the metal, the resistance Of two or more through-holes for electrically connecting the element and the outside, different through-holes are continuously exposed in two or more times, and the through-holes formed on the resistive element metal are all etched at the same time. A method of manufacturing a semiconductor integrated device, comprising: a step of forming a semiconductor integrated device and a step of forming a wiring. 2. The method for manufacturing a semiconductor integrated device according to claim 1, wherein the material used for the resistance element is the same as the material for the gate electrode of the semiconductor element. 3. The method for manufacturing a semiconductor integrated device according to claim 1, wherein the material used for the resistance element is the same as the material for the ohmic electrode of the semiconductor element.