JP2589393B2 - GaAs Hall element - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Hall element, and more particularly to a high-sensitivity GaAs Hall element having a structure in which characteristics are unlikely to deteriorate during a manufacturing process and has a small offset voltage. is there.

[Conventional technology]

Conventionally, a Hall element using a GaAs single crystal substrate has an n-type GaAs layer 2 epitaxially grown on a semi-insulating GaAs substrate 1 or a semi-insulating single-crystal GaAs substrate 1 as shown in FIG.
A thin layer 2 of n-type GaAs obtained by implanting ions such as Si ⁺ or S ⁺ into the surface of the substrate and annealing at a high temperature of 800 ° C. or higher was used as the magnetic sensing part of the Hall element. On the n-type GaAs layer on the surface, an electrode 4 and an insulating film 5 such as Sa ₃ N ₄ or SiO ₂ were formed in direct contact. Therefore, Si ₃ N ₄ by sputtering or plasma CVD
The basic characteristics such as the output and the resistance value of the Hall element change greatly depending on the film forming conditions of the insulating film such as SiO ₂ , which is a major problem in manufacturing. In other words, the insulating film on GaAs has the property of greatly changing the crystal characteristics of GaAs at the interface with GaAs, and as a result, the characteristics of the GaAs Hall element have changed.

However, this insulating film is indispensable for a GaAs Hall element, and is important as a protective film against moisture in an element molded with resin or the like.

[Problems to be solved by the invention]

As described above, the conventional Hall element has a structure in which the insulating film 5 such as Si ₃ N ₄ or SiO ₂ directly contacts the surface of n-type GaAs. For this reason, dislocations and point defects occur on the surface of the active layer by forming an insulating film such as Si ₃ N ₄ or SiO _{2 on} the surface, and abnormal diffusion of implanted impurities due to a subsequent heating step such as annealing, or There has been a problem that the surface of the active layer is thermally deformed and the element characteristics are changed. That is,
In the process of forming an insulating film such as Si ₃ N ₄ or SiO ₂ , a large change in input resistance and output resistance of a GaAs Hall element to be manufactured and a decrease in Hall output occur. Therefore, an object of the present invention is to have high sensitivity, high quality, and high reliability with a structure that does not deteriorate the characteristics in the manufacturing process and has a good yield and a small amount of offset.
The purpose is to provide a GaAs Hall element.

[Means for solving the problem]

The GaAs Hall element of the present invention has an active layer made of an n-type GaAs conductive layer formed on an insulating substrate, a surface protective layer made of GaAs or GaAlAs having small conductivity formed on the active layer, An ohmic electrode formed on the active layer,
An insulating layer covering the surface protective layer.

(Operation)

In the conventional structure, when an insulating film such as Si ₃ N ₄ or SiO ₂ is formed, the GaAs active layer itself is damaged, and the electrical characteristics are changed. However, when an electrically inactive layer is formed on the active layer and an insulating film is formed thereon, the Si ₃ N
_When an insulating film such as ₄ or SiO ₂ is formed, it is an electrically inactive layer that does not contribute to the electrical characteristics of the GaAs Hall element. Therefore, fluctuations in the characteristics of the manufactured GaAs Hall element are extremely reduced, and a GaAs Hall element with stable and uniform characteristics can be mass-produced with good reproducibility.

〔Example〕

 Hereinafter, the present invention will be described by way of examples.

FIG. 1 shows the structure of an embodiment of the device according to the present invention. This device has an active layer 2 made of n-type GaAs on a semi-insulating GaAs substrate 1, and further thereon an GaAs layer 3 having small conductivity or an AlGaAs layer 3 in which a part of Ga is replaced by Al. The electrode 4 and the protective film 5 are provided on the electrically inactive layer 3. That is, a semiconductor layer 3 which is electrically inactive and lattice-matched to the GaAs active layer is formed between the active layer and the insulating film.

The Hall element of the present invention is manufactured as follows. In other words, the surface of the semi-insulating substrate 1 is
N-type impurities such as Si, S, Sn and Ge are 2 × 10 ¹⁶ to 1 × 10 ¹⁸ / cm
^{(3) A} doped GaAs layer 2 is formed to a thickness of 0.15 to 0.50 μm by a method such as the MEB method or the MOCVD method. It is formed with a thickness of not more than μm to be an inactive layer on the surface. This layer is lattice-matched with the GaAs active layer doped with an n-type impurity, and does not affect the electrical characteristics of the active layer. In such a structure, Si ₃ N ₄ or SiO ₂
When the insulating film 5 is formed, it is an electrically inactive layer that does not contribute to the electrical characteristics of the GaAs Hall element. When the active layer 2 having n-type conductivity is formed by ion implantation of Si ⁺ or S ⁺ , the carrier energy is increased on the surface of the substrate by increasing the acceleration energy during ion implantation (300 keV or more). An amorphous GaAs layer with few ions and through which ions have passed is formed. Then, the implanted ions are activated by rapid annealing without diffusing the impurities into the surface layer. At this time, the dose is 3 × 10 ¹⁶ to 1 × after the peak carrier concentration is activated.
Make the amount to be 10 ¹⁸ / cm ³ . The amorphous GaAs layer 3 formed on the surface functions as a layer for protecting the lower active layer in the step of forming the insulating film 5 such as Si ₃ N ₄ or SiO ₂ . As a result, the variation in characteristics of the GaAs Hall element to be manufactured is extremely small, and a stable and uniform GaAs Hall element can be mass-produced with good reproducibility.

The insulating film used at this time is not limited to Si ₃ N ₄ or SiO ₂ ,
In general, all materials used for passivation of semiconductors can be used. Among them, Si ₃ N ₄ , SiO ₂ and Al ₂ O ₃ are more preferable. This insulating film is formed with a thickness of 0.15 to 0.40 μm.

(Trial Production Example 1) FIG. 3 shows a trial production example in which the MBE method was used and an undoped GaAs layer was used as the surface layer. First, an n-type GaAs active layer 2 doped with silicon is grown to a thickness of 0.3 μm on a semi-insulating GaAs substrate 1 by MBE, and then an undoped GaAs layer 3 having a thickness of 0.15 μm is formed at a low temperature of 400 ° C.
A semiconductor layer for obtaining the element configuration shown in FIG. 1 was formed (FIG. 3A).

Next, a photoresist 6 is applied to form a predetermined cross-shaped pattern (FIG. 3 (b)).
The substrate was etched to a predetermined depth, and then the resist was removed by an ashing method using a resist stripper or O ₂ plasma to form a magnetically sensitive portion of the Hall element (FIG. 3 (c)).

An insulating film 5 such as Si ₃ N ₄ having a thickness of 0.3 μm was formed on the entire surface of the substrate at 300 ° C. by a plasma CVD method (FIG. 3D). By adopting a process at a low temperature of 300 ° C., there was almost no thermal decomposition of the GaAs substrate.

Next, the part of Si ₃ N ₄ that forms ohmic contact with the electrode metal
Was etched, and a pattern was formed so that a hole was formed in a portion where an ohmic contact was to be formed. Thereafter, using this resist as a mask, CF ₄
The contact portion was opened by reactive dry etching using a gas and an O ₂ gas (FIG. 3E). Then, the GaAs layer on the surface was removed by slight etching. Then, As
Ge, Ni and Au are 0.25μm, 0.05μm and 0.35μm respectively
Then, the photoresist and the metal on the photoresist were removed by a lift-off method to form an electrode pattern 4. Then, in order to obtain ohmic contact, alloying treatment was performed in an infrared heating furnace at about 400 ° C. for 5 minutes under a N ₂ gas atmosphere. In this way, a large number of Ga
As Hall elements were formed (FIG. 3 (f)).

Thereafter, dicing was performed to separate the individual GaAs Hall element pellets. Subsequently, die bonding and transfer molding were performed to produce a Hall element.

Table 1 shows a comparison of characteristics when a GaAs Hall element is manufactured by a conventional method and a method according to the present invention. Compared with the conventional method, in the present invention, the characteristics of the GaAs Hall element do not vary, and the unbalance voltage is reduced.

(Trial Production Example 2) FIG. 3 shows a trial production example in which the MBE method was used and an undoped AlGaAs layer was used as the surface layer. First, semi-insulating GaAs
N-type GaAs doped with silicon by MBE on the substrate 1
An active layer 2 was grown to 0.3 μm, and then an undoped AlGaAs layer 3 of 0.15 μm was formed at a substrate temperature of 600 ° C. to form a semiconductor layer for obtaining the device configuration shown in FIG. 1 (FIG. 3A). .

Next, a photoresist 6 is applied to form a predetermined cross-shaped pattern (FIG. 3 (b)).
The substrate was etched to a predetermined depth, and then the resist was removed by an ashing method using a resist stripper or O ₂ plasma to form a magnetically sensitive portion of the Hall element (FIG. 3 (c)).

An insulating film 5 such as Si ₃ N ₄ having a thickness of 0.3 μm was formed on the entire surface of the substrate at 300 ° C. by a plasma CVD method (FIG. 3D). By adopting a process at a low temperature of 300 ° C., there was almost no thermal decomposition of the GaAs substrate.

Next, the part of Si ₃ N ₄ that forms ohmic contact with the electrode metal
In order to etch, a pattern was formed so that a hole was formed in a portion where an ohmic contact was formed by applying a photoresist 7. Thereafter, using the resist as a mask, a contact portion was opened by reactive dry etching using CF ₄ gas and O ₂ gas (FIG. 3E). And on the surface
The GaAs layer was removed by slight etching. Then AuG
e, Ni and Au were deposited to a thickness of 0.25 μm, 0.05 μm and 0.35 μm, respectively, and then the photoresist and the metal were removed from the photoresist by a lift-off method to form an electrode pattern 4. Then, in order to obtain ohmic contact, alloying treatment was performed in an infrared heating furnace at about 400 ° C. for 5 minutes under a N ₂ gas atmosphere. In this way, a large number of Ga
As Hall elements were formed (FIG. 3 (f)).

Thereafter, dicing was performed to separate the individual GaAs Hall element pellets. Subsequently, die bonding and transfer molding were performed to produce a Hall element.

Table 2 shows the characteristics when a GaAs Hall element is manufactured by the conventional method and the method according to the present invention. Compared with the conventional method, in the present invention, the characteristics of the GaAs Hall element do not vary, and the unbalance voltage is reduced.

The range of compositions that can be used for the undoped AlGaAs layer is given by the formula
When represented by Al _X Ga _1-X As, the range is 0 <x ≦ 1.

(Trial Production Example 3) FIG. 4 shows a trial production example using the ion implantation method. First, on a semi-insulating GaAs substrate 1, silicon ions (S
i ⁺ ) with an acceleration energy of 300 keV and a dose of 2.3 × 10 ¹² / cm
² (dose amount such that the peak carrier concentration after activation was about 5 × 10 ¹⁶ / cm ³ ). Then, in order to activate the silicon ions and to recover the defects, a rapid anneal treatment at 850 ° C. for 10 seconds in an arsine (AsH ₃ ) atmosphere is performed, and the n-type conductive GaAs active layer 2 and the surface are removed. Layer 3 was formed. In this way, a semiconductor layer for obtaining the element configuration shown in FIG. 1 was formed (FIG. 4A). Since the acceleration energy is 300 keV, the peak of the carrier concentration is formed at a depth of about 0.2 μm from the surface. On the surface of the substrate having a depth of 0.1 μm or less, a small conductive surface layer having a carrier concentration of 5 × 10 ¹⁵ / cm ³ or less is formed. Therefore, the n-type active layer does not contact the surface of the GaAs substrate. The sheet resistance of the active layer formed by the above process is approximately 1 kΩ
Becomes

Next, a photoresist 6 is applied to form a predetermined cross-shaped pattern (FIG. 4 (b)).
The substrate was etched to a predetermined depth, and then the resist was removed by an ashing method using a resist stripper or O ₂ plasma to form a magnetically sensitive portion of the Hall element (FIG. 4 (c)).

An insulating film such as Si ₂ N ₄ having a thickness of 0.3 μm was formed on the entire surface of the substrate at 300 ° C. by a plasma CVD method.
Figure (d). By adopting a process at a low temperature of 300 ° C., there was almost no thermal decomposition of the GaAs substrate.

Next, the portion of the Si ₂ N ₄ that forms ohmic contact with the electrode metal
In order to etch, a pattern was formed so that a hole was formed in a portion where an ohmic contact was formed by applying a photoresist 7. Then, using this photoresist as a mask, CF
_The contact portion was opened by reactive dry etching using ₄ gas and O ₂ gas (FIG. 4 (e)). Then, the GaAs layer on the surface was removed by slight etching. afterwards,
AuGe, Ni and Au are 0.25μm, 0.05μm and 0.35μm respectively
The metal on the photoresist and the photoresist was removed by a lift-off method to form an electrode pattern 4. Then, in order to obtain ohmic contact, alloying treatment was performed in an infrared heating furnace at about 400 ° C. for 5 minutes under a N ₂ gas atmosphere. In this way, a large number of Ga
As elements were formed (FIG. 4 (f)).

Thereafter, dicing was performed to separate the individual GaAs Hall element pellets. Subsequently, die bonding and transfer molding were performed to produce a Hall element.

Table 3 shows the characteristics when GaAs Hall elements were made by the conventional method and the method according to the present invention. Compared with the conventional method, in the present invention, the characteristics of the GaAs Hall element do not vary, and the unbalance voltage is reduced.

(Trial Production Example 4) Another trial production example using the ion implantation method is shown in FIG. First, a photoresist 6 is applied on a semi-insulating GaAs substrate 1, and a window of an ion implantation region is formed by using a usual photolithography method. Then, to form an n-type GaAs active layer, silicon ions (Si ⁺ ) were accelerated at an energy of 300 keV and a dose of
2.3 × 10 ¹² / cm ² (Peak carrier concentration after activation is 5 × 10
^At a dose of about ¹⁶ / cm ³ ) (FIG. 5A), silicon ions (Si ⁺ ) are then accelerated at 150 ke to form a low resistance n ⁺ GaAs portion 8 for external connection.
V, implantation at a dose of 1.0 × 10 ¹³ / cm ² (FIG. 5 (b))
Thereafter, the resist was removed by a resist stripping solution or an ashing method using O ₂ plasma. In order to activate the silicon ions and recover defects, arsine (As
H ₃ ) Rapid anneal processing was performed in an atmosphere at 850 ° C. for 10 seconds to form an active layer, and a semiconductor layer for obtaining the element configuration shown in FIG. 1 was formed (FIG. 5C). Since the acceleration energy is 300 keV, the peak of the carrier concentration is
It is formed to a depth of about 0.2 μm from the surface. Depth 0.1
On the surface of the substrate having a thickness of not more than μm, a surface layer having a small conductivity having a carrier concentration of not more than 5 × 10 ¹⁵ / cm ³ is formed. Therefore, the n-type active layer does not contact the surface of the GaAs substrate. The sheet resistance of the active layer formed by the above processing is approximately 1 kΩ.

An insulating film such as Si ₃ N ₄ having a thickness of 0.3 μm was formed on the entire surface of the substrate at 300 ° C. by a plasma CVD method (fifth embodiment).
Figure (d). By adopting a process at a low temperature of 300 ° C., there is almost no thermal decomposition of GaAs as a substrate.

Next, the part of Si ₃ N ₄ that forms ohmic contact with the electrode metal
In order to etch, a pattern was formed so that a hole was formed in a portion where an ohmic contact was formed by applying a photoresist 7. Then, using this photoresist as a mask, CF
_The contact portion was opened by reactive dry etching using ₄ gas and O ₂ gas (FIG. 5 (e)). Then, the GaAs layer on the surface was removed by slight etching. afterwards,
AuGe, Ni and Au are 0.25μm, 0.05μm and 0.35μ respectively.
Then, the photoresist and the metal on the photoresist were removed by a lift-off method to form an electrode pattern 4. Then, in order to obtain ohmic contact, an alloying treatment at about 400 ° C. for 5 minutes in an infrared heating furnace was performed using N _2.
The test was performed under a gas atmosphere. Thus, a number of GaAs Hall elements were formed on one substrate (FIG. 5 (f)).

Thereafter, dicing was performed to separate the individual GaAs Hall element pellets. Subsequently, die bonding and transfer molding were performed to produce a Hall element.

Table 4 shows the characteristics when a GaAs Hall element is manufactured by the conventional method and the method according to the present invention. Compared with the conventional method, in the present invention, the characteristics of the GaAs Hall element do not vary, and the unbalance voltage is reduced.

[Effects of the Invention] As described above, according to the present invention, deterioration of characteristics is unlikely to occur constantly during the process of forming an insulating film such as Si ₃ N ₄ , and a high-quality Hall element is produced with good reproducibility. be able to.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view schematically showing a device according to the present invention, FIG. 2 is a cross-sectional view schematically showing a device according to a conventional method, FIG. 3 is an MBE method, and FIGS. It is a process drawing explaining the example of trial manufacture of the present invention. 1 ...... semi-insulating GaAs substrate, 2 ...... n-type GaAs active layer, 3 ...... GaAs or AlGaAs surface layer 4 ...... electrode, 5 ...... Si ₃ N ₄ or SiO ₂ or the like of the insulating film, 6 and 7 ...... Photoresist 8 ... Low resistance n ⁺ GaAs for external connection.

Claims (1)

(57) [Claims] 1. An active layer comprising an n-type GaAs conductive layer formed on an insulating substrate; a surface protective layer made of GaAs or GaAlAs having a small conductivity formed on the active layer; A GaAs Hall element comprising: an ohmic electrode formed on the substrate; and an insulating layer covering the surface protective layer.