JP2571296B2 - High reliability and high sensitivity InAs Hall element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a high-sensitivity InAs hole having a structure in which characteristics are unlikely to deteriorate during a manufacturing process, has good temperature characteristics and reliability, and has a small offset voltage. It relates to an element.

[Conventional technology]

Conventionally, an InAs Hall element using a single crystal substrate uses an n-type InAs layer 2 epitaxially grown on a semi-insulating GaAs substrate 1 as a Hall element magnetic sensing part as shown in FIG. On the n-type InAs layer on the surface, an insulating film 5 such as Si ₃ N ₄ or SiO ₂ was formed as a passivation layer in direct contact. For this reason, an insulating film for passivation such as Si ₃ N ₄ or SiO ₂ is formed by a method such as sputtering or plasma CVD, but the basic characteristics such as the output and the resistance value of the Hall element are large depending on the film forming conditions at this time. Instead, it was a major problem in manufacturing. In other words, when the insulating film on the surface is formed, it has the property of changing the crystal characteristics of InAs at the interface with InAs, and as a result, there is a problem that the characteristics of the manufactured Hall element deteriorate. In particular, when an InAs thin film having a high electron mobility is converted into a Hall element to produce a high-sensitivity Hall element, the active layer of the InAs thin film is thin, and this characteristic deterioration is a serious problem.

However, this insulating film is indispensable for obtaining the reliability of the InAs Hall element, and is particularly necessary as a protective film for providing long-term reliability. Therefore, this is a major problem to be solved in fabricating a high-sensitivity InAs Hall element.

[Problems to be solved by the present invention]

FIG. 2 shows the structure of a conventional Hall element. In this case there are n-type InAs active layer 2 on the surface, said layer directly Si ₃ N ₄ and S
This is a structure in contact with an insulating film 5 such as iO ₂ . Therefore, S
In the process of forming an insulating film such as i ₃ N ₄ or SiO _{2 on} the surface, dislocations and point defects are generated on the surface of the active layer, that is, at the interface between the insulating layer and the active layer, and impurities are generated in a subsequent heating process such as annealing. And abnormal diffusion, or thermal denaturation of the active layer surface,
There was a process variation in which the element characteristics deteriorated. When the active layer is thin, the active layer itself may be changed. As a result, the input resistance of the InAs Hall element
The output resistance greatly changed and the Hall output voltage dropped. In particular, when the active layer of InAs is doped with a donor impurity such as Si, S, or Ge to reduce the temperature change of the resistance value and reduce the thickness of the active layer to 0.1 to 0.7 μm, a large decrease in characteristics occurs. Was. Therefore, the present invention provides an InAs Hall element having a thin n-type InAs active layer, in which the active layer is doped with Si, S, Sn, Ge, or the like as a donor impurity, without any deterioration in characteristics in a manufacturing process and at a high yield. High sensitivity, high quality, and high reliability with a structure with less offset
An InAs Hall element is provided.

[Means for solving the problem]

The InAs Hall element of the present invention has been made to solve such a problem. A surface layer made of a semiconductor layer having small conductivity, and a thickness of 0.1 to
It has an n-type conductive layer of 0.7 μm, further comprises an electrically insulating substrate layer in contact with the conductive layer, an ohmic electrode is formed on the n-type InAs conductive layer, and an insulating layer is formed on the surface layer. An InAs Hall element formed, in which Si, S, Sn or Ge is doped as a donor impurity of the conductive layer, and the electron concentration at room temperature is in a range of 4 × 10 ¹⁶ to 1 × 10 ¹⁸ / cm ³ . It is characterized in that it is formed as such.

That is, as shown in FIG. 1, a structure is employed in which the insulating film 5 is not formed directly in contact with the InAs active layer 2 constituting the magnetic sensing part of the Hall element. Electrically inactive In between the active layer and the insulating film.
A structure in which a conductive and small semiconductor layer 3 having good compatibility with the As active layer is formed.

(Operation)

In the conventional structure, the thin InAs active layer 2 itself when the insulating film such as Si ₃ N ₄ or SiO ₂ is formed is damaged, and the electrical characteristics are changed. However, if an element structure like the present invention shown in FIG. 1 is used, when an insulating film such as Si ₃ N ₄ or SiO ₂ is formed, the electrically inactive layer 3 can be damaged, This layer does not contribute to the electrical characteristics of the InAs Hall element. Accordingly, the deterioration of the characteristics of the InAs Hall element manufactured in this step was extremely reduced, and a stable, high-sensitivity InAs Hall element with uniform characteristics could be mass-produced with good reproducibility.

〔Example〕

FIG. 3 shows an embodiment of the high-sensitivity InAs Hall element of the present invention. That is, n-type impurities such as Si, S, Sn, and Ge are added to the surface of the semi-insulating substrate to form a magnetically sensitive portion in an amount of 2 × 10 ¹⁶ to
A 1 × 10 ¹⁸ / cm ³ -doped InAs layer is formed with a thickness of 0.10 to 0.60 μm, and then a GaAs layer not doped with a donor impurity and a layer having no electrical conductivity such as an InGaAs or AlAs layer are formed.
It is formed with a thickness of 20 μm or less to form an inactive semiconductor layer on the surface. This layer is well compatible with an InAs active layer doped with an n-type impurity, and unlike an insulating layer, has little lattice mismatch and does not significantly affect the electrical characteristics of the active layer. Further, in such a structure, what is directly contacted when the insulating film is formed is an electrically inactive layer, and this layer does not contribute to the electrical characteristics of the InAs Hall element. That is, the electrically inactive semiconductor layer formed on the surface acts as a layer for protecting the underlying InAs active layer in the process of forming an insulating film on the surface, and the characteristics of the InAs thin film are extremely deteriorated in the manufacturing process. As a result, the deterioration of the characteristics of the manufactured InAs Hall element is extremely small, and a stable and practically sensitive InAs Hall element with uniform characteristics can be mass-produced with good reproducibility.

The insulating film formed on the surface of the InAs Hall element of the present invention may be any material generally used for passivation of a semiconductor. Particularly, Si ₃ N ₄ , SiO ₂ , Al ₂ O _{3 and the} like are more preferable. The insulating layer is usually 1.
It is formed with a thickness of 0 μm or less, preferably 0.15 to 0.40 μm.

Prototype Example 1 FIG. 3 shows a prototype example in which the MBE method is used and an undoped GaAs layer is used as the surface layer. First, an n-type semiconductor doped with 0.4 μm silicon by MBE on a semi-insulating GaAs substrate 1
An InAs active layer 2 is grown and then 0.1 μm undoped G
An aAs layer 3 was formed at a substrate temperature of 400 ° C., and a semiconductor layer for obtaining the element configuration shown in FIG. 1 was formed (FIG. 3A).

Next, a photoresist 6 is applied, and a predetermined cross-shaped pattern is formed by a photolithography process (FIG. 3 (b)).
The As layer was etched. Thereafter, the resist was removed with a resist stripper to form a magnetically sensitive portion of the Hall element [FIG. 3 (c)].

On this substrate, an insulating film 5 of Si ₃ N ₄ having a thickness of 0.3 μm was formed on the entire surface at 300 ° C. by a plasma CVD method [third.
Figure (d).

Next, a required resist pattern was formed by photolithography to form an electrode portion. Thereafter, the resist was used as a mask to remove the Si ₃ N ₄ of the electrode portion by reactive dry etching using CF ₄ gas and O ₂ gas (FIG. 3E).

Subsequently, the GaAs layer on the surface was removed by etching. Thus, the surface of InAs was exposed. Then, Cu, Ni, Au
An electrode pattern 4 was formed by vapor deposition with a thickness of 0.25 μm, 0.05 μm, and 0.35 μm, and then removing the photoresist and the metal on the photoresist by a lift-off method. Next, in order to completely obtain ohmic contact between the electrode metal and the InAs layer, an alloying treatment was performed in a heating furnace at 400 ° C. for 5 minutes in an N ₂ gas atmosphere. Thus, a large number of InAs Hall elements were formed on one substrate [FIG. 3 (f)].

Thereafter, dicing was performed to separate the individual InAs Hall element pellets. Next, die bonding was performed on a lead frame, transfer molding was performed, and a Hall element entirely molded with epoxy resin was manufactured.

Table 1 shows the characteristics when an InAs Hall element is manufactured by the conventional method and the method according to the present invention. Compared with the conventional method, in the device of the present invention, the Hall device characteristics do not vary, the unbalanced voltage is small, and the design value from the film characteristics is well reproduced, and the sensitivity is high. As for reliability, Table 2 shows the results of the PCT test (pressure cooker test). In the present invention, there is no change in element characteristics, and high reliability is shown.

Prototype Example 2 FIG. 3 shows a prototype example in which the MBE method is used and an undoped AlGaAs layer is used as the surface layer. First, n doped with 0.4 μm silicon on the semi-insulating GaAs substrate 1 by MBE method.
A type InAs active layer 2 was grown, and then a 0.1 μm undoped AlGaAs layer 3 was formed at a substrate temperature of 600 ° C. to form a semiconductor layer for obtaining the device configuration shown in FIG. 1 (FIG. 3A). .

Next, a photoresist 6 was applied to form a predetermined pattern (FIG. 3 (b)), and the InAs layer and the AlGaAs layer on the surface were etched using this as a mask. Thereafter, the resist was removed by an ashing method using O ₂ plasma to form a magnetically sensitive portion of the Hall element [FIG. 3 (c)].

On this substrate, an insulating film 5 of Si ₃ N ₄ having a thickness of 0.3 μm was formed on the entire surface at 300 ° C. by a plasma CVD method [third.
Figure (c)]. Next, a photoresist 7 was applied and a pattern was formed by a photolithography process so that a hole was formed in a portion where an electrode was to be formed. Thereafter, Si ₃ N ₄ on the electrode was removed by reactive dry etching using CF ₄ gas and O ₂ gas using this resist as a mask [FIG. 3 (e)]. Next, the AlGaAs layer on the surface was etched and removed. Thereafter, Cu, Ni, and Au were respectively 0.25 μm, 0.05
Then, the photoresist and the metal on the photoresist were removed by a lift-off method to form an electrode pattern 4. And electrode metal and In
In order to completely obtain ohmic contact with the As layer, alloying treatment was performed in a heating furnace at 400 ° C. for 5 minutes under an N ₂ gas atmosphere.
Thus, a large number of InAs Hall elements were formed on one substrate [FIG. 3 (f)].

Thereafter, dicing was performed to separate the individual InAs Hall element pellets. Next, die bonding was performed on a lead frame, transfer molding was performed, and a Hall element entirely molded with epoxy resin was manufactured.

Table 3 shows the characteristics when an InAs Hall element was produced by the conventional method and the method according to the present invention (average value of 25 elements).
According to the present invention, as compared with the conventional method, the Hall element characteristics do not vary, the unbalance voltage is reduced, and the design value based on the film characteristics is well reproduced, and the sensitivity is high. The reliability is shown in Table 4 with the PCT test and the results (average value of 25 elements). In the present invention, there is no change in element characteristics, and high reliability is shown.

[Effects] As described above, according to the present invention, deterioration of element characteristics hardly occurs in the step of forming an insulating film, and a high-quality Hall element can be produced with good reproducibility. Therefore, stable mass production is possible.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of an InAs Hall element according to the present invention, FIG. 2 is a schematic sectional view of an element according to a conventional method, and FIG.
It is a figure explaining the example of trial manufacture of the present invention by the E method. 1: semi-insulating GaAs substrate, 2: n-type InAs active layer, 3: electrically small and inert semiconductor layer, 4: electrode, 4: insulating film,
6 and 7: photoresist.

Claims (2)

(57) [Claims] 1. An electric device comprising: a surface layer made of a semiconductor layer having low conductivity; an n-type conductive layer having a thickness of 0.1 to 0.7 μm in contact with a lower portion of the surface layer; An InAs Hall element comprising an insulating substrate layer, an ohmic electrode formed on an n-type InAs conductive layer, and an insulating layer formed on the surface layer. 2. The conductive layer according to claim 1, wherein said conductive layer is doped with Si, S, Sn or Ge as a donor impurity, and has an electron concentration at room temperature in the range of 4 × 10 ¹⁶ to 1 × 10 ¹⁸ / cm ³ . Highly reliable and sensitive InAs characterized by being formed as described in
Hall element.