JP2597774Y2 - Hall element - Google Patents

Description

[Detailed description of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetoelectric conversion element comprising a heterojunction, and more particularly to stabilization of the high sensitivity characteristic of the element.

[0002]

2. Description of the Related Art A Hall element is known as one of the so-called magnetoelectric conversion elements which detects a magnetic field and generates an electric signal according to the strength. This Hall element is a kind of magnetic sensor that uses a Hall (Hall) voltage generated by the movement of electrons in the semiconductor constituting the Hall element when a magnetic field is applied as a detection amount. It is used extensively in industry.

As semiconductor materials for the Hall element, in addition to elemental semiconductors such as silicon (Si) and germanium (Ge), elements such as indium antimonide (InSb), indium arsenide (InAs) and gallium arsenide (GaAs) are used. A group III-V binary compound semiconductor obtained by combining an element belonging to Group III of the periodic table with two elements belonging to Group V is also used.

However, looking at conventional Hall elements made of compound semiconductors, there are advantages and disadvantages in the characteristics of Hall elements depending on the physical properties of the semiconductor used. For example, a Hall element composed of GaAs has a relatively small band gap of a GaAs semiconductor and thus has a small temperature change in element characteristics, but has a low electron mobility, and consequently has a lower product sensitivity than a Hall element composed of InSb. There is. On the other hand, I
The nSb Hall element has a large characteristic temperature change due to the low band gap of the InSb semiconductor, but has the advantage of obtaining high product sensitivity.

Recently, the need for precision sensing technology in a high-temperature environment, such as precise rotation control of an automobile engine, has increased, and the device has a capability of outputting a high Hall voltage and has a low change in element characteristics due to temperature. There has been a demand for a new suppressed high-performance Hall element. Here, the Hall voltage depends on the Hall coefficient of the semiconductor material,
The higher the Hall coefficient, the higher the output capability of the Hall voltage.
The Hall coefficient increases in proportion to the mobility of the semiconductor material. Therefore, in order to obtain a high Hall output voltage, that is, to obtain a high-sensitivity Hall element, it is necessary to use a semiconductor material that exhibits high electron mobility.

[0006] For this reason, in consideration of the demand for high-performance Hall elements from the industry, studies have been made on the physical properties of semiconductor materials. More recently, three types of elements have been mixed even in the same group III-V compound semiconductors as before. Attempts have been made to apply a material having a heterojunction composed of a ternary mixed crystal of gallium indium arsenide (GaInAs) and indium phosphide (InP) as a material for a new high-sensitivity Hall element. (Shinobu Okuyama et al., Proceedings of the 53rd Japan Society of Applied Physics, Fall 1992, No. 3 (published by the Japan Society of Applied Physics), 16a-SZC-16, p. 1078). This G
The aInAs Hall element has a relatively small change in characteristics with temperature, and also has excellent product sensitivity because of extremely high electron mobility at room temperature. Hereinafter, as an example of a Hall element having a heterojunction, a Hall element using a GaInAs / InP heterojunction, which is a III-V compound semiconductor, will be described.

[0007] Such a GaInAs Hall element is generally composed of Ga _x In ₁ -x As (x represents a mixed crystal ratio) grown on a high-resistance semi-insulating InP single crystal substrate to which an appropriate amount of Fe is added. The film is configured as a magnetic sensing part. However, simply depositing a Ga _x In ₁ -x As film on a Fe-doped InP single crystal substrate does not necessarily stably impart high electron mobility to the Ga _x In ₁ -x As film. Absent. This is mainly because Fe impurities contained in a high-resistance InP single crystal used as a substrate have a desired Ga content on the InP single crystal.
_{When the X} In _1-X As film is exposed to a certain high-temperature growth environment for epitaxial growth, it is thermally diffused into the Ga _X In _1-X As film growing from the InP single crystal substrate side. Is due. That is, the Fe impurity acts as a so-called electron trap and hinders the movement of electrons, thereby hindering the improvement of the mobility. In order to prevent this, a high-resistance, for example, an InP layer is inserted as a buffer layer between the Ga _x In _1-x As magnetic sensing part film and the InP substrate, and the InP substrate crystal is formed. The propagation of impurities or crystal defects to the magnetic sensing layer is reduced.

[0008] Such an InP buffer layer and Ga _x In
An element is formed from an epitaxial wafer having a so-called hetero junction composed of a layer with a _1-X As magnetic sensing layer and having a so-called hetero junction. In order to form a Hall element, an input electrode for passing an operating current for operating the element and an output electrode for outputting a Hall voltage must be formed so as to be in electrical contact with the magnetosensitive part. Naturally, these input / output electrodes are required to have ohmic properties. In order to impart ohmic properties to an electrode made of a metal film, a heat treatment called alloying is usually applied to the metal electrode deposited on the magnetosensitive layer.

However, the above-mentioned alloying is generally performed at a temperature of 400 ° C. to 500 ° C. for an appropriate period of time. However, although the ohmic property can be given to the electrode by the heating operation at the time of this alloying, A thermal shock is applied to the interface of the heterojunction to cause a defect such as a loss of steepness of the interface. As a result, the electron mobility of the Ga _x In _1-x As magnetic sensing layer is reduced, and the sensitivity is reduced. There is a serious drawback that the realization of the Hall element is hindered.

To prevent such a situation, for example, GaIn
A method is employed in which a low-resistance crystal layer having a high carrier concentration is inserted on the As-sensitive layer and directly below the electrode to form an electrode exhibiting ohmic properties without alloying. I have. A method of forming an ohmic electrode by this method is called a non-alloy contact method because alloying is not required, and gold (Au) which is usually used as an ohmic electrode material for a semiconductor crystal exhibiting an n-type conductivity type is used.・ Germanium (G
e) An ohmic electrode made of a single metal such as aluminum (Al) can be formed without using an alloy.

The low-resistance crystal layer having a high carrier concentration is, for example, a carrier layer having a carrier concentration of 10 ¹⁹ to 10 ²⁰ cm.
^-3 GaInAs layer or InP layer may be used,
In the case of providing such a high carrier concentration layer on the GaInAs layer, from the viewpoint of the occurrence of mutual crystal distortion, etc.
A high carrier concentration layer of InAs is often deposited by an epitaxial growth method. Recently, the ion implantation method has been used, and GaInAs has n
(Si) and selenium (S)
e) Injecting ions such as e) to selectively make the region a high carrier concentration region, and depositing a single metal on the region by a vacuum deposition method, a sputtering (sputtering) method, etc. to form a non-alloy type ohmic electrode. There is also. Regardless of the method of forming the high carrier concentration layer, the conventional Au.Ge
Since the ohmic electrode can be formed of a single metal material instead of the alloy as described above, there is an advantage that variation in contact resistance of the electrode due to, for example, variation in alloy composition at the time of vapor deposition can be reduced.

A Hall element is obtained from a wafer having such a non-alloy ohmic electrode. The element is substantially the same as the conventional Hall element provided with an alloyed electrode, and is a unique method. Does not require. In such a Hall element, a lead wire is generally connected to each of the input / output electrodes, and the input / output electrodes are supported on a desired support and packaged to produce a product. This connection is usually performed by an ultrasonic bonding method or the like, but when bonding the lead wire, considerable mechanical pressure and impact are applied to bond and fix the lead wire to the electrode. And the GaInAs layer existing near the region where the electrode is formed
The heterointerface with P is crystallized, and the GaI
There was a serious drawback that the electron mobility of the nAs magnetic sensing layer was reduced.

For this reason, conventionally, it has been considered to add a bonding electrode, that is, a so-called pad electrode, on the surface of an electrode for input / output. FIG. 1 shows a conventional GaInA having a pad electrode for bonding.
FIG. 1 shows an example of a schematic plan view of an s Hall element. (101) in the figure indicates an input / output ohmic electrode,
(102) denotes bonding pad electrodes provided on the input / output electrodes (101). As shown in the figure, it is a very general technique that the pad electrode (102) has a shape similar to the input / output electrodes, and the shape center point (103) of the pad electrode (102). Exists on the center line (105) in the width direction of the functional portion region (104) of the Hall element composed of the magnetic sensing portion layer. However, at present, merely providing a pad electrode on the magneto-sensitive layer as in the prior art is not, in fact, an effective means for protecting the above-mentioned heterointerface from destruction. As a result of intensive studies on this point, the present inventors cannot easily avoid mechanical shock at the time of bonding to the hetero interface simply by providing a pad electrode for bonding. The present inventors have found that the thickness of the film is more greatly affected by the position of the pad electrode provided on the input / output electrode than by reducing the mechanical shock at the time of bonding by increasing the film thickness.

[0014]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional drawbacks, and has been described in connection with an input / output electrode without destroying a Ga _X In _{1 -X} As crystal layer and a hetero interface with InP. A new method for bonding a lead wire is newly devised, and a high sensitivity Hall element is realized by maintaining the high electron mobility inherent in the GaInAs magnetosensitive layer.

When the bonding pad electrode is provided in electrical contact with the input / output electrodes of the Hall element, the bonding pad electrode is provided in the substrate area other than the magnetic sensing portion, and the bonding pad electrode is provided at the time of bonding. In addition to avoiding such mechanical pressure from being directly applied to the magneto-sensitive part such as the magneto-sensitive part, an ohmic electrode made of a single metal is provided in the hetero junction structure part through a non-alloy ohmic contact layer having a high carrier concentration. An ohmic electrode is formed without going through a heat treatment step to prevent the occurrence of thermal distortion, thereby preventing a decrease in the electron mobility of the magnetosensitive part.

Hereinafter, the present invention will be described using a GaInAs / InP heterojunction Hall element as an example. Usually, GaIn
In forming an As / InP heterojunction Hall element, a high-resistance semi-insulating InP single crystal substrate is used. In practice, an InP single crystal substrate having a specific resistance of 10 ⁶ Ω · cm or more is generally used, and these crystals are formed of a liquid-encapsulated Czochralski (Liquid Encapsulated Czochralski).
ski; LEC) method and recently VB (Vertical Bridgma)
n) It can be easily manufactured by a vertical Bridgman method called a method. Further, when there is a concern that the Fe impurity in the Fe-added InP single crystal adversely affects the electrical characteristics such as the electron mobility of the crystal layer, the InP single crystal is dissolved with hydrochloric acid or the like, and the solution is purified with pure water or the like. The concentration of Fe impurities is quantitatively analyzed by wet instrument analysis such as atomic absorption spectroscopy or high-frequency induction argon plasma spectroscopy, or solid instrument analysis such as secondary ion mass spectrometry. It is sufficient to select crystals having a concentration. Therefore, there is no risk of obstructing the acquisition of an InP substrate crystal having a Fe concentration within a specified range, which is necessary for realizing the Hall element according to the present invention.

On these InP single crystal substrates, an InP layer and a G
a _X In _1-X As layer is deposited to form a heterojunction, but there is no limitation on the order of stacking these epitaxial layers. First, an InP layer is grown on an InP single crystal substrate, and then GaInAs is deposited. Alternatively, they may be deposited in the reverse order. However, usually, in order to improve the electron mobility of the GaInAs layer serving as the magnetic sensing part, GaInAs of Fe impurity from the InP single crystal substrate is used.
Generally, first, InP is generally deposited as a buffer layer on an InP single crystal substrate in order to suppress diffusion into the epitaxial growth layer. By providing this buffer layer, effects such as suppression of propagation of crystal defects and the like to the epitaxial growth layer are produced.
GaInAs without unnecessarily lowering the electron mobility of the layer
Advantages such as the high sensitivity characteristic of the Hall element can be maintained. A low-resistance GaInAs layer having a carrier concentration of 10 ¹⁹ cm ⁻³ is further grown on the wafer having the layer having such a configuration in order to provide a non-alloy ohmic contact.

The above InP buffer layer and GaInA
The growth method of the s layer is not particularly limited, and is, for example, a liquid phase epitaxial growth method (LPE method) or a molecular beam epitaxial growth method (Molecular Beam Epitaxial;
MBE method) or metal-organic thermal decomposition vapor deposition method, so-called MOV
PE (Metal Organic Vapor Phase Epitaxial; MOC)
It may also be called VD method or OMVPE method. ) Method, or MO ・ M combining MOVPE method and MBE method
It is considered that the BE method or the like can be applied. However, at present, the MOVPE method is frequently used for growing semiconductor thin films such as InP containing phosphorus (P) having a relatively high vapor pressure from the viewpoint of stoichiometric composition control rather than the MBE method. In particular, M using cyclopentadienyl indium (C ₅ H ₅ In) having a monovalent valence as a starting material of In
With the OVPE method, normal pressure (atmospheric pressure), which has been considered difficult in the past
Even below, high-quality InP and GaInAs can be obtained. Further, the InP layer is formed, for example, by MOVPE.
The Ga _x In ₁ -x As layer not containing P is grown by the M method.
There is no problem even if the growth method is different for each layer, such as by the BE method, and it is not necessary to provide each layer for forming the heterojunction by only one growth method, and the growth method may be different for each layer. Of course.

Further, the mixed crystal ratio x of the Ga _X In _{1 -X} As
Is preferably set to 0.37 ≦ x ≦ 0.53. Because Ga _x In _1-x lattice-matched to InP
As the mixed crystal ratio of As deviates from the mixed crystal ratio x = 0.47,
The difference between the lattice constants of Ga _X In _{1 -X} As and InP, that is, the degree of lattice mismatch, is also remarkable. This is because the characteristics are also deteriorated, and the characteristics of the Hall element are greatly impaired in improving the product sensitivity.

Further, the Ga _x In _{1-X according to the present invention}
There is no particular limitation on the thickness of the As layer. However, in the actual manufacture of the Hall element, a step called mesa etching for removing a crystal layer in a specific region is generally adopted in order to electrically insulate the elements. Therefore, if the thickness of the layer exhibiting conductivity to be removed by mesa etching and the overall thickness of the epitaxial growth layer increase, the time required for mesa etching necessarily increases, and etching due to the crystal orientation is inevitable. Significant differences in volume as well as in etched shape. This leads to an increase in the unbalance rate, which is one of the important characteristics of the Hall element, which hinders the high quality of the element characteristics and lowers the yield of non-defective elements. Therefore, in forming the heterostructure described in the present invention, good results can be obtained by setting the thickness of the Ga _x In ₁ -x As layer, which is a constituent element thereof, to less than about 5 μm.

Using the epitaxial wafer as described above as a host material, a Hall element having a heterojunction between Ga _x In ₁ -x As and InP is manufactured. In this manufacturing, a region serving as a magnetic sensing portion and an input / output electrode portion is formed by a mesa etching method using a processing technology such as a known photolithography technology and an etching technology. A method for obtaining the mesa structure will be described here. First, Ga _x In _{1 -x} A which is the outermost surface of the base material is used.
A general photoresist material is applied to the surface of the s layer, and thereafter, the resist material is left only in a region for forming an input and output electrode and a region to be a magnetically sensitive portion by a normal photolithography technique. The resist material in the region is peeled and removed. After that, GaInAs using inorganic acid
And the InP layer is etched. By this etching, the electrode forming portion and the magneto-sensitive portion region are trapezoidal when they are viewed from a vertical cross section, so-called mesa shape or inverted trapezoidal shape depending on the axial direction of the crystal, so-called inverted mesa plateau (mesa). As a residual. In the mesa etching, when the total thickness of the growth layer exceeds 5 μm, the difference in the etching shape based on the crystal axis (crystal orientation) becomes remarkable as described above, thereby increasing the unbalance voltage, which is one of the hall element characteristics. , Which leads to a worsening of the imbalance rate.
Therefore, as described above, it is advantageous to set the total thickness of the epitaxial growth layer used for manufacturing the Hall element to approximately 5 μm or less in that the imbalance rate is not increased.

After the mesa etching, input and output electrodes are formed. In this formation, a general photoresist material is applied to the entire surface of the mesa-etched wafer. Thereafter, only the photoresist material in the region where the input / output electrodes are formed is peeled off and removed by a known photolithography method, thereby exposing the surface of the GaInAs layer having a high carrier concentration immediately below. Next, a single piece of Al serving as an electrode material is vacuum-deposited on the processed resist material. Here, Al was used as the electrode material. However, the electrode material is not limited to this, and Au may of course be used. After vacuum deposition of the electrode material, the Al film deposited on the resist material is removed by using a so-called lift-off method while removing the resist material. At this point, the ohmic property is given to the Al electrode without alloying. Incidentally, there is no problem if the shape of these Al electrodes is a rectangular plane, a circle or an ellipse.

In the above description, the element formation region is processed into a mesa shape by mesa etching to electrically insulate it from other regions. However, the insulation between the element region and other regions is limited to this. Instead, for example, nonmetallic ions such as hydrogen and oxygen or ions of a transition metal such as iron may be implanted outside the element formation region to insulate the region. In this case, there is an advantage that the insulation can be achieved without generating a step in the depth direction as in the case of the mesa etching, and the increase in the unbalance voltage of the Hall element can be suppressed.

Further, the entire surface of the wafer on which the electrodes are formed is again covered with a photoresist material, and patterning is performed by using a known photolithography technique to form pad electrodes. This pad electrode is provided in a region other than the element magneto-sensitive function part on each of a total of four electrodes of a pair of input and output electrodes. The bonding pad electrode is arranged at such a position in order to prevent mechanical pressure or the like during bonding from being directly applied to the semiconductor crystal layer constituting the element function part. After patterning is completed, Al is vacuum-deposited on the entire surface, and the Al film deposited on the photoresist material other than the pad electrode formation region is removed again by the lift-off method. In this pad electrode formation region, the thickness of the Al film is naturally thicker than in other electrode regions.

Next, silicon dioxide (SiO ₂ ) having an insulating property is deposited by a known plasma CVD method to cover the wafer surface. In the present invention, general SiO ₂ is used as the insulating coating film, but another insulating film such as silicon nitride (SiN) may be used. Next, the SiO ₂ insulating film manufactured as described above is covered with a general resist material. Thereafter, the resist material at a portion corresponding to a position for forming a dicing line necessary for so-called dicing, which separates the pad electrode portion and the individual elements, is removed by a known photolithography technique. The immediately underlying SiO ₂ insulating film is exposed. In addition, the exposed Si
The O ₂ insulating film is immersed in hydrofluoric acid (chemical formula HF) to dissolve and remove the SiO ₂ insulating film in the relevant portion. As a result, the surface of the GaInAs layer is exposed on the surface of the input / output electrode and the portion where the dicing line is formed. In actual separation into individual elements, the GaInAs layer exposed at a portion corresponding to the dicing line may be removed by etching using an appropriate inorganic acid. After that, GaIn
The InP layer immediately below the As layer is also removed with an inorganic acid. Usually, etching is further advanced to remove a part of the surface layer of the InP single crystal substrate. This is done in order to reduce in advance that a scriber or a blade used for dicing mechanically damages the epitaxial growth layer or the hetero interface at the time of element isolation. The formation and processing steps of the above-described insulating film and the formation and processing method of the dicing line are not changed irrespective of the insulating method such as mesa etching or ion implantation.

After the above processing, known scribing is performed along the dicing line to separate the manufactured Hall elements into individual Hall element chips. Thereafter, one element chip is mounted on a metal support, and the lead terminals attached to the support and each electrode pad are connected to each other by ultrasonic bonding using a general lead wire. After that, the connected chip is surrounded by a general semiconductor sealing epoxy resin, and is surrounded (molded).

The main electrical characteristics of the new GaInAs Hall element according to the present invention, especially the product sensitivity, are the same as those of the conventional GaInAs Hall element.
These were compared with those of the As Hall element. As a result, a remarkable difference was recognized in the product sensitivity, which is an important characteristic that determines the superiority or inferiority of the Hall element.
In the nAs Hall element, the product sensitivity was remarkably improved. The reason for this is that, as described in the present invention, a factor that could mechanically damage the GaInAs / InP hetero interface that exhibits high electron mobility was eliminated as much as possible from the manufacturing process of the Hall element. Is determined.

By a simple method of providing a bonding pad electrode at a specific position of an input / output electrode, it is possible to avoid direct application of mechanical pressure to a heterojunction interface, and to provide a high carrier concentration through a non-alloy ohmic contact layer. The formation of ohmic contacts made of a single metal without heat treatment avoids the occurrence of thermal distortion and enables the stable realization of highly sensitive Hall elements without impairing the high electron mobility of the heterojunction. I do.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below based on embodiments. FIG. 2 shows an example of a schematic plan view of a GaInAs / InP heterostructure Hall element according to the present invention. Also,
FIG. 3 is a schematic cross-sectional view of the Hall element shown in FIG. 2 in a vertical direction along a broken line AA ′. (201) in FIG. 2 is a semi-insulating InP single crystal having a plane orientation (100) obtained by adding iron (Fe) used as a substrate in forming the hetero junction. The thickness of the InP single crystal (201) was about 350 μm. In this embodiment, a crystal having a specific resistance of about 10 ⁷ Ω · cm was used. In the figure, reference numeral (202) denotes an undoped (undoped) InP buffer layer having a thickness of about 100 nm, which is epitaxially grown on a crystal substrate (201) by MOCVD under normal pressure using C ₅ H ₅ In as an In source. . The buffer layer (202) was grown at a temperature of 610 ° C. Further, an n-type Ga having a mixed crystal ratio of 0.47 and a thickness of about 400 nm is formed on the InP buffer layer (202).
_{A 0.47} In _0.53 As epitaxial magnetosensitive layer (203) was provided by a normal pressure MOCVD growth method. This Ga _0.47 In _0.53
The growth temperature of the As-sensitive layer (203) is also controlled by the buffer layer (20).
It is 610 ° C as in 2). Ga _0.47 In _0.53
The carrier concentration is 2 × 10 ¹⁹ on the As magnetic sensing layer (203).
Ga having a thickness of 120 nm exhibiting n-type conduction of cm ⁻³
_{A 0.47} In _0.53 As high carrier concentration layer (204) was provided. This is because, as described in the text, a non-alloy ohmic contact can be easily formed using a single metal instead of a conventional alloy. The InP buffer layer (202) and the n-type GaInAs magnetosensitive layer (203)
Have a carrier concentration of 2 × 10 ¹⁵ cm ⁻³ and 2 × 10
It was ¹⁶ cm ^-3 . The epitaxial layer (202-2)
No. 04) was grown by the MOCVD method described above.

As described above, the wafer having such a structure is firstly subjected to the well-known photolithography method and the etching method to first form an element function portion region (2) which exhibits the function of the Hall element.
05) was subjected to mesa etching to leave a trapezoidal (mesa) shape to form a mesa region including a magnetically sensitive portion and the like. Thereafter, the surface of the wafer is covered with a general photoresist material, and through a process such as patterning and resist peeling lift-off, high-purity Al is applied to form an input and output electrode by about 60%.
Vacuum evaporation was performed to a thickness of 0 nm, thereby forming ohmic input / output electrodes (206). All of these electrodes (206) have the same shape, and the plane has a long side of about 200 μm.
m is a rectangle with a short side of about 70 μm.

Next, the surface of the wafer is covered again with a general photoresist material, and a region where a pad electrode (207) having a rectangular plane is to be formed, that is, a region as shown in FIG. The surface of the input / output electrode (206) was exposed only in this area. In the present invention, unlike the related art, the center point (20) of the pad electrode (207) is different.
8) is a center line (2) in the width direction of the semiconductor magneto-sensitive layer (209) which is orthogonal to each other and forms the element function part region (205).
10) Arranged so as not to be positioned above. Thereafter, high-purity Al was vacuum-deposited again to form a pad electrode (207) in a region other than the magneto-sensitive layer (209). The total film thickness including the pad electrode portion reached about 1500 nm.

Further, the entire surface of the wafer was once covered with an SiO ₂ insulating film (211) by a plasma CVD method. The thickness of the SiO ₂ film (211) was about 300 nm. Next, a general photoresist material is applied on the insulating film (211),
The surface of the pad electrode (207) was exposed for electrical connection later through the photolithography and patterning steps as described above. A dicing line (21) is used to separate the individual Hall elements by continuing the process.
2) was formed. After that, dicing line (212)
Was scribed along the line, and separated into individual elements (chips). In forming the chip, a part of the back surface of the InP single crystal substrate (201) is removed by etching to reduce the thickness of the substrate from the initial thickness of 350 μm to about 13 μm.
The thickness was set to 0 μm, and scribing was facilitated.

After scribing into chips, the chips are mounted on a very common metal frame,
Thereafter, one end of the lead wire was bonded to a pad electrode by an ultrasonic bonding method, and the other end of the lead wire was connected to a lead terminal attached to a metal frame. After such a connection operation, the Hall element was surrounded and molded with an epoxy resin generally used for sealing a semiconductor element.

The Hall element prepared as described above was subjected to electrical characteristics evaluation. The conventional Ga
The characteristics of the InAs Hall element were also evaluated. Here, the conventional Hall element is one in which the pad electrode is located substantially on the extension of the element function part. However, the thickness of the InP buffer layer is the same as 100 nm in both cases. Among the results of the comparison of the characteristics, a remarkable difference was observed between the new Hall element according to the present invention and the conventional Hall element, particularly at room temperature electron mobility which directly affects the sensitivity of the Hall element.
As shown in FIG. 4, in the new Hall element based on the present invention, the room-temperature electron mobility hardly changes from the room-temperature mobility in an unprocessed wafer state which has not been subjected to the element conversion step, whereas In the Hall element, the room temperature mobility was reduced by about 15 to 20% from the state of the unprocessed wafer as the element manufacturing process was performed. As a result of step-by-step investigation of the cause of the decrease in room temperature mobility, no change was observed in room temperature mobility in both the present invention and the conventional example until the non-alloy Al electrode was formed. However, at the end of the bonding step, the above differences were clearly apparent. In this regard, as a result of investigating the cause from the viewpoint of the introduction and generation of crystal defects, a large amount of defects such as dislocations due to bonding in the conventional Hall element having a conventional bonding pad arrangement were found inside the GaInAs crystal layer, and The induction and introduction at the hetero interface with the InP layer was confirmed by observation of a vertical cross section of the wafer with a high-resolution transmission electron microscope. On the other hand, in the case of the present invention, in the GaInAs crystal layer immediately below the bonding pad, crystal defects are introduced almost in the same manner as in the conventional example, but it is important for exhibiting device characteristics. It has been found that dislocations and the like are hardly introduced into the element functional portions.
Taking these experimental facts into account, the extreme decrease in room temperature mobility observed in conventional Hall elements is related to crystal defects induced by mechanical pressure during bonding. In order to mitigate the adverse effects of induced crystal defects on the mobility, bond pads should be arranged as in the present invention to avoid the direct introduction of crystal defects into the element function part. Clearly has a significant effect.

In the above embodiment, GaInAs / In
Although the present invention has been described by taking the P heterojunction Hall element as an example, the present invention is not limited to the GaInAs / InP heterojunction Hall element, but includes, for example, GaAs and aluminum gallium arsenide (AlGaAs) or aluminum indium arsenide. The present invention can also be applied to a Hall element or the like including a heterojunction of (AlInAs) and GaInAs.

By adding a new idea to the structure and arrangement of the pad electrode for bonding, it is possible to avoid the influence of crystal defects due to stress strain induced and introduced during the device fabrication process on the device functional portion, and A new Hall element maintaining high sensitivity characteristics can be obtained.

[Brief description of the drawings]

FIG. 1 is a schematic plan view of a conventional GaInAs Hall element.

FIG. 2 is a schematic plan view of the GaInAs Hall element according to the present invention.

FIG. 3 is a schematic cross-sectional view of the Hall element shown in FIG. 2 in a vertical direction along a broken line AA ′.

FIG. 4 is a diagram showing a change in room-temperature electron mobility of a GaInAs Hall device according to the present invention and a conventional example before and after device fabrication.

[Explanation of symbols]

(101) Ohmic input / output electrodes (102) Bonding pad electrode (103) Center point of the shape of the bonding pad electrode (104) Mesa-shaped element functional area (105) Element functional area (201) InP semi-insulating single crystal substrate (202) Undoped InP buffer layer (203) Magnetic sensing layer (204) High carrier concentration layer (205) Processed in a mesa shape (206) Ohmic input / output electrode (207) Bonding pad electrode (208) Center point of the shape of the bonding pad electrode (209) the semiconductor layer (210) the center line in the width direction of the semiconductor layer constituting the functional part of the device (211) SiO ₂ insulating film (212) dicing line comprising

Continuation of front page (56) References JP-A-61-20378 (JP, A) JP-A-1-239489 (JP, A) JP-A-62-2268 (JP, U) JP-A-6-70262 (JP , U) Shinobu Okuyama, et al., "Highly Sensitive Hall Devices Using GaInAs / inP Heterojunction Epi-Wafer", Proceedings of the 53rd Autumn Meeting of the 19th Applied Physics Society of Japan, No. 3, 16a-SZC -16, p. 1078 (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 43/06 G01R 33/07

Claims (1)

(57) [Scope of request for utility model registration] In a Hall element having a heterojunction structure as a magnetic sensing portion, an ohmic electrode made of a single metal is provided on the heterojunction structure via a non-alloy ohmic contact layer having a high carrier concentration. A heterojunction Hall element wherein the ohmic electrode is drawn to a region other than the heterojunction structure, and a bonding pad electrode is provided on the ohmic electrode drawn to a region other than the heterojunction structure.