JP3395277B2 - Magnetoelectric conversion element - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Hall element having a heterojunction, and particularly to achieving high sensitivity.

[0002]

2. Description of the Related Art A Hall element is known as one of so-called magnetoelectric conversion elements which detects a magnetic field and generates an electric signal according to the strength thereof, that is, the magnetic field strength. This Hall element is a kind of sensor that uses the Hall voltage generated by the movement of electrons in the semiconductor known as the Hall effect when a magnetic field is applied as a detection amount, and rotates with magnetism as a detection target. Widely used in industry as a detection sensor, position detection sensor, etc.

Semiconductor materials for Hall elements include elemental semiconductors such as silicon (Si) and germanium (Ge), as well as elements such as indium antimonide (InSb), indium arsenide (InAs) and gallium arsenide (GaAs). A III-V group binary compound semiconductor formed by combining elements belonging to a Group V element similar to Group III of the periodic table is also used. However, looking at a conventional Hall element made of a compound semiconductor, there are advantages and disadvantages in the characteristics of the Hall element depending on the physical properties of the semiconductor used. For example, a Hall element made of GaAs has a relatively small change in temperature characteristics of element characteristics due to a relatively large band gap of a GaAs semiconductor, but conversely has a slightly low electron mobility and thus has a product sensitivity of InSb.
It has a drawback of being lower than the Hall element made of.
On the other hand, the InSb Hall element has an advantage that a high product sensitivity can be obtained although the characteristic temperature change is large because the band gap of the InSb semiconductor is low.

Recently, the need for precision sensing technology in high temperature environments, such as precise rotation control of automobile engines, has increased, it has the ability to output a high Hall voltage, and the change in element characteristics due to temperature is low. There has been a demand for new high-performance Hall elements that are suppressed. Here, the Hall voltage depends on the Hall coefficient of the semiconductor material, and the higher the Hall coefficient, the higher the Hall voltage output capability. Moreover, this Hall coefficient increases in proportion to the electron mobility of the semiconductor material. Therefore, in order to obtain a high Hall output voltage, that is, to obtain a highly sensitive Hall element, it is necessary to use a semiconductor material exhibiting a high electron mobility.

For this reason, studies have been conducted from the viewpoint of the physical properties of semiconductor materials, and in recent years, so-called two-dimensional confinement has been proposed.
A Hall element utilizing a high electron mobility characteristic manifested by a two-dimensional electron gas has also been proposed (Japanese Patent Publication No. 3-25035). However, such a two-dimensional electron has conventionally been generated by Si semiconductor and silicon dioxide (S
It is known to appear at the heterojunction interface with iO ₂ ). So-called SiMOS (metal-oxide-semiconducto
A Hall element using two-dimensional electrons expressed by r) structure was already reported in 1966 (Solid-State El
ectronics Vol.9 P.571 ~ P.580). Furthermore, SiMO
A theoretical study of Hall elements with S-structure has also been conducted (Solid-State Electronics Vol.17 1974 P.1039-1.
043). In addition to the manifestation of two-dimensional electrons due to the MOS structure described above, gallium arsenide / aluminum arsenide (AlGaA) formed by mixing three kinds of elements in a III-V group compound semiconductor is also used.
s) or gallium arsenide / indium arsenide (GaInAs) or other compound ternary mixed crystal, a method of forming a two-dimensional electron gas by a heterojunction is also known (Japanese Patent Publication No. 59-5371).
4). A heterojunction for obtaining a two-dimensional electron gas formed by a heterojunction based on such a known combination is composed of an intrinsic semiconductor and an N-type semiconductor having a bandgap higher than that of the intrinsic semiconductor. Has been done.
A field effect transistor is known as such a semiconductor device.

As a combination that develops such a two-dimensional electron gas, a heterojunction of GaInAs and InP is known (USP 4,163,327). Furthermore, as an intrinsic semiconductor forming a heterojunction, not only the above compound semiconductor but also a single semiconductor such as germanium is mentioned.
It is said that a three-dimensional electron gas can be obtained. If a heterojunction is simply formed on the basis of such a combination of semiconductor materials having different electron affinities, it is not always possible to stably obtain a high electron mobility by a two-dimensional electron gas. To explain this, the Schottky junction type high electron transfer type transistor utilizing the above-mentioned heterojunction of AlGaAs and GaAs will be taken as an example. For this transistor, electron mobility is a factor that influences important transistor characteristics such as transconductance and noise figure. However, high electron mobility cannot always be stably obtained simply by forming a heterojunction. This depends on the steepness of the hetero interface whether or not the two-dimensional electron gas exists, but even if the two-dimensional electron gas exists, high electron mobility is hindered by factors such as electron scattering. Because there is. Therefore, conventionally, an undoped AlGaAs layer has been inserted at the heterojunction interface between GaAs having a large electron affinity and AlGaAs having a smaller electron affinity. This undoped layer is generally called a spacer layer and is made of AlG.
Not limited to aAs / GaAs heterojunction system, AlInAs
It was also provided as a base material for a high electron mobility transistor composed of a / GaAs heterojunction.

However, although the influence of factors that hinder the high mobility characteristics of two-dimensional electrons, such as electron scattering, can be mitigated by inserting the spacer layer, the thickness of the spacer layer, the sheet carrier concentration, and the electron mobility are reduced. Since it is sensitively affected, on the contrary, precise control of the film thickness of the spacer layer is required, resulting in adding complexity to the thin film manufacturing process. Attempts have been made to insert spacers not only in transistors but also in Hall elements. For example AlGa
High-resistance AlGaAs is used as a spacer in a heterojunction Hall element composed of As and GaAs (Journal of the Institute of Electronics, Information and Communication Engineers Vol. J70-C No. 5 1987).
Also, in the heterojunction Hall element of GaInAs and AlInAs, high resistance AlInAs is used as a spacer (Technical Digest of The 11th Sensor).
Symposium 1992). In both cases, the spacer layer thickness is 10n
It is a very thin film having a thickness of less than m and usually about 2 to 5 nm. In order to stably obtain such an ultrathin film layer, a dense and elaborate growth technique is required, and it is determined by this technique whether a desired high electron mobility can be obtained, that is, by a two-dimensional electron gas. The yield of the high-sensitivity Hall element will be affected. Further, a high-sensitivity Hall element (Japanese Patent Publication No. 3-25035) using a heterojunction in which GaInAs is an N-type semiconductor and InP is an intrinsic semiconductor, and conversely, GaInAs is used as an intrinsic semiconductor,
A high-sensitivity Hall element using nP as an N-type semiconductor (Proceedings of the Japan Society of Applied Physics, 1992) has also been reported. Unlike the conventional Hall elements, these Hall elements employ a technique of directly forming a heterojunction without using a spacer.

[0008]

However, GaInAs /
Even in the high-sensitivity Hall element utilizing the high electron mobility achieved by the InP-based heterojunction, desired high-sensitivity characteristics are not always stably obtained. This is because the factors that cause high electron mobility in heterojunctions have not been clarified in detail, and the requirements necessary for stable formation of heterojunctions have not yet been clarified. The present invention has been made to overcome such a situation, and clarifies the requirements that a base material containing a GaInAs / InP heterojunction must have in order to exert its high-sensitivity characteristics unfailingly and stably. It is intended to overcome the conventional drawbacks.

[0009]

The present invention does not use a spacer made of a heterogeneous semiconductor film for a heterojunction as in the prior art, but provides a strained layer in a semiconductor layer forming the heterojunction and provides the strained layer. By limiting the region in which is present to a specific range, high electron mobility characteristics are exhibited. A technique for obtaining a high electron mobility characteristic by interposing a strained layer at the interface of a heterojunction has already been completed for a field effect transistor. This transistor is usually pseudomor
It is called a phic transistor and is used as an element for low-noise signal amplification. Looking at the constituent elements of this type of base material for transistors, it is common to have a GaInAs layer elastically confined on a GaAs layer and further include a heterojunction in which AlGaAs is deposited.
The AlGaAs layer deposited on the GaAs layer is naturally limited in thickness because it is necessary to confine strain, and is usually set to about 10 nm. That is, strain is present over the entire AlGaAs layer. On the other hand, in the present invention, the strained layer is present in the semiconductor layer forming the heterojunction, and the strained layer is present in a region within 20% of the film thickness of the magnetic sensing part layer from the heterojunction interface, whereby high electron It has become possible to exhibit mobility characteristics in a stable manner.

First, in order to suppress diffusion of Fe impurities from the InP single crystal substrate on the InP single crystal substrate, In
It is common to deposit P as a buffer layer. By providing this buffer layer, the effect of suppressing the propagation of crystal defects and the like to the epitaxial growth layer is produced. Further, the buffer layer is not limited to InP, and other materials such as aluminum arsenide and indium may be used.

On the InP buffer layer, Ga _x becomes a magnetically sensitive portion.
Deposit In _1-x As layer. The mixed crystal ratio x of Ga _x In _1-x As is preferably 0.37 ≦ x ≦ 0.57. Because Ga _x In lattice-matched to InP
As the mixed crystal ratio deviates from the mixed crystal ratio x = 0.47 of _1-x As,
The difference in lattice constant between Ga _x In _1-x As and InP, that is, the degree of lattice mismatch becomes remarkable, which induces a large amount of crystal defects and the like, which leads to the deterioration of crystallinity and the electrical mobility such as the decrease of electron mobility. This is because the characteristics are also deteriorated and the characteristics of the Hall element greatly hinder the improvement of the product sensitivity.

The carrier concentration of the Ga _x In _1-x As layer is 1 × 10 ¹⁵ c in order to exhibit high electron mobility.
Good results are obtained in the range of m ⁻³ or more and 1 × 10 ¹⁷ cm ⁻³ or less. If the carrier concentration is less than 1 × 10 ¹⁵ cm ⁻³ , the ohmic characteristics of the input and output electrodes will become more unstable and the electrode resistance will increase when a Hall element is used.
This is because it causes instability of device characteristics. On the other hand, 1 × 10
^If it exceeds ¹⁷ cm ^-3 , the electron mobility will be remarkably reduced, and a high-sensitivity Hall element cannot be obtained.

There is no particular limitation on the film thickness of the Ga _x In _1-x As layer. However, in the actual fabrication of the Hall element, a process for removing the crystal layer in a specific region called mesa etching is generally adopted in order to electrically insulate the elements from each other. Therefore, if the film thickness of the conductive layer that should be removed by mesa etching, or even if the overall thickness of the epitaxial growth layer is increased, the time required for mesa etching is inevitably increased. It causes a significant difference in the amount and the etching shape. This leads to an increase in the unbalance rate, which is one of the important characteristics of Hall elements,
This hinders the improvement of device characteristics and lowers the yield of non-defective devices. Therefore, in constructing the heterostructure described in the present invention, good results can be obtained by setting the total film thickness of the Ga _x In _1-x As layer and the InP layer, which are the constituent elements, to be less than approximately 5 μm.

Next, by providing a strained layer inside the Ga _x In _1-x As layer, higher electron mobility can be achieved. As a result of intensive studies by the present inventor, it is preferable to apply strain to the region within 20% of the Ga _x In _1-x As layer thickness from the heterojunction interface. The results of the inventor's experiment are shown in FIG. FIG. 3 shows the relationship between the electron mobility at room temperature and the ratio of the thickness of the strained layer to the total thickness of the magnetosensitive layer in the heterojunction between the Ga _0.47 In _0.53 As layer and the InP layer. . As shown in FIG. 3, when the film thickness exceeds 20% of the total film thickness, the electron mobility becomes extremely low.

There are several methods for providing a strained layer in a region within a certain range from the heterojunction interface. For example, InP
The buffer layer is epitaxially grown, and then the Ga _x In _1-x As layer to be the magnetic sensing layer is epitaxially grown.
The strained layer can be formed relatively easily by appropriately adjusting the cooling rate in the subsequent cooling process. That is,
It takes about 20 minutes to cool the InP layer and the Ga _x In _{1 -x} As layer in the MOVPE method from the normal growth temperature of around 600 ° C to 200 ° C. That is, 2 per minute
When cooled at a cooling rate of around 0 ° C., strain can be generated relatively easily. When the cooling rate is further increased, the region where strain exists tends to widen. For example, the cooling rate is 3
At around 5 ° C., the area where strain exists reaches 40%. As a method of generating strain, the mixed crystal ratio of the Ga _x In _1-x As layer is gradually changed from the heterojunction interface, and finally the In
It may be x = 0.47, which is lattice-matched with P. However, in this case, if an extremely thick layer having a different mixed crystal ratio is interposed, the region where strain exists exceeds the appropriate range, so the thickness of the layer having a different mixed crystal ratio should be kept at 10 nm at the maximum.

FIG. 4 shows the relationship between the sheet resistance and the room temperature electron mobility of an epitaxial wafer having a heterojunction having a strained layer therein thus obtained. Here, the thickness of the entire magnetic sensing part layer is 150 nm, and as a result of observation with a transmission electron microscope, the range where the strained layer is present is about 1 from the heterojunction interface.
The range is 6 nm, which corresponds to about 10% of the total thickness of the magnetic sensing layer. Further, FIG. 4 also shows a wafer corresponding to FIG. 3 in which the intervening region of strain is 20% to 40% of the entire thickness of the magnetic sensing part layer. According to FIG. 4, the electron mobility was 8,000 cm ² / V · S in the past regardless of the sheet resistance value.
According to the present invention, the sheet resistance is 1,000 to 1,500Ω.
/ □ has an electron mobility of 10,000 cm ² / VS
A product of 12,000 cm ² / V · S can be obtained.

Next, a GaInAs Hall element is manufactured using the epitaxial wafer composed of the InP buffer layer and the GaInAs magnetic sensitive layer grown on the InP single crystal substrate as described above as a base material. In this fabrication, well-known processing techniques such as photolithography technology and etching technology are used, and so-called mesa etching is performed on the GaInAs magnetic sensitive layer and the InP buffer layer that exhibit the function as the Hall element, so that the element functional region is mesa-shaped. To process. Crosses in a cross shape when processing this mesa 2
The two semiconductor thin mesa layers are <0 bar 1 each orthogonal to each other.
1> and <0 bar 1 bar 1> direction.

After performing such mesa etching, input and output electrodes are formed. In this formation, a general photoresist material is applied to the entire surface of the mesa-etched wafer. After that, the region where the electrode is to be formed is patterned (patt) by a known photolithography method.
erning), only the photoresist material in the region where the input / output electrodes are formed is peeled and removed to expose the surface layer of the GaInAs layer of the magnetic sensing portion layer immediately below.

Next, gold (elemental symbol: Au) used as an electrode material
-Germanium (elemental symbol: Ge) alloy is vacuum-deposited on the processed resist material. Next, the surface of the wafer is coated with a silicon dioxide (SiO ₂ ) film having an insulating property as a passivation film by a known plasma CVD method. The silicon dioxide insulating film manufactured as described above is covered with a general resist material. After that, a dicing line necessary for dicing is formed. The resist material in the portion corresponding to the predetermined position is removed by a known photolithography technique to expose the SiO ₂ insulating film immediately below. Further, the exposed SiO ₂ insulating film is hydrofluoric acid (chemical formula:
HF) to dissolve and remove the SiO ₂ insulating film at the relevant portion. This exposes the surface of the input / output electrode and the surface of the GaInAs layer at the portion where the dicing line is formed. The GaInAs layer exposed at the portion corresponding to the dicing line may be removed by etching using a suitable inorganic acid. After that, I directly under the GaInAs layer
The nP layer is removed with an inorganic acid. Usually, etching is further advanced to remove a part of the surface layer of the InP single crystal substrate.

[0020]

By providing a strained layer in the Ga _x In _1-x As layer within a certain range of distance from the heterojunction interface, the electron mobility of the heterojunction is improved.

[0021]

EXAMPLES The present invention will be described in detail based on examples. Figure 1
FIG. 3 is a schematic plan view of a Hall element having a GaInAs crystal layer as a magnetic sensing part according to the present invention. 2 is a schematic view of a vertical cross section along the direction of the broken line AA ′ in the schematic plan view shown in FIG. In forming an epitaxial wafer, a semi-insulating high-resistance InP single crystal substrate (10) having a plane direction (100) with a specific resistance of about 10 ⁶ Ω · cm added with iron was used.
1), an undoped InP layer (102) as the first layer
Were grown to a thickness of about 100 nm. This InP layer (1
As a result of measuring the carrier concentration of No. 02) by the Hall effect method, it was about 2 × 10 ¹⁵ cm ⁻³ .

Then, 250 nm of undoped n-type Ga _0.47 In _0.53 As (103) with a carrier concentration of 2 × 10 ¹⁶ cm ^-3 and a mixed crystal ratio of 0.47 is formed on the InP crystal layer (102). Deposited to a thickness of. A spacer is not inserted here as in the conventional case, and the InP buffer layer (10
2) and Ga _0.47 In _0.53 As (103) were directly heterojunctioned. In this example, both the InP and GaInAs crystal layers were grown by the atmospheric pressure MOVPE method using cyclopentadienylindium (chemical formula: C ₅ H ₅ In) having a valence of 1 as the In source. The growth temperature is 61
It is 0 ° C. After the epitaxial growth is completed, the range from the growth temperature of 610 ° C. to 200 ° C. is set to 20
It was cooled over a period of time, that is, at a cooling rate of about 20 ° C. per minute.
In this case, when observed with a transmission electron microscope, the strained layer exists within a range of 20 nm from the heterojunction interface.
This corresponds to about 13% of the total thickness of the s layer of 150 nm.

Next, the GaInAs magnetic sensitive layer (103) is entirely coated with a normal organic photoresist material, and then,
By using well-known photolithography technology and etching technology, the region (104) to be formed with the input / output electrodes and the magnetically sensitive portion was processed into a mesa shape. In this example, an inorganic acid was used for the mesa etching process. Then G
The entire surface of the aInAs layer (103) was again covered with the organic resist material. Next, a pair of input electrodes (1
05) and the resist material existing in the region where the output electrode (106) is to be formed were removed by photolithography to expose the surface of the GaInAs layer (103). After that, Au / G containing about 13% by weight of Ge
The e alloy was vacuum deposited. After that, the wafer is dipped in an organic solvent mixed solution, the resist material is peeled off, and at the same time, it is not necessary for manufacturing an element deposited on the resist material by vapor deposition.
The u.Ge alloy film was removed by a so-called lift-off method. Next, the wafer to which an alloy film to be an electrode was applied to obtain an ohmic electrode was heat-treated at a temperature of 420 ° C. for several minutes.

Further, a pad electrode (107) is provided on each electrode in electrical connection with the input / output electrodes (105 and 106). The pad electrode (107) was placed on the surface layer portion of the InP single crystal substrate (101) exposed by the mesa etching as described above. This is Ga during heat treatment
This is to prevent the strain from being directly introduced into the InAs magnetic sensitive layer. Further, a region other than the input / output electrode portions on the surface of the heterojunction material which has undergone the above steps was covered with a silicon dioxide film (108) by using a plasma CVD method. The deposited film thickness of the oxide film was about 400 nm. Further, the entire surface of the element was covered with a general photoresist material again, and patterning was performed to form a dicing line (110) for separating the Hall element formed on the entire surface of the wafer into individual Hall element chips. . After that, each layer was sequentially removed by etching to form a dicing line (110).

The electrical characteristics of this Hall element, especially the electron mobility, were compared with those of the conventional GaInAs Hall element. Results are shown in FIG. The conventional Hall element here means that the thickness of the strained layer existing in the buffer layer and the magnetic sensitive layer is about 52 nm, which is about 35% of the total layer thickness of Ga _x In _1-x As.
/ InP heterojunction Hall element. As a result, in the Hall element according to the present invention, the average electron mobility at room temperature reaches 10,000 cm ² / V · S, whereas in the conventional example, there is a difference of about 6,100 cm ² / V · S from about 40%. ,
The superiority of the present invention has been demonstrated.

[0026]

According to the present invention, a high electron mobility characteristic can be stably imparted, and a highly sensitive Hall element can be stably supplied.

[Brief description of drawings]

FIG. 1 is a schematic plan view of a Hall element according to the present invention.

FIG. 2 is a broken line A- of the schematic plan view of the Hall element shown in FIG.
It is a figure which shows the cross section along A'typically.

FIG. 3 is a diagram showing a relationship between room temperature electron mobility and a ratio of strain to the film thickness of the entire magnetic sensing part layer.

FIG. 4 is a diagram showing the relationship between the sheet resistance of a heterojunction and room temperature electron mobility.

FIG. 5 is a diagram comparing electron mobilities of an example of the present invention and a conventional example.

[Explanation of symbols]

(101) Fe-added high-resistance InP single crystal substrate (102) InP buffer layer (103) GaInAs magnetic sensitive layer (104) Mesa area (105) Input electrode (106) Output electrode (107) Pad electrode (108) Oxide film (109) Dicing line

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-60-198877 (JP, A) JP-A-63-1464 (JP, A) JP-A-4-298050 (JP, A) JP-A-5- 218528 (JP, A) JP 4-106988 (JP, A) JP 64-2384 (JP, A) JP 54-114089 (JP, A) JP 7-79032 (JP, A) International Publication 93/2479 (WO, A1) Electrotechnical Laboratory News, Vol. 511, pp. 6-10 1992 Autumn Proceedings of 53rd Annual Meeting of the Society of Applied Physics, No. 3, p. 1078 (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 43/06 H01L 21/338 H01L 29/778 H01L 29/812 JISST file (JOIS)

Claims (3)

(57) [Claims] 1. A Hall element comprising a heterojunction of a III-V group compound semiconductor, wherein a strained layer is formed in a region within 20% of the film thickness of the magnetic sensing part layer from the heterojunction interface in the magnetic sensing part layer. Hall element characterized by being present. 2. The magnetic sensing layer is gallium indium arsenide (G).
The hall element according to claim 1, which is made of aInAs). 3. A heterojunction comprising gallium indium arsenide (GaInAs) and aluminum indium arsenide (A).
(1InAs) or gallium indium arsenide and indium phosphide (InP).