JPH05291644A - Gaas hall element and its fabrication - Google Patents

Abstract

PURPOSE:To improve the unbalanced voltage characteristics of GaAs Hall element, the output characteristics obtained when a magnetic field is applied, etc., by appropriately forming the buffer layer. CONSTITUTION:An undoped GaAs buffer layer 11 is formed on a semi-insulating GaAs wafer 10 by a molecular beam epitaxial method at a growth temperature below 400 deg.C. A GaAs Hall element is formed on a buffer layer 11 by sequentially forming an N-type GaAs layer 12 and an N<+>-type GaAs layer 13. With this, the ratio of the content of As to the content of Ga in the buffer layer 11 becomes greater than 1, and a deep level which is formed in the buffer layer 11 by the presence of excess As causes the buffer layer 11 to exhibit very high resistance characteristics. As a result, a leak current that flows from the N-type GaAs layer 12 formed on the buffer layer 11 as an active domain to the buffer layer 11 is reduced, and the unevenness of the leak current is suppressed.

Description

Detailed Description of the Invention

[0001]

The present invention relates to gallium arsenide (hereinafter
GaAs) Hall element and its manufacturing method.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 4, for example, a method of manufacturing a GaAs Hall element of this type has been shown in FIG.
Undoped GaAs buffer layer 2 at a growth temperature of about 00 ° C
Or form a P-type GaAs buffer layer 2 doped with beryllium (hereinafter referred to as Be) at a growth temperature of about 600 ° C. and form an active region on these high-resistance GaAs buffer layer 2. The N-type GaAs layer 3 and the N ⁺ -type GaAs layer 4 constituting the ohmic contact region are sequentially formed, and the N ⁺ -type GaAs is formed.
The Hall element was formed by taking out the ohmic electrode 5 from the layer 4.

[0003]

However, the above-mentioned 600 ° C.
When an undoped GaAs buffer layer grown to a certain degree is used, variations in the electrical characteristics of the buffer layer, especially in the resistivity, occur depending on the purity of the raw materials in the MBE device (molecular beam epitaxy device) and the usage of the MBE device. .. And
As a result, as shown in FIG.
The drift of the unbalanced voltage VOFFSET due to the influence of the leak current from the layer 3 to the buffer layer 2 becomes large, and the linearity and symmetry are deteriorated, and the output voltage VOUT characteristic when a magnetic field is applied is also non-linear and causes a large drift. Has occurred.
For this reason, the manufacturing yield of the Hall element decreases, and
The design margin during system operation becomes smaller, and an adjustment mechanism for adjusting the variations in Hall element characteristics is required.

When a P-type GaAs buffer layer doped with Be at a growth temperature of about 600 ° C. is used, Be is mixed from the buffer layer or the MBE device into the N-type GaAs layer which is the active region, and the compensation effect is obtained. Occurs, resulting in a decrease in carrier mobility and deterioration in sensitivity characteristics.

The present invention is intended to solve the above-mentioned problems, and by forming a high-resistance GaAs buffer layer on a semi-insulating GaAs substrate, an unbalanced voltage VOFFSET and an output voltage VOUT characteristic when a magnetic field is applied. It is an object of the present invention to provide a GaAs Hall element having good linearity and symmetry and a small drift.

[0006]

In order to achieve the above object, the structural feature of the invention according to claim 1 is that it has a semi-insulating property.
An undoped GaAs buffer layer formed on a GaAs substrate,
An N-type GaAs layer forming an active region formed on the undoped GaAs buffer layer, an N ⁺ -type GaAs layer forming an ohmic contact region formed at a predetermined position on the N-type GaAs layer, and the N ⁺ In an undoped GaAs buffer layer in a GaAs Hall element having an electrode film connected to a GaAs layer of
The content ratio of As to Ga has been made larger than 1.

The feature of the invention according to claim 2 is that an undoped GaAs buffer layer is formed on a semi-insulating GaAs substrate by a molecular beam epitaxy method at a growth temperature of 400 ° C. or less at a growth temperature of 400 ° C. or lower. Forming step, an N-type GaAs layer forming step of forming an N-type GaAs layer forming an active region on the formed undoped GaAs buffer layer by a molecular beam epitaxy method, and a molecular beam epitaxy method on the N-type GaAs layer N ⁺ type GaAs forming an ohmic contact region with
And a step of forming an N ⁺ -type GaAs layer for selectively forming the layer.

[0008]

In the invention according to claim 1 configured as described above, in the undoped GaAs buffer layer formed on the semi-insulating GaAs substrate, gallium (hereinafter, Ga
The content rate of arsenic (hereinafter referred to as As) relative to
Making it bigger. The buffer layer exhibits a very high resistance characteristic due to the deep impurity level formed in the buffer layer due to the presence of excess As in the undoped GaAs buffer layer. The reason for this will be described below.

In a low temperature grown GaAs substrate, the donor is
As at the Ga position and As at the interatomic position, this excess As constitutes a deep impurity level. Since such a deep level donor is not activated around room temperature and does not generate carriers, if the donor concentration ND is higher than the acceptor concentration NA, all the carriers from the acceptor are compensated by the donor and electrical conduction occurs. There are no carriers to be used, and the GaAs substrate has a high resistance. Since the residual acceptor concentration NA in undoped GaAs is usually 10 ¹⁵ cm ^-3 or less, the above condition is satisfied if the donor concentration ND is 10 ¹⁵ cm ^-3 or more. Atomic density in GaAs is 4.42
× 10 ²² atoms cm ^-3 , the donor concentration ND is about 2 ×
If it is 10 ^-6 % or more, that is, 0.02 ppm or more, all the carriers from the acceptor are compensated by the donor,
The GaAs substrate has a high resistance.

Due to the high resistance characteristic of the buffer layer, an N-type GaA forming an active region formed on the buffer layer is formed.
The leak current from the s layer to the buffer layer is reduced, and the non-uniformity of the leak current is suppressed. Furthermore, by providing the high-resistance buffer layer, the influence on the N-type GaAs layer due to the nonuniform substrate potential of the semi-insulating GaAs substrate is suppressed. As a result, as shown in FIG. 3, the GaAs Hall element is excellent in the linearity and symmetry of the unbalanced voltage VOFFSET with respect to the control applied voltage VD and the output VOUT characteristic when a magnetic field is applied, and has an extremely small drift. It has hall element characteristics.

In the invention according to claim 2 configured as described above, in the undoped GaAs buffer layer forming step, the undoped GaAs buffer is grown on the semi-insulating GaAs substrate by a molecular beam epitaxy method at a growth temperature of 400 ° C. or less. A layer is formed. Under such low temperature conditions, undoped Ga
By forming the As buffer layer, the content ratio of excess As donor to Ga acceptor in the undoped GaAs buffer layer can be made larger than 1. Then, an N-type GaAs layer and an N ⁺ -type Ga layer are further formed on the undoped GaAs buffer layer.
The GaAs Hall element obtained by sequentially forming the As layer has the high resistance buffer layer due to the presence of excess As as described above. As a result, according to the above manufacturing method, the unbalanced voltage VOFFSET is generated for the same reason as described above.
Also, a GaAs Hall element having excellent linearity and symmetry of the output voltage VOUT characteristic when a magnetic field is applied and excellent characteristics of very small drift can be obtained.

[0012]

An embodiment of the present invention will be described with reference to the drawings.
1 and 2 are schematic views showing the schematic manufacturing process of the GaAs Hall element according to the embodiment.

First, the MBE method is performed on a semi-insulating GaAs substrate 10 which is held at a substrate temperature of 400 ° C. or lower, eg, 300 ° C.
Thus, the undoped GaAs layer 11 is formed. Furthermore, Ga
With the As substrate 10 still set in the MBE device, the substrate temperature is raised to about 600 ° C. and the undoped GaAs layer 1
The N-type GaAs layer 12 is formed by MBE to provide an active region exhibiting a magnetic-sensitive property on the substrate 1, and then the N ⁺ -type GaAs layer 13 is provided by MBE to provide an ohmic contact region (see FIG. 1 ( See a)).

Next, the undoped GaAs layer 11, N
A photoresist film 14 is selectively formed by a photolithography technique on a portion of the GaAs substrate 10 on which the n-type GaAs layer 12 and the N ⁺ -type GaAs layer 13 are formed (FIG. 1).
(See (a)). Using this photoresist film 14 as a mask, N ⁺ type Ga is formed by a dry or wet etching method.
A part of the As 13, the N-type GaAs layer 12 and the undoped GaAs 11 is removed by etching, and the remaining resist film 14 is peeled off to form a convex portion H for forming a Hall element (see FIG. 1B).

Next, a photoresist film 15 for forming a Hall element on the convex portion H is selectively formed on the substrate 10 by the photolithography technique (see FIG. 1C). Using the photoresist film 15 as a mask, the N ⁺ type GaAs layer 13 and the N type GaAs are formed by a dry or wet etching method.
A part of the layer 12 is removed by etching, and the remaining resist film 14 is peeled off to form a cross-shaped magnetic sensing portion J of the Hall element (see FIG. 1D).

Next, in order to form gold germanium / nickel / gold (AuGe / Ni / Au) as an ohmic electrode in a desired pattern on the surface of the GaAs substrate 10 on which the magnetically sensitive portion J is formed, it is often used. The photoresist film 17 is applied by the lift-off process (see FIG. 2 (e)), and the photoresist film is patterned as 17a by the photolithography technique. Subsequently, AuGe / Ni is continuously formed.
/ Au multilayer conductor film 16 is formed by vacuum deposition (Fig. 2
(See (f)). By peeling off the resist film 17a from such a substrate, the Au film laminated on the resist film 17a is formed.
By removing the Ge / Ni / Au multilayer conductor film at the same time,
The ohmic electrode 16a is formed (see FIG. 2G).

Although not described in detail, a protective film 18 made of silicon oxide and an external connection electrode 19 made of aluminum are selectively formed on the GaAs substrate 10 on which the ohmic electrode 16a is formed. A Hall element chip is formed by dividing the GaAs substrate 10 into individual Hall elements (see FIG. 2 (h)).

This Hall element is composed of a semi-insulating GaAs substrate 10.
Since the upper undoped GaAs buffer layer 11 is formed at a low temperature of at least 400 ° C. or lower by the MBE method,
The content ratio of As to Ga in the buffer layer 11 is set to be larger than 1. Therefore, the buffer layer 11 exhibits a very high resistance characteristic due to the deep impurity level formed in the buffer layer 11 due to the presence of excess As in the undoped GaAs buffer layer 11. Due to the high resistance characteristic of the buffer layer 11, the leak current from the N-type GaAs layer 12 forming the active region formed on the buffer layer 11 to the buffer layer 11 is reduced and the non-uniformity of the leak current is suppressed. It Further, due to the high resistance buffer layer 11, the N-type GaAs layer 1 due to the non-uniform substrate potential of the semi-insulating GaAs substrate 10 is formed.
The effect on 2 is also suppressed.

As a result, as shown in FIG. 3, the GaAs Hall element has an unbalanced voltage VOFFSET characteristic with respect to the control applied voltage VD and an output voltage VOUT characteristic when a magnetic field is applied, as compared with the conventional example (see FIG. 5). It has excellent Hall element characteristics with good linearity and symmetry and very small drift. In addition, the undoped GaAs buffer layer 11 described above is
The presence of excess As has a very high resistance characteristic and the reduction of the leakage current is realized, so that the leakage current at the time of high temperature operation of the GaAs Hall element (for example, 200 ° C.) is suppressed and the temperature characteristic is improved.

In the above embodiment, semi-insulating Ga is used.
As the buffer layer formed on the As substrate, an undoped GaAs layer formed by the MBE method at a low temperature condition of 400 ° C or lower is used.
Undoped AlxGa1-xAs layer (x = 0 ~
Even if 1) is used, the same effect as described above can be obtained. That is, on a semi-insulating GaAs substrate at a low temperature condition of 400 ° C or less.
By providing an undoped AlxGa1-xAs layer by the MBE method, the content ratio of As to Al and Ga is made larger than 1.
As a result, the buffer layer exhibits very high resistance characteristics due to the deep impurity levels formed in the undoped AlxGa1-xAs buffer layer due to the presence of excess As in the buffer layer.
Due to the high resistance characteristic of the buffer layer, the leak current from the N-type GaAs layer forming the active region on the buffer layer to the buffer layer is reduced and the nonuniformity of the leak current is suppressed. Further, the high-resistance buffer layer suppresses the influence of the non-uniform substrate potential of the semi-insulating GaAs substrate on the N-type GaAs layer.

In the above embodiment, the undoped GaAs buffer layer or the undoped AlxGa1-xAs buffer layer formed by the MBE method at 400 ° C. or lower is used, but impurities such as silicon and beryllium are used when forming the buffer layer. However, even if it is introduced up to about 10 ¹⁹ cm ^-3, these impurities are compensated by the deep impurity level due to excess As in the buffer layer, so that a buffer layer with a very high resistance can be obtained as in the case of undoping. Be done. Therefore, even if such a doped GaAs buffer layer or AlxGa1-xAs buffer layer is used, the linearity and symmetry of the unbalanced voltage VOFFSET characteristic and the output voltage VOUT characteristic when a magnetic field is applied are excellent, and the drift is extremely small. It is possible to obtain a Hall element having excellent characteristics that is extremely small.

Further, in the above embodiment, the semi-insulating property
A Hall element is formed by providing an N-type GaAs layer and an N ⁺ -type GaAs layer on a GaAs buffer layer or AlxGa1-xAs buffer layer formed on a GaAs substrate at a low temperature of at least 400 ° C or lower by the MBE method. However, a semiconductor device such as a GaAs integrated circuit or a GaAs high electron mobility transistor (GaAs HEMT) that forms active regions of various configurations on the GaAs buffer layer or AlxGa1-xAs buffer layer is formed.
The present invention may be applied to the formation of the GaAs buffer layer.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a first half of a schematic manufacturing process of a GaAs Hall element according to an embodiment of the present invention.

FIG. 2 is a schematic diagram showing a latter half of a schematic manufacturing process of the same GaAs Hall element.

FIG. 3 is a graph showing an unbalanced voltage VOFFSET characteristic of the same GaAs Hall element and an output voltage VOUT characteristic when a magnetic field is applied.

FIG. 4 is a schematic view showing a schematic cross section of a GaAs Hall element according to a conventional example.

FIG. 5 is an unbalanced voltage V of a GaAs Hall element according to a conventional example.
6 is a graph showing an OFFSET characteristic and an output voltage VOUT characteristic when a magnetic field is applied.

[Explanation of symbols]

10 ... Semi-insulating GaAs substrate, 11 ... Undoped GaAs buffer layer, 12 ... N-type GaAs layer, 13 ... N ⁺ -type GaAs layer, 14, 1
5, 17 ... Photoresist film, 16a ... Ohmic electrode.

Claims (2)

[Claims] 1. An undoped GaAs buffer layer formed on a semi-insulating GaAs substrate, an N-type GaAs layer forming an active region formed on the undoped GaAs buffer layer, and the same N-type GaA.
In an GaAs Hall element including an N ⁺ type GaAs layer forming an ohmic contact region formed at a predetermined position on the s layer and an electrode film connected to the N ⁺ type GaAs layer, the undoped GaAs buffer layer A GaAs Hall element characterized in that the content ratio of As to Ga is larger than 1. 2. An undoped GaAs buffer layer forming step of forming an undoped GaAs buffer layer on a semi-insulating GaAs substrate by a molecular beam epitaxy method at a growth temperature of 400 ° C. or lower, and on the formed undoped GaAs buffer layer. An N-type GaAs layer forming step of forming an N-type GaAs layer forming an active region by a molecular beam epitaxy method, and an N ⁺ -type GaAs layer forming an ohmic contact region by a molecular beam epitaxy method on the N-type GaAs layer are selected. Form N ⁺
Type GaAs layer forming step, and a method of manufacturing a GaAs Hall element, comprising: