JP3456254B2 - Epitaxial wafer for Hall element and method of manufacturing the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a heterojunction Hall element using an InP crystal as a substrate, and particularly to a GaInAs heterojunction Hall element composed of a heterojunction with GaInAs.

[0002]

2. Description of the Related Art Hall (Ha) is one of the magnetoelectric conversion elements.
11) elements are known. This Hall element is a kind of magnetic sensor and is already used as a rotation detection sensor, a current sensor, or the like. In addition to elemental semiconductors such as Si and Ge, semiconductor materials for Hall elements include InSb,
III-V group compound semiconductors such as InAs and GaAs are also used. Recently, the need for precision sensing technology in high temperature environments, such as precise rotation detection of automobile engines, has increased, and it has the ability to output high Hall voltage and has suppressed the change in element characteristics due to temperature to a low level. There is a demand for a high-performance Hall element.

The Hall voltage is the hole (Hal) of a semiconductor material.
l) Depending on the coefficient, the larger the Hall coefficient, the higher the Hall voltage output capability. Moreover, this Hall coefficient increases in proportion to the electron mobility of the semiconductor material. Therefore, in order to obtain a high Hall output voltage, that is, to obtain a highly sensitive Hall element, it is necessary to use a semiconductor material exhibiting a high electron mobility. Therefore, recently, Ga _X In _1-X As (x
Represents the composition ratio. ) InP using a ternary mixed crystal as a magnetic sensing layer
A high-sensitivity Hall element made of a hetero-junction material has been realized (Okuyama Shinobu et al., Autumn 1992 53rd Annual Meeting of the Society of Applied Physics, Proceedings No. 3, page 1078, lecture number 16a-SZC-16 ). This new GaInAs
The heterojunction Hall element has an excellent sensitivity characteristic because the characteristic temperature change is relatively small and the room temperature electron mobility is extremely high.

This GaInAs heterojunction Hall element uses a semi-insulating InP single crystal as a substrate (Okuyama Shinobu et al., Autumn 1992, 53rd Annual Meeting of the Society of Applied Physics, Proceedings No. 3, page 1078). , Lecture number 16a
-SZC-16). The thickness of the InP single crystal substrate conventionally used as a substrate is generally 250 to 450 μm. This is because it does not hinder the handling as a substrate, facilitates subsequent processing steps such as epitaxial growth, and suppresses "warp" of the substrate in a thermal environment. The InP single crystal substrate is usually used by cutting a single crystal obtained by the Czochralski method and polishing the surface. InP crystal contains carbon, sulfur, iron,
It contains impurities such as manganese and is distributed in the ingot according to a certain distribution coefficient. These impurities move under the influence of the thermal environment and affect the electron mobility in the device.

The surface of the InP crystal used as the substrate, that is, the crystal surface on the side where the buffer layer and the magneto-sensitive layer are deposited, is
In order to obtain a growth layer with excellent flatness, it is precisely polished flat. On the other hand, the back side of the InP substrate crystal is not usually polished as smoothly as the front side. Generally, after lapping with polishing powder, the processing is limited to etching. In general, there is a case where both front and back surfaces are mirror-finished, which is generally called double-side polishing, but even in this case, the front and back surfaces are not made to have the same roughness due to the handling of the substrate crystal during processing. In the case of double-sided polishing, the surface with less roughness is used as the surface to deposit the epitaxial layer.

The root mean square value (abbreviated as rms) is used to quantitatively express the surface roughness (roughness). When unevenness is present on the surface, assuming that a line showing the average value of the degree of these unevenness is y _m, and letting the straight line distance between each unevenness and y _m be y _n , the rms showing the average roughness is It is given by the following formula. rms = {(y ₁ ² + y ₂ ² + y ₃ ² + ·· + y _n ² ) / n} ^1/2 (1) The rms of the surface of a conventional, very general InP crystal used as a substrate. Is less than 10 nm. On the other hand, the roughness on the back surface side is about 100 nm in rms.

Conventionally, a heterojunction system of GaInAs and InP has been formed on the crystal surface having the above roughness. However, although this heterojunction system is reported to exhibit high electron mobility at room temperature (for example, Kenjiro Konuma et al., Proceedings of the 53rd Autumn Meeting of the Applied Physics Academic Conference, No. 1, 1992, Lecture No. 18a). -ZE-3,
283 pages, or Hilde Hardtdegen
J. J. et al. Cryst. Growth, Vol. 116
(1992), p. p. 521-523. ), In order to obtain this high electron mobility in a stable manner, simply forming a heterojunction does not always give a stable high electron mobility characteristic. Certainly, the steepness of the composition at the hetero interface is one of the important factors for obtaining a high electron mobility, but a method for more stably obtaining a high electron mobility has not been presented yet. For this reason, the current situation is that the stable supply of the Hall element composed of a high-quality GaInAs / InP heterojunction having a high product sensitivity is hindered.

GaInAs / InP or GaInAs
In order to form a heterojunction such as / AlInAs, a semi-insulating InP single crystal is used as described above from the viewpoint of lattice matching. By the way, iron (Fe) is usually added to obtain semi-insulating InP. Fe easily diffuses thermally within the InP crystal. Therefore, it diffuses into the growth layer deposited on the surface of Fe-doped InP crystal having a small rms. The Fe impurity diffused into the epitaxial growth layer functions as a trap and reduces electron mobility. Therefore, GaInAs / InP
In order to fully exhibit the high electron mobility characteristics of the heterojunction system, it is necessary to suppress the penetration of Fe impurities into the growth layer. In addition to Fe impurities as a dopant, for example, diffusion of impurities serving as donor impurities remaining in the InP substrate into the epitaxial layer may also be a factor that lowers the electron mobility.

As a result of intensive studies by the present inventors, I
InP near the heterojunction interface provided on the nP single crystal substrate
It has been newly found that the electron mobility obtained is extremely reduced in the presence of a high carrier concentration region due to thermal diffusion of residual donor impurities in the substrate. It was also found that this high carrier concentration region was accumulated in the InP crystal mainly composed of sulfur (elemental symbol: S) contained in the InP single crystal substrate, where n-type impurities having a relatively large diffusion constant were accumulated. Therefore, in order to impart high electron mobility characteristics to the heterojunction, it is necessary to suppress the diffusion of such easily diffused impurities from the surface of the InP crystal substrate to the epitaxial growth layer.

[0010]

Highly sensitive GaInAs
In order to stably obtain a heterojunction Hall element made of / InP or the like, that is, in order to easily impart high electron mobility characteristics to the heterojunction material with good reproducibility, diffusion of Fe and residual donor impurities into the epitaxial growth layer is performed. The purpose is to suppress permeation.

[0011]

That is, according to the present invention, the roughness of the back surface of the InP single crystal substrate is made rough, and impurities in the crystal are gettered to the rough surface portion by the heat of the epitaxial growth process, and then the back surface is polished. It is designed to be partially removed to eliminate the influence of impurities. Specifically, the surface roughness represented by the root mean square value (abbreviated as rms) is 100.
Semi-insulating property I having a back surface of 0 nm or more and 8000 nm or less I
On the nP substrate crystal, a Ga _x In _1-x As (x represents a composition ratio) layer and an InP layer or an Al _x In _{1- x} As (x) layer.
Represents the composition ratio. ) Layer with a heterojunction and then I
The back surface of the nP crystal substrate is removed by polishing at least half the thickness.
Using this epitaxial wafer as a base material, a GaInAs Hall element having excellent sensitivity characteristics can be stably obtained.

GaInAs / InP or GaInA
Each growth layer forming the s / AlInAs heterojunction is obtained by a metal organic thermal decomposition method (MOVPE method), an MBE method, or the like. Regardless of the growth method, it is convenient to set the growth temperature to obtain the growth layer as low as possible. Semi-insulating I
This is because diffusion of Fe and residual donor impurities in the nP substrate crystal to the growth layer side can be suppressed. Further, the InP layer is grown by, for example, the MOVPE method, and Ga _x In containing no P is formed.
There is no problem even if the growth method is different for each layer, such as growing the _1-X As layer by the MBE method, and it is not necessary to provide each layer forming the heterojunction by the only growth method.

There is no limitation on the stacking order of the epitaxial layers, and the InP layer may be first grown on the InP single crystal substrate, and then Ga _X In _1-X As may be deposited. There is no problem in depositing with. However, in order to improve the electron mobility of the Ga _x In ₁ -x As layer, which is normally used as the magnetic sensing part, to a considerable extent, the Ga _x In ₁ -x containing the Fe impurity from the InP single crystal substrate is used as the magnetic sensing part layer. In order to suppress diffusion into the As epitaxial growth layer, the In
InP is generally deposited as a buffer layer on a P single crystal substrate. By providing this buffer layer, the effect of suppressing the propagation of crystal defects and the like to the Ga _X In _1-X As epitaxial growth layer is produced, so that G
The electron mobility of a _X In _1-X As layer without unnecessarily lowering, leading to advantages such as to hold the high-sensitivity characteristics of GaInAs Hall element.

In addition, the composition ratio x of the Ga _x In ₁ -x As
With respect to, it is desirable that 0.37 ≦ x ≦ 0.57. Because, Ga _X In _1-X lattice-matched to InP
As the composition ratio of As deviates from x = 0.47,
The difference in lattice constant between Ga _X In _1-X As and InP, that is, the degree of lattice mismatch becomes remarkable, and induces a large amount of crystal defects and the like, which leads to deterioration of crystallinity and also causes reduction of electron mobility. This is also because the characteristic characteristics of the Hall element are deteriorated and the product sensitivity is greatly hindered due to the characteristics of the Hall element. Even when a III-V group compound semiconductor material such as Al _X In _1-X As that lattice-matches with InP is used as the buffer layer, Ga _X In _1-X As is used.
The composition ratio does not change.

The above heterojunction system is deposited on a semi-insulating InP single crystal substrate crystal. Normally the specific resistance is about 10
^It is common to use an InP single crystal of ⁴ Ω · cm to 10 ⁸ Ω · cm for the substrate. The surface of the substrate crystal has a plane orientation of {001} or an angle of several degrees from {001},
The surface is inclined. The thickness of the substrate is not strictly defined, but is generally 300 to 500 μm. The processing accuracy of the back surface of the InP single crystal substrate used as the substrate is r
The time in ms is 1000 nm or more and 8000 nm or less. The definition of rms on the back surface of the crystal is to intentionally deteriorate the roughness so that impurities in the crystal can be selectively accumulated on the back surface side of the InP substrate crystal, so that S etc. from the substrate front surface side to the growth layer can be increased. This is because the diffusion and accumulation of the impurities can be prevented. If the rms on the back side of the substrate crystal is the same as that on the front side of the substrate, the probability of so-called gettering is almost the same on both sides, and gettering does not occur preferentially on the back side of the InP single crystal. Therefore, the processing precision is not made equal on the front and back surfaces of the InP substrate crystal, and the rms on the back surface side is intentionally increased. 10 rms
If the thickness is not more than 00 nm, preferential gettering of impurities to the back surface side of the substrate does not significantly appear.

Fe whose backside rms is in the above numerical range
FIG. 4 exemplifies the concentration distribution of the S impurity after the semi-insulating InP single crystal substrate added with is heated to and held at the temperature required for the growth of the epitaxial growth layer. As shown in the figure, the S impurity is gettered and accumulated in a region that exceeds about half the thickness of the substrate crystal and reaches the back surface side. The S concentration on the back surface side of the substrate crystal exceeds 10 ¹⁷ cm ^-3 . In a region within about 1/2 of the thickness of the substrate crystal from the surface of the substrate crystal,
No significant accumulation of impurities has occurred. That is, when the surface processing is performed according to the present invention, if the half of the thickness of the substrate is left from the surface of the substrate crystal and the region on the back surface side where the impurities are gettered is removed, the donor inside the InP substrate crystal is removed. The impurity concentration is almost constant in the depth direction.

However, the rms of the back surface of InP is 8000 nm
If a rough surface processing is performed to exceed the range, processing strain remains in the InP substrate crystal due to such rough processing. High electron mobility cannot be obtained with a grown layer deposited on a strained substrate. Therefore, the rms on the back side of the InP single crystal
Is specified to be 1000 nm or more and 8000 nm or less. This is because high electron mobility characteristics are stably imparted. The substrate surface is finished by precision polishing so that the rms is 100 nm or less.

After obtaining the desired epitaxial growth layer, the back surface of the InP single crystal substrate having the above-mentioned surface roughness is ½ of the thickness.
Remove the above. By doing so, as can be judged from the concentration distribution of the impurities illustrated in FIG. 4, the concentration of the donor impurity mainly composed of sulfur in the InP single crystal substrate is 10 ¹⁶
It is possible to manufacture an epitaxial wafer for Hall elements formed on a substrate having a donor concentration of cm ⁻³ or less and a substantially uniform donor concentration distribution in the thickness direction of the substrate crystal. 10 ^{16 in} the thickness direction of the InP single crystal substrate, particularly in the vicinity of the interface between the substrate and the epitaxial growth layer provided immediately above
The presence of donor impurities exceeding cm ⁻³ makes it difficult to stably obtain an epitaxial wafer for Hall devices having a high electron mobility. In the case of a high-purity InP single crystal having a semi-insulating property and a high resistance, the donor concentration may be considered to be a carrier concentration.

[0019]

The substrate portion having a high impurity concentration is utilized by utilizing the gettering effect of the impurities contained in the substrate crystal exposed to a relatively high temperature such as the epitaxial growth process of the semiconductor layer forming the heterojunction. Are removed by polishing to prevent impurities from diffusing to the epitaxial growth layer side forming the heterojunction, thus providing an epitaxial wafer for a Hall element having high electron mobility.

[0020]

EXAMPLES The present invention will be specifically described below based on examples. FIG. 1 shows a schematic plan view of a GaInAs / InP heterostructure Hall element according to the present invention. Further, FIG. 2 is a schematic cross-sectional view in the vertical direction taken along the broken line AA ′ in FIG. In forming the heterojunction, a semi-insulating InP single crystal (101) having a plane orientation of {100} and containing iron (Fe) was used as a substrate. The specific resistance of the InP single crystal (101) was 1 × 10 ⁷ Ω · cm, and the thickness was about 350 μm.

The front and back surfaces (101a and 101b) of the above InP single crystal substrate (101) were processed according to the present invention, the rms of the front surface (101a) was 0.2 nm, and that of the back surface (101b) was 1214 nm. It was Therefore, the rms on the back surface was about 6070 times that on the front surface side. Regarding the roughness on the front surface side, the above-mentioned rms was achieved by selectively performing polishing and etching on the front surface side of a crystal having a surface roughness of almost the same rms on both front and back surfaces. .

On the rms crystal substrate (101), cyclopentadienylindium (molecular formula: C ₅ H
An undoped n-type InP layer (102) having a film thickness of about 100 nm, which was grown by the MOVPE method of atmospheric pressure (atmospheric pressure) using ₅ In as an In source, was deposited. InP used as a buffer layer
Layer (102) was grown at a temperature of 610 ° C.

An n-type G having a composition ratio of 0.47 and a film thickness of about 400 nm is formed on the InP buffer layer (102) as a magnetic sensitive layer.
An a _0.47 In _0.53 As layer (103) was deposited to form a heterojunction with the InP layer (102). Magnetic layer (10
The layer 3) was also formed by the atmospheric pressure MOVPE growth method described above, and the growth temperature was also 610 ° C. like the InP layer (102).

InP layer (102) and n-type Ga _x In
The carrier concentration of the _1-X As layer (103) is 2 × 10 each.
^{It was 15} cm ⁻³ and 2 × 10 ¹⁶ cm ⁻³ . Ga _X In
The carrier concentration of the _1-X As layer (103) was achieved by S doping. The electron mobility in this heterostructure was 11,000 cm ² / V · s at room temperature.

As described above, the hole crossing region including the magnetically sensitive portion exhibiting the magnetically sensitive function and the electrode forming region are patterned on the wafer having such a structure by utilizing the well-known photolithography technique. The photoresist material was left. Then, so-called mesa etching was applied to the region to leave the element functional region in a mesa shape.
During this mesa processing, the two semiconductor mesa layers crossing each other in a cross shape are perpendicular to each other at <0 bar 11> and <0 bar 11>.
0 bar 1 bar 1> were provided parallel to the direction. By this etching, the vertical cross section of the electrode forming portion and the magnetic sensing portion area is
When viewed from the directions of crystal axes of <0 bar 11> and <0 bar 1 bar 1> which are orthogonal to each other, the cross section in the <0 bar 11> direction has a trapezoidal shape, that is, a so-called forward mesa shape cross section, Conversely, in the <0 bar 1 bar 1> crystal axis direction, an inverted trapezoidal so-called inverted mesa cross section was formed.

After that, the wafer surface is covered with a general photoresist material, and 13% by weight of Ge is contained so as to form an input electrode and an output electrode through steps such as patterning, resist stripping, and lift-off. The Au / Ge alloy was vacuum-deposited to a thickness of about 600 nm to form the ohmic input / output electrode (104). All of these electrodes (104) have the same shape, and the plane has a long side of about 0.
The rectangle is 2 mm and the short side is about 0.07 mm.
By the way, the input resistance of the obtained Hall element was distributed around 1 KΩ.

Further, the front and back surfaces of the wafer are plasma CV
It was covered with a SiO ₂ insulating film (105) by the D method. table,
The thickness of the SiO ₂ film (105) was about 300 nm on both back surfaces. Next, a general photoresist material is applied onto the insulating film (105) on the wafer surface side, and the surface of the input / output electrode (104) is left behind after the photolithography and patterning steps as described above. Exposed for electrical connections. Following this, a dicing line (106) for separating into individual Hall elements was formed. In parallel with the formation of the dicing line (106), the back surface side of the InP crystal substrate (101) was etched to obtain the initial 350 μm.
The thickness was reduced from the thickness of m to about 150 μm. That is,
About 200 μm was removed from the back side of the substrate crystal (101) so that the thickness of the substrate crystal (101) was ½ or less of the initial thickness. During this thinning, the back surface (10) of the InP crystal substrate (101) was
The rms of 1b) was improved from the original 1214 nm to 85 nm. This back surface etching is performed to remove the layer on the back surface side where impurities are accumulated. After that, scribing was performed along the dicing line (106) to separate into individual devices (chips). Next, the chip was surrounded with a general surrounding epoxy resin to obtain a molded product.

The electrical characteristics of the manufactured GaInAs Hall element were evaluated. Further, the characteristics were compared with that of a GaInAs Hall element using a conventional InP single crystal substrate. Table 1 shows the product sensitivities of the present invention and the conventional example. In the conventional example, it was 462 V · A / T. On the other hand, Ga according to the present invention
The product sensitivity of the InAs Hall element is about 740V ・ A / T.
Was superior to the conventional example.

In the measurement of the impurity concentration distribution in the thickness direction of the substrate crystal by secondary ion mass spectrometry (SIMS), the concentration of S according to the present invention is substantially constant in the thickness direction of the substrate of 10 ¹⁶ cm ^−. It was less than ³ . On the contrary, in the conventional example, I
About 2 × 10 ¹⁷ cm ⁻³ S impurity was detected near the interface between the nP crystal substrate and the InP buffer layer. Also, FIG.
As can be seen from the electric measurement method by the ordinary CV method as shown in Fig. 1, in the conventional example, the maximum is about 1 × 10 ¹⁷ cm ^-3 mainly due to the accumulation of S in the surface layer portion of the InP crystal substrate. There was a region of high carrier concentration. On the contrary, in the present invention, In
No region of high carrier concentration was observed in the surface layer of the P crystal substrate. It was found that this is due to gettering of S impurities and the like caused by defining the rms on the back side of the InP single crystal substrate.

[0030]

[Table 1]

[0031]

EFFECT OF THE INVENTION High-quality GaInAs excellent in sensitivity characteristics
A Hall element can be obtained. Incidentally, in the present embodiment has been described taking a GaInAs Hall element comprising a heterojunction between Ga _X In _1-X As and InP as an example, G
Thus although using InP single crystal substrate also GaInAs Hall element comprising a heterojunction between a _X In _1-X As and Al _X In _1-X As, the effect of the present invention is exhibited.
In addition, regardless of the GaInAs Hall element, other elements such as G
It can also be applied to a Hall element made of aAs, InAs, InSb, or the like. In particular, the effect of the present invention is further exerted in the case of a Hall element including a heterojunction that utilizes the physical properties brought by the heterojunction.

[Brief description of drawings]

FIG. 1 is a schematic plan view of a GaInAs Hall element according to the present invention.

FIG. 2 is a schematic view of a cross section taken along a broken line AA ′ in FIG.

FIG. 3 is a diagram comparing carrier concentration profiles of a case according to the present invention and a conventional example.

FIG. 4 is a diagram showing accumulation of donor impurities in the case where the surface processing according to the present invention is performed.

[Explanation of symbols]

(101) Crystal substrate (101a) Crystal substrate front surface (101b) Crystal substrate back surface (102) Buffer layer (103) Magnetosensitive layer (104) Ohmic input / output electrode (105) Insulating film (106) Dicing line (107) Crystal Depth position from the substrate surface corresponding to 1/2 of the substrate thickness

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-5-275767 (JP, A) JP-A-60-233831 (JP, A) JP-A-4-267339 (JP, A) JP-A-4-27339 302139 (JP, A) JP 7-94803 (JP, A) JP 7-162057 (JP, A) JP 63-17577 (JP, A) JP 63-17576 (JP, A) 1992 Autumn Proceedings of 53rd Annual Meeting of the Society of Applied Physics, No. 3, p. 1078 Electrotechnical Laboratory News, No. 511, pp. 6-10 (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 43/06 H01L 43/14

Claims (2)

(57) [Claims] In claim 1 a thickness 200μm or less, I having 10 ¹⁶ cm ^-3 or less of sulfur concentration distribution in the concentration with respect to the thickness direction
An epitaxial wafer for Hall devices, comprising a heterojunction of a gallium arsenide / indium layer and an InP layer or an aluminum arsenide / indium arsenide layer on the surface of an nP single crystal substrate. 2. The surface roughness of the back surface is the root mean square value (rm
s) is 1000 nm or more and 8000 nm or less InP
On the surface of the single crystal substrate to form a heterojunction between gallium arsenide, indium layer and the InP layer or aluminum arsenide, indium layer, or back side of the InP single crystal substrate
A method for manufacturing an epitaxial wafer for Hall devices, characterized by removing ½ or more of the thickness of the substrate .