JP3404843B2 - Manufacturing method of Hall element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] [Industrial applications] Compound semiconductor Hall elements
Especially high-precision rotation sensor, current sensor and magnetic field measurement.
High demands for sensors used in industry such as
Simple and reasonable individual elements of Hall elements with high sensitivity characteristics
It relates to the method of separating children. [0002] 2. Description of the Related Art A magnetic field is detected and an electric signal is detected in accordance with the strength of the magnetic field.
Signal as one of the so-called magnetoelectric conversion elements.
Hall elements are known. This Hall element
When a magnetic field is applied, the Hall element
The Hall voltage generated by the movement of electrons
This is a kind of magnetic sensor that detects the amount of magnetism and detects magnetism
Rotation and position detection sensor or current sensor as medium
In addition to the above, a probe (probe; pr
obe), and is already used for a wide range of industries.
Have been used. Silicon is used as a semiconductor material for a Hall element.
Element semiconductors such as silicon (Si) and germanium (Ge)
Other, indium antimonide (InSb), indium arsenide
Elements such as aluminum (InAs) and gallium arsenide (GaAs)
Two elements belonging to Group III and Group V of the periodic table
III-V binary compound semiconductor, which is a combination of
used. However, a conventional compound semiconductor semiconductor
Looking at the element, the hole element depends on the physical properties of the semiconductor used.
There are advantages and disadvantages in the characteristics of children. For example, GaAs
The Hall element consists of a GaAs semiconductor with a band gap of
Small temperature change of element characteristics due to relatively large
On the contrary, the product sensitivity is lower than that of InSb because the mobility is slightly lower.
There is a drawback that it is lower than that of a Hall element. On the other hand, I
The nSb Hall element has a band gap of InSb semiconductor.
The temperature change of the characteristics is large because of the low, but high product sensitivity is obtained.
Have the advantage of being [0005] Recently, precise rotation control of an automobile engine has been performed.
Necessity of precision sensing technology in high temperature environment
Has the ability to output a high Hall voltage, and
New high performance with low changes in device characteristics due to temperature
There has been a demand for Hall elements. Where the hall
The voltage depends on the Hall coefficient of the semiconductor material,
The larger the Hall coefficient, the higher the output capability of the Hall voltage. Ma
The Hall coefficient increases in proportion to the mobility of the semiconductor material.
Add. Therefore, to obtain a high Hall output voltage,
Express high electron mobility to obtain high sensitivity Hall element
Semiconductor materials must be used. Therefore, high performance Hall elements from the industry
In consideration of the physical properties of semiconductor materials
Very recently, the same III-V compound semiconductors as before
But gallium arsenide, a mixture of three elements
(GaInAs) ternary mixed crystal and indium phosphide (I
nP) is formed on an InP single crystal substrate.
Use the material provided above as the material for the new high-sensitivity Hall element
(Shino Okuyama et al., 1992)
Proceedings of the 53rd JSAP Academic Lecture Autumn No. 3
(Published by the Japan Society of Applied Physics in 1992), 16a-SZC-1
6, page 1078). This new Hall element has
Temperature change is relatively small and room temperature mobility is extremely high
It is said that the high product yields unprecedented excellent product sensitivity
You. In order to obtain a Hall element, the material used must be
Instead, a single substrate goes through various processes for device fabrication
Form multiple elements on top of each other and eventually dice
(Dicing) process is called an individual element.
It is separated into loose chips. This dicing
Use a regular diamond blade
This is done by mechanical cutting. Extremely high as above
Even in the recently reported Hall element, GaAs
An element similar to a GaAs Hall element using a crystal as a substrate.
From the notion that
In addition, it was considered that chips could be stably achieved. However, a GaInAs Hall element
Is a GaAs hose using a conventional GaAs crystal as a base material.
Unlike element, it is much more brittle than GaAs crystal
InP single crystal with high
When dicing along the direction of the open wall that is perpendicular to each other,
"Chip" on the end face of the element chip, usually called chipping
And cracking of the chip itself, resulting in poor appearance
Failure on the chip, significantly lowering the yield of good chips
As well as crystal defects such as dislocations due to mechanical shock.
Introduces a defect that degrades the device characteristics itself
I was In order to overcome such a situation, dicing must be performed.
The crystal is inherently provided by the sucriber method
Attempts to make chips using cleavage have been considered.
Because this method is based on crystallographic properties,
Chips are less likely to occur on the chip end face, resulting in poor appearance
Is expected to reduce the incidence of problems due to
I have. However, in the scriber method having this advantage,
Even chip defects pass through dicing scriber
So-called die, provided with a linear cut groove
Strong dependence on the depth of the singing line
It turned out. [0010] The above dicing line
Is usually defined in a certain crystallographic direction,
They are provided so as to be orthogonal to each other along the axis. For example, G
III-V compound semiconductor crystals such as aAs and GaInAs
In the case of a Hall element consisting of
Along the [110] crystal axis direction, which is the direction in which the crystal cleaves
Dicing lines are often created. Or this
When formed in such a direction, depending on the crystal axis direction
Has a so-called inverted mesa or forward mesa shape
To the [011] direction and 45 °
[001] Dicing line is provided in the crystal axis direction
In some cases. Such dicing lines are commonly used
Forming using both lithography and etching technologies
But the shape of the etching depends on the direction of the crystal axis.
There is a difference. In other words, etching depends on the direction of the crystal axis.
The cross-sectional shape of the dicing line formed
This causes a difference in depth. Add a specific explanation
And in a crystal such as GaAs or InP, <0 bar
Cleavage method of <11> and <0 bar 1 bar 1> orthogonal to each other
In the dicing line formed in the direction, <0 bar 11
> In the direction, the area of the bottom is reduced compared to the etching depth direction
Reduce the so-called forward mesa type etching shape
Present. Conversely, <0 bar 1 bar 1> direction dicing la
The cross section of the in is the area of the bottom with respect to the etching depth direction.
Shows an inverted mesa-shaped shape. This means that
When forming a ling line, as has been done from the past
Dies for dicing in directions orthogonal to each other
If the line width of the sing line is set to the same
In addition to making the shape of the etching groove
The result is that everyone is different. The physical properties of the interface of the heterojunction are
In the case of the GaInAs Hall element that affects the characteristics,
Separate into individual elements along the scribe line
When passing through a cutting blade (blade) for separation
However, the mechanical shock at the time of this cutting, etc.
Deterioration of Hall element characteristics due to overhanging part and magnetic sensitive part
It was revealed to come. This characteristic change is
The important characteristics of the element are the unbalance rate,
Mainly excellent GaInAs Hall element
Characteristics are impaired. Furthermore, the cause of this characteristic deterioration
As a result of intensive studies, this change in characteristics has been
The Hall element formed in the base material is
When separating using a
Because it relies on cutting, its mechanical impact
Induces crystal defects, which cause
The present inventors have found that the excellent properties exhibited are impaired, and
It has been reached. That is, the present invention relates to an As Hall element.
Hall element that can output high Hall voltage by itself
Devices can be separated individually without deteriorating high sensitivity characteristics.
To provide a new separation method. [0012] [Means for Solving the Problems] Holes in the substrate surface
From the end face of the element formation area of the element to the dicing line
Distance, in other words the line width of the line for dicing
Are configured to be different in directions orthogonal to each other,
By etching the dicing line
The depth of the formed etching groove is determined by the shape of the dicing line.
Chip-type element that is held constant regardless of the growth direction
Of GaInAs hole element
Reliable individual separation without impairing the excellent characteristics of the child
To achieve. Provided to separate the Hall elements individually
From the center line of the dicing line (cut line)
Or the shortest distance to the output electrode within the dicing line
7% or more of the distance between the center lines, so that the dicing line
Dicing line phase from the center line to the outermost part of the electrode
Provide an interval equivalent to 7% or more of the interval between the center lines
In this way, separate cutting for individualization of the Hall element
Crystal defects such as dislocations generated due to mechanical shock sometimes applied
Defects adversely affect the electrodes and magnetically sensitive parts including the heterojunction.
This is to avoid blurring. Also, dicing line
For example, if the cross-sectional shape of
What is the center line of the above dicing line
Is the shortest distance from the output electrode to the cross section of the dicing line
When the shape differs depending on the shape and the cross section is reverse mesa
Is the center line of the dicing line
5% compared to the shortest distance to the output electrode
By setting a larger value as described above,
This prevents deterioration of characteristics due to mechanical shock at the time of disconnection.
is there. Usually, a GaInAs / InP heterojunction transistor is used.
When forming the element, a semi-insulating high resistance
InP single crystal substrate is used. Specific resistance is 10^Four ~ 1
0⁸Substrates in the range of Ωcm may be used
However, in practice, the specific resistance is 10⁶Ω · cm-10⁷ Ω · cm
It is common to use a substrate of about InP single crystal,
These crystals are liquid sealed Czochralski (Liquid En
capsulated Czochralski (LEC) method and recently VB
(Vertical Bridgman) method called vertical bridgeman
It can be easily manufactured by the method. In addition, Fe-added InP
The Fe impurities in the crystal may cause electrical characteristics such as electron mobility in the crystal layer.
If there is a concern about adverse effects on
Dissolve the single crystal with hydrochloric acid, etc.
Absorption spectroscopy and high frequency induction argon plasma spectroscopy
Instruments such as the wet method, or secondary ion mass spectrometry
Quantitatively determine the concentration of Fe impurities by physical instrument analysis, etc.
Then, a crystal having a desired Fe concentration may be selected. On this InP single crystal substrate, an InP layer and an n-type
Ga_X In_1-X As layer (x represents a composition ratio, 0 <x <1
It is. ) To form a heterojunction
There is no restriction on the stacking order of the epitaxial layers of
First, an InP layer is grown on a crystal substrate, and then Ga_X I
n_1-X As may be deposited and deposited in the reverse order.
There is no harm in stacking. However, it is usually
Ga_X In_1-X To improve the electron mobility of the As layer
First, Ga such as Fe impurity from the InP single crystal substrate is used._X In
_1-X Preventing diffusion to As epitaxially grown layer
First, buffer InP on the InP single crystal substrate (bubble).
ffer) layer. This buff
The formation of epitaxial defects such as crystal defects
To produce effects such as suppressing propagation to long layers,
_X In_1-X Without unnecessarily lowering the electron mobility of the As layer
In addition, the high sensitivity characteristics of the GaInAs Hall element can be maintained.
Invite such advantages. A wafer having such a layer configuration is
Update to provide for the formation of alloy ohmic contacts.
Carrier concentration is 10¹⁹-10²⁰cm^-3Low resistance n-type G
a_X In_1-X A As layer is grown. The above InP buffer layer and Ga_X In
_1-X There is no particular limitation on the growth method of the As layer,
Taxi growth method (Liquid Phase Epitaxial; LPE)
Method), molecular beam epitaxial growth method (Molecular Beam E)
pitaxial; MBE method), metal-organic pyrolysis vapor deposition,
Wauru MOVPE (Metal Organic Vapor Phase Epit
axial; a place called MOCVD or OMVPE
In some cases. ), Or both MOVPE and MBE
It is considered that the combined MO / MBE method can be applied.
You. However, at present, phosphorus with a relatively high vapor pressure (elemental description)
No .: P) for the growth of semiconductor thin films such as InP
Exclusively from the viewpoint of stoichiometric composition controllability than the E method
The MOVPE method is frequently used, particularly with the starting material of In.
To give a monovalent cyclopentadienyl indium
(Molecular formula: C_Five H_Five MOVPE method (in particular)
(See Kaihei 1-94613).
High quality InP and Ga even under normal pressure (atmospheric pressure)
InAs or the like can be obtained. In addition, the InP layer
Ga grown by OVPE and containing no P_X In_1-X A
The growth method differs for each layer, for example, the s layer is grown by MBE.
There is no problem. The heterojunction is the only growth method
It is not necessary to provide each layer to be formed, and the growth method differs for each layer.
Of course, you can do so. Further, the Ga_X In_1-X Mixed crystal ratio x of As
Is preferably set to 0.37 ≦ x ≦ 0.57.
No. This is because Ga lattice-matched to InP_X In_1-X
As the mixed crystal ratio of As deviates from the mixed crystal ratio x = 0.47,
Ga_X In_1-X The difference in lattice constant between As and InP,
The degree of child mismatch also becomes remarkable, causing a large number of crystal defects, etc.
In addition to causing a decrease in mobility,
Deterioration of characteristics and improvement of product sensitivity due to Hall element characteristics
This can cause a great deal of trouble. Further, the above Ga according to the present invention_X In_1-X
There is no particular limitation on the thickness of the As layer. However, Ho
The elements are electrically insulated during the actual production of
Therefore, the crystal layer in a specific region called mesa etching is
A process for removal is generally employed,
Conductivity to be removed by mesa etching for inter-insulation
Thickness of the layer exhibiting properties, especially the entire epitaxial growth layer
Time required for mesa etching inevitably increases
With the increase in etching, the amount of etching and the etching
This causes a noticeable difference in the chin shape. This is good
Of the unbalance ratio, one of the important characteristics of the Hall element
Increase, which hinders high quality device characteristics and
This leads to lower device yield. Therefore, the heterogeneous described in the present invention.
In constructing the structure, its constituent Ga
_X In_1-X The total thickness of the As layer and the InP layer is approximately
Good results can be obtained by setting the thickness to less than 5 μm. As described above, the growth on the InP single crystal substrate
Ga_X In_1-X As magnetic sensing layer and InP buffer layer
Heterojunction epitaxial wafer composed of
As a base material, Ga_X In_1-X Produce As Hall element
Was. In this production, a well-known photolithography technique is used.
Making full use of processing technology such as etching and etching technology,
That exhibits the function of_X In_1-X As magnetic sensing layer,
So-called mesa etching on the InP layer
Then, the element functional region is processed into a mesa shape. This feeling
The magnetic part layer has a cross-shaped plane, and two
The semiconductor mesa layers are each <0 bar 11>
And in parallel with the <0 bar 1 bar 1> direction. Here
To add a description of the method for obtaining the
Ga which is the outermost surface of the base material_X In_1-X As magnetic sensing layer
Apply a general photoresist material on the surface of
Input and output using normal photolithography technology
The resist material is left only in the region for forming the force electrode, and
The resist material in the other area is peeled off and removed. Naturally
After that, Ga is added using inorganic acid._X In_1-X As for the magnetic sensing layer
Then, etching is performed. The photoresist
Ga in the region where the strike material has been removed_X In_1-X As layer
It is selectively removed, and only the above-mentioned Ga_X In
_1-X The As magnetic sensing layer will be present. Then, again
The entire surface of the wafer is covered with a similar photoresist material and
After using photolithography technology,
To selectively etch the InP buffer layer by etching
To be removed. By this etching, the electrode formation part and the magnetic sensitivity
The vertical cross section of the region is represented by <0 bar 11> and <
0 bar 1 bar 1> viewed from the direction of the crystal axes orthogonal to each other
If it is a cross section in the <0 bar 11> direction,
It becomes a so-called mesa-shaped cross section, and conversely, <0 bar 1 bar 1
> In the direction of the crystal axis, an inverted trapezoidal so-called inverted mesa
You will have a cross section. Electrically, this
In the electrode formation area and the magnetic sensing area,
This can ensure the insulation of the element function part. However, the mesa etching is not completed.
When the total thickness of the long layer exceeds 5 μm, it is based on the crystal axis (crystal orientation).
The difference in etched shape is remarkable.
Causes an increase in unbalanced voltage, which is one of the characteristics of
This leads to a worsened imbalance rate. Therefore, as described above,
Of the entire epitaxial growth layer used for the fabrication of
Unbalance rate increases when the film thickness is set to approximately 5 μm or less.
This is convenient in that it is not allowed. After the proper mesa etching,
In addition, an output electrode is formed. In forming this,
General photoresist on the entire surface of the etched wafer
Apply a strike material. After that, the area where the electrode is to be formed is disclosed.
Patterning (patt) by well-known photolithography
erning) and the photoresist in the area where the input / output electrodes are formed.
Strips and removes only the dying material, and the magnetic sensing part layer that exists immediately below
Ga_X In_1-X The surface layer of the As layer is exposed. In the present invention, the position between the electrode and the dicing line is
A rule is added regarding the positional relationship. First, the magnetically sensitive part
The so-called hole cross section extends along the [001] crystal axis direction.
Is formed, so the dicing line is also common sense
[001] direction, ie, [011] direction which is the cleavage direction
And 45 °.
In this case, the etching is performed by a known wet method.
For example, <100> and <010> orthogonal to it.
Even if dicing lines are formed along the
Difference in cross-sectional shape of dicing line due to
Does not occur. Therefore, in the case of a Hall element, usually 4
The center of the dicing line with any of the electrodes provided
Set the distance between the wire and the end of the ohmic electrode between the dicing lines.
May be 7% or more of the interval. General GaAs device
Etc., the chip size is approximately 280
~ 400 μm, corresponding to between dicing lines
Is about 300 to 450 μm. Therefore Daishi
The distance between the scanning line and the end of the electrode is about 20 to 30 μm
About. This shortest distance between dicing lines
7% or more of the interval is added at the distance below
Indicates that the shock generated during dicing is the
Because it is not enough to prevent coverage. example
For example, an error for detecting a pit based on a dislocation can be obtained.
When the pitching is performed, the shortest distance described above is the specified condition of the present invention.
If not satisfied from the dicing line
Dislocation pits are continuously generated up to the electrode formation area.
This indicates that the dislocation has penetrated just below the electrode.
It is. On the other hand, unlike the above, a dicing line
Are cleavage directions, that is, <0 bar 11>, <0 bar 1 bar 1>
Are formed along the [011] crystal axis direction.
The dicing line formed by etching.
The shape of the vertical cross section differs depending on the direction of the crystal axis
Becomes More specifically, it is parallel to the <0 bar 11> direction.
The vertical cross-sectional shape of the dicing line groove formed in
It becomes a so-called forward mesa shape, and conversely, <0 bar 1 bar 1> direction
Of vertical cross section of dicing line groove formed along
The shape becomes an inverted mesa shape. Here, understand the shape of the cross section
FIG. 4 shows a very general structure near the dicing line.
The results are shown together with the arrangement of the electrodes. The example shown is dicing
Line groove (301) is <0 bar 11> crystal axis and
<0 bar 1 bar 1> formed along the crystal axis
It is. Also, the cross section of each dicing line
In order to illustrate the shape of <0 bar 11> as shown in FIG.
For dicing lines formed in the direction
It becomes a so-called forward mesa in which the cross-sectional area of the bottom decreases in the direction,
Conversely, in the <0 bar 1 bar 1> direction, as the groove depth increases
Along with this, as shown in FIG.
Become. Daishin having such an inverted mesa cross section
Look at the positional relationship between the grin (301) and the electrode (302).
Then, because of the inverted mesa shape, the bottom is
And the distance between the electrode (302) is further reduced.
I have. That is, this uses the dicing line (301)
Susceptible to mechanical shock during scribing
Means that On the other hand, in the case of a normal mesa,
As the height increases, the cross-sectional area at the bottom decreases,
The distance to the pole is in the direction of spreading. Therefore, we have mentioned above
Dicing line is <0 bar 1 bar 1> crystal axis direction
When the cross section is an inverted mesa,
Is the center of the dicing line (301) as shown in FIG.
The distance between the line (301a) and the electrode (302)
And represented by the symbol L. ) Is between dicing lines (301)
At least 7 (here, tentatively represented by symbol D).
%, A die having a forward mesa shape having a distance equivalent to at least
Distance between the center line (301a) of the sing line and the electrode (Figure
L for 4₀ Expressed by ) Must be further increased by 5% or more. Using the formula, the center line of the dicing line
When the distance between the electrodes is summarized, the die
Distance between the center of the scanning line and the electrode (L₀ Below)
In the relational expression (1) described above, and also, a daisin exhibiting an inverted mesa cross section
Relational expression for the distance (L) between the center of the grin and the electrode
Each of them will follow (2). L₀ ≧ 0.7 × D ‥‥‥‥‥‥‥ (1) L ≧ 1.05 × (0.7 × D) ‥‥‥‥‥‥‥ (2) Next, gold (Au) -germani used as an electrode material
(Ge) alloy on the resist material that has been processed.
Vapor deposited. Here, Au / Ge alloy is used as the electrode material
However, the electrode material is not limited to this.
N-type Ga_X In_1-X O per As crystal
What is necessary is just to use the material which can obtain a mimic electrode. Also,
For example, n-type Ga with low resistance and high carrier concentration_X In_1-X
As concentration layer as non-alloy ohmic contact layer
If it is provided, it should not be an alloy such as Au / Ge.
And simple metals such as aluminum (Al) and Au
An ohmic electrode can be formed. Here, the simple metal
The reason why an electrode exhibiting ohmic properties is obtained
Resistance Ga with high carrier concentration_X In_1-X As
Layer as a contact layer.
Therefore, a high carrier concentration layer for such a contact is provided.
If not, the ohmic properties can be
Obtaining an electrode that presents is nearly impossible. Next, after vacuum deposition of Al, a resist material
The lift-off (lift of
f) Au ・ deposited on the resist material using the method
The Ge alloy film is removed. For non-alloy contacts
When the metal material is applied,
Although the alloy is provided with a non-alloy contact layer,
If not, obtain an ohmic electrode.
After depositing the electrode material, alloying
It is necessary to perform a heat treatment called g). By the way, these
Al electrodes generally have a rectangular plane
However, the planar shape of the electrode is not particularly limited to this, and may be various.
It can be square, circular, or elliptical.
There is no obstacle. Next, insulating properties are obtained by a known plasma CVD method.
Silicon dioxide (SiO_Two) Deposit the wafer surface
To cover the entire surface. In the present invention, general SiO 2_TwoInsulate
A film that has been adopted as a coating film but has another insulating property, for example,
Silicon nitride (SiN) may be used. Next,
SiO manufactured as_TwoInsulating film with general resist material
Cover. After that, the electrode part and dicing line are formed.
A portion of the resist material corresponding to the position for
Removed by photolithography technology,_TwoAbsolute
Expose the rim. Here again, the present invention will be described.
In the direction of the crystal axis where the dicing line is located
Therefore, the line width of the dicing line is changed.
Therefore, the exposed SiO_TwoThe line width of the insulating film depends on the direction.
Is differentYou. Further, the exposed SiO_Two Fluorinated water for insulating film
Immersion in basic acid (molecular formula: HF)_Two Insulating film
Is dissolved and removed. As a result, the surface arrangement of the input and output electrodes
In the dicing line formation area, Ga_X In_1-X
The surface of the As layer is exposed. Actually separate into individual elements
Is exposed to the part corresponding to the dicing line
Ga_X In_1-X The As layer is further etched using an inorganic acid.
It is sufficient to remove the pitching. After that, Ga_X In_1-X As
The InP layer immediately below the layer is also removed by the inorganic acid. Normal
Is the surface layer of the InP single crystal substrate
Remove part of the part. Doing this in dicing
Use a scriber or blade
 ) And the like during the separation of the device,
Pre-reducing mechanical damage to the heterointerface
It is. When forming the dicing groove, the substrate
The back side of the InP single crystal substrate used as the material
When the etching proceeds, the base
The thinning of the plate crystal was achieved, and the above dicing line
Increases dicing integrity in conjunction with formation, making it extremely convenient
It is. After performing such processing, <0 bar 11> crystal
Known dicing along a dicing line parallel to the axis
Is applied. After that, the line width of the dicing line is smaller
<0 bar 1 bar 1> Dicing line parallel to crystal axis
By dicing along, the manufactured Hall element
These are individually separated to form Hall element chips. The present invention
To the line width of the dicing line according to the orientation of the crystal axis
By making a difference and dicing from the wider line width
In the vicinity of the ball element chip generated during dicing.
Without breaking the chip or the Hall element itself,
It was confirmed that the device could be easily diced into chips
Was. Also, the line width of the dicing line varies depending on the crystal axis.
The area of the occupied area by the margin
Use the difference to bond the lead wire
g) Recognition of the bonding position at the time can be performed easily.
A ripple effect such as this is also created. [0031] [Function] The line width of the separation margin of the Hall element is
By providing a difference according to the orientation of the crystal axis, the die
Determine the depth of the etching groove of the sing line in the direction of the crystal axis.
And dicing is easy.
Has the effect of Also, the margin for element isolation is occupied.
The difference between the two areas depends on the orientation of the crystal axis.
To detect the position of the input and output electrodes of the ball element, or
If it is easy to position the ball element chip during dending
It also has a ripple effect. Furthermore, with dicing
Eliminates the effects of mechanical stress and prevents a drop in electron mobility
I do. [0032] The present invention will be specifically described below based on examples.
You. (Embodiment 1) FIG. 1 shows a GaInAs hole according to the present invention.
FIG. 3 is a schematic plan view of an element. This hole element has a current of 1 mA.
When operating current is passed, magnetic field strength of 1k Gauss
It has the ability to output a hall voltage of 70 mV below
You. 2 and 3 are broken lines of the Hall element shown in FIG.
A cross section along A-A 'and a cross section along dashed line B-B' are schematically shown.
FIG. FIG. 2 (101) shows the heterojunction.
The iron (Fe) used as the substrate was added
Half of a plane orientation of (100) and a thickness of about 350 μm
It is an insulating InP single crystal. In this embodiment, the specific resistance is
About 10⁷ The crystal of Ωcm was used,
The position and the specific resistance also depend on the hole element fabrication process or the crystal layer.
It may be appropriately selected in consideration of the growth method and the like. (1)
02) is C on the crystal substrate (101)._Five H_Five In to In source
Grown by a normal pressure MOCVD method to a thickness of about 10
0 nm additive-free (and-oop) InP epitaxial bonding
It is a crystal layer. Further, the mixed crystal ratio on the InP layer (102) is
0.47, a Ga having a thickness of about 400 nm._0.47In
_0.53Normal pressure MOCVD of As epitaxial layer (103)
Provided by the growth method. InP layer (102) and Ga_0.47In
_0.53Carrier concentration of As epitaxial (103) layer
Is 2 × 10^Fifteencm^-3And 2 × 10¹⁶cm^-3so
there were. The above epitaxial layer (102 to 103)
Was grown by all MOCVD methods, but at normal pressure.
Or a reduced pressure method, and the In source is also C_Five H_Five Limited to In
Of course, other organic In compound raw materials may be used.
A wafer having such a structure can be formed by known photolithography.
Using the method and etching method, for the magnetic sensing area and input
In addition, the electrode area for forming the output electrode is referred to as a mesa area.
It was selectively processed as needed. In forming the mesa region, the G
a_X In_1-X As epitaxial layer (103) and I
magneto-sensitive area of nP epitaxial layer (102)
Areas other than those corresponding to the areas for forming the force and output electrodes
Must be removed, but in this example, the inorganic acid
These layers are selectively removed, and the InP single crystal group is further removed.
A part of the surface layer of the plate (101) is removed, and Ga is removed in the depth direction.
_X In_1-X As (103) to InP single crystal substrate (10
A mesa leading to 1) was formed. After that, input and output
Contains about 13% by weight of germanium to form an electrode for use
A gold-germanium (Au-Ge) alloy is vacuum deposited and
After that, the wafer on which the electrode material was deposited was heated at 420 ° C.
Then, the heat treatment was performed for 3 minutes, and the ohmic electrode (10
4) was formed. Next, the surface of the elementized wafer is
SiO by plasma CVD_TwoWith insulating film (105)
Coated. SiO_Two The thickness of the film (105) is about 300 nm
And Furthermore, this SiO_Two Well-known photo on film (105)
Using lithography technology and etching technology,
Dicing line for cutting and separating elements individually
(107) are converted to <0 bar 11> and <
0 bar 1 bar 1> formed along the crystal axis direction. The aforementioned
As described above, the line width of the dicing line (107) is
Difference in etching groove depth depending on the difference in direction
Therefore, a change is intentionally given depending on the crystal axis. That is,
Here, the line width of the dicing line is on the InP substrate surface.
<0 bar 11> 100 μm in the crystal axis direction
And half in the <0 bar 1 bar 1> direction
It was set to 0 μm. Therefore, these dicing lines
When dicing along the center line of (107)
Is the plane of the margin area (106) according to the direction of the crystal axis.
The products will be different. Specifically, in this case, FIG.
As described above, the length of one side of the individually cut element is 3
Since it is a 50 μm square, it is flat in the <0 bar 11> direction.
The area of the margin area (106) existing in the row is <0 bar
Occupies an area twice as large as the area in the -1 bar 1> direction (106)
I have. Note that, in this embodiment, the dying
The line width of the grin (107) is set to 100 and 50 μm.
However, the line width is not limited to this, and the ratio of the line width
There is no restriction to the values of the present embodiment. Thus, the end surface (108) of the element forming region
Distance from the center line (107) of the dicing line to
Be different in the direction perpendicular to each other,
From the end face of the area where the element
Element separation existing between the center line (107)
The areas occupied by the margins (106) are orthogonal to each other
The dicing lane by changing
Formed by etching the
The depth of the notching groove depends on the dicing line formation direction.
And maintain a constant
The incidence rate is reduced and the excellent characteristics of GaInAs Hall element
The individual separation was surely achieved without impairing the performance. Visual inspection of the ball element prepared as described above
Then, the surrounding area was inspected for chipping or falling off. Table 1 shows the evaluated terms.
Eyes and defect rates are compared between the case according to the present invention and the conventional example.
Shown in comparison. Here, the conventional example is the line of the dicing line
The width is the same in each direction. [0039] [Table 1] (Embodiment 2) Plane of the Hall element of Embodiment 2
FIG. 7 shows the structure, and FIG. 8 shows the cross-sectional structure. First, Example 1
The InP buffer layer and the GaI
A heterojunction consisting of the nAs magnetic sensing layer was formed. This
A wafer having such a structure is formed by a known photolithography as described above.
Making full use of key technology, the magnetic sensing part that first exhibits the magnetic sensing function
Patterning of hole cross area and electrode formation area including
General photoresist material only in the area
I let you. Thereafter, oxygen ions having a mass number of 32 are
Injected over the entire surface of the parent material. The accelerating voltage is
InP layer (102) and Ga_0.47In_0.53As layer (10
Considering the total film thickness of 3), and oxygen ions are
14 so as to penetrate a part of the surface layer of the crystal (101).
5 KV. The dose of oxygen ions is InP
Layer (102) and Ga_0.47In_0.53Of the As layer (103)
3.0 × 10 to increase the resistance of the desired area¹³cm^-2When
did. By this ion implantation, the above photoresist is
InP layer (102) and G
a_0.47In_0.53The resistance of the As layer (103) is increased.
Therefore, the electrode formation region and the region including the hole cross
It is insulated from the region. 7 and 8 show ion injection.
The region insulated by the insertion is indicated by the number (204). Thereafter, the wafer is made of a general photoresist material.
C Cover the surface, pattern, remove resist, lift
G to become input and output electrodes through processes such as
Au / Ge alloy containing 13% by weight of e
Vacuum deposited to a thickness of 600 nm.
Input electrode (105a) and output electrode (10
5b) was formed. Further, the entire surface of the wafer is once subjected to plasma CVD.
SiO by the method_Two It was covered with an insulating film (105). SiO
_Two The thickness of the film (105) was about 300 nm. Next,
A general photoresist material is applied on the insulating film (105).
And photolithography and patterning as described above.
Table of input / output electrodes (104a and b) after each process
The surface was exposed for later electrical connections. In this process
Daishin to continue and separate into individual Hall elements
Grins (107a and 107b) were formed. This da
The ising lines (107a and 107b) are [0
11] direction, but one of the lines (107
a) is in the <0 bar 11> direction, and the other (107b) is
It was provided in the direction of <0 bar 1 bar 1>. Attention here
To wake up, a dicing line provided in the <0 bar 11> direction
(107a) is the input ohmic electrode (104)
a) and one line (107b) is
The arrangement is close to the mic electrode (104b).
After that, the part corresponding to the dicing line is exposed.
Ga_X In_1-X Etch the As layer using an appropriate inorganic acid
Removed. Next, Ga_X In_1-X Just below the As layer
The InP layer was also removed with an inorganic acid. Furthermore,
The etching proceeds to a part of the surface layer of the InP single crystal substrate.
Removed. The die formed by the above etching
Of the cross-sectional shape of the groove of the lining lines (107a and b)
In other words, a line formed parallel to the <0 bar 11> direction
In the vertical cross section of the pin (107a),
Along the <0 bar 1 bar 1> direction, which is a direction orthogonal to this,
Line (107b), the cross section is inverted mesa
Shape. Here, the scribe line according to the present invention
The electrodes (104) based on the difference in shape of (107a and b)
When the arrangement of a and b) is omitted, the input electrode (104)
In the case of a), the scribe line (107
Because of the proximity to a), the same line (107a)
The distance from the force electrode (104a) is 30 μm.
This distance is determined by the adjacent dicing formed in the same direction.
6. Line spacing (represented by symbol D in FIG. 4).
Equivalent to 5%. That is, the dicing line spacing is formed
It is 400 μm regardless of the direction. On the other hand, it has an inverted mesa shape
Output electrode (104) close to the line (107b)
In the case of b), a dicing line (107b) and an electrode
Was set to 40 μm. This shortest distance is Daishi
10% of the distance between
A line having a mesa (107a) and an input electrode (104)
The distance is increased by about 33% from the shortest distance to a).
You. Note that the <0 bar 11> direction and the <0 bar 1 bar 1> direction
And secured by the dicing line formed along
Generally within the chip formation area where the plane is square
The electrodes are formed diagonally in this square.
In other words, one of the periphery of the electrode is a normal mesa dicing
It is formed along the line, one of which is the reverse mesa line
If it is formed along the
Make the shortest distance between the center of the dicing line and the electrode different.
Inverse mesa line that requires a long separation distance
And the distance between the electrodes may be unified. Thereafter, the dicing lines (107a and 107a)
scribe along b), and individual elements (chips)
Separated. In making this chip, InP single crystal base
To remove part of the back of the plate (101) by etching
Thus, the thickness of the substrate is reduced from the initial thickness of 350 μm to about 13 μm.
The thickness was set to 0 μm, and scribing was facilitated. The GaInAs manufactured by the above steps
Hall elements are generally used for sealing semiconductor elements.
Silica (SiO_Two ) Non-novolak type with filler
Surrounded with epoxy resin and surrounded. Forming an envelope
The highest required for softening the epoxy resin and injecting it into the mold
Was 190 ° C. By the way, the epo used
The expansion coefficient of the xy resin is about 6 × 10^-Five/ ° C. Envelope
Is a rectangular parallelepiped and the outer dimensions are 5mm x 5mm x
2 mm. Next, the Ga fabricated by the processing as described above is used.
The InAs Hall element was subjected to evaluation of electrical characteristics. This
Of the electron mobility at room temperature and the unbalanced
The pressure is evaluated with emphasis, and the conventional GaInAs hole
The device and the characteristics were compared. First, the room temperature electron mobility
As a result of comparing the present invention with the conventional example, it is manufactured according to the present invention.
GaInAs Hall element
The average electron mobility of the device provided is about 10,000 cm.^Two
/ V · s, whereas that of the conventional example is 6,200 c
m^Two / V · s. Also, to compare the unbalance rates,
In the element according to the present invention, the average is about ± 6%.
In contrast to that of the conventional example, a clear difference of ± 13% was observed.
Was called. Furthermore, the operating current of the Hall element is extended for a long time.
In the current-carrying deterioration test of the electrode applied to the input electrode.
However, the GaInAs Hall element according to the present invention is not
Is extremely low, whereas conventional Hall elements
Immediately after energization is started,
Many elements that cause electrode destruction due to reasons
Was. [0047] As described above, the photo resist is formed on the substrate surface.
Adjust the line width drawn with the
Distances to the center of the
The depth of the etching groove
Can be kept constant regardless of the direction of the
To reduce the occurrence rate of defective appearance of chipped devices
You. Impairing the excellent characteristics of GaInAs Hall element
And achieves individual element separation without dicing.
The sensitivity characteristics are not affected by the process.
Unprecedented high performance with excellent balance and low unbalance rate
Effective in providing high-quality GaInAs Hall elements easily
There is. In this embodiment, the GaInAs hose is used.
In the present invention, a buffer layer is formed.
Regardless of the material to be formed, Ga_X In_1-X As magnetic
Hall element or GaAs, InSb or
It can be applied to conventional Hall elements such as InAs.
Of course.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram schematically showing a planar structure of a Hall element according to the present invention. FIG. 2 shows the Hall element shown in FIG.
0 bar 11> is a diagram schematically showing a cross section perpendicular to the crystal orientation. FIG. 3 shows the direction of BB ′ of the Hall element shown in FIG.
It is a figure which shows typically the cross section perpendicular | vertical to 0 bar 1 bar 1> crystal orientation. FIG. 4 is a diagram illustrating a planar structure near a dicing line. FIG. 5 is a diagram showing a cross-sectional structure of a forward mesa dicing line. FIG. 6 is a diagram showing a cross-sectional structure of a reverse mesa dicing line. FIG. 7 is a diagram showing a planar structure of a Hall element according to a second embodiment. FIG. 8 is a diagram showing a cross section taken along line AA ′ of FIG. 7; [Description of Reference Numerals] (101) InP single crystal substrate (102) an undoped InP buffer layer (103) Ga _0.47 In _0.53 As sensing section layer (104) ohmic input and output electrodes (105) SiO ₂ insulating film (106) Device separation margin region (107) Dicing line (cut line) (108) Device end surface (204) Insulated region (301) Dicing line (302) Ohmic electrode

────────────────────────────────────────────────── ─── Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI G01R 33/06 H (72) Inventor Masahiko Usuda 1505 Shimokagemori, Chichibu City, Saitama Prefecture Showa Denko KK Chichibu Laboratory (72) Invention Ryoichi Takeuchi 1505 Shimokagemori, Chiba, Saitama, Japan Showa Denko KK 1505, Shimokagemori, Chichibu City, Japan Showa Denko KK Chichibu Plant (56) References JP-A-57-128086 (JP, A) JP-A-1-133703 (JP, A) (58) Fields surveyed (Int .Cl. ⁷ , DB name) H01L 43/06 G01R 33/07 H01L 21/301 H01L 43/04 H01L 43/14

Claims (1)

(57) [Claim 1] The substrate is made of InP single crystal having a plane orientation of (100).
It is made of a crystal, and Ga _X In _{1 -X} As (0.37 ≦ X ≦ 0.
57) The compound semiconductor of the magneto-sensitive layer and the InP layer composed of
A Hall element having a junction is connected to an epitaxial wafer.
In the method of manufacturing Hall elements manufactured by dicing
And the dicing lines are orthogonal to each other <0 bar 1
1> and <0 bar 1 bar 1> along the crystal axis direction,
0 bar 11> Compared to the line width in the crystal axis direction <0 bar 1 bar
1> Form by etching by reducing the line width in the crystal axis direction
<0 bar 11> Dicing line in the crystal axis direction
After dicing along <0 bar 1 bar 1> crystal axis direction
Dicing along the dicing line
And the hall elements are individually separated.
Manufacturing method of the element.