JP2005005646A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device formed with a Schottky junction formation layer which does not cause a characteristic deterioration of a heterojunction type field-effect transistor by reducing a thickness of a barrier layer. <P>SOLUTION: The heterojunction type field-effect transistor has such a structure that compound semiconductor layers which are formed as an InAlAs buffer layer 2, an InGaAs channel layer 3, an InAlAs spacer layer 4, an InP carrier supply layer 5 obtained by planar-doping Si and an InAlAsSb Schottky junction formation layer 6 are sequentially laminated on a compound semiconductor InP substrate 1. Further, a gate electrode 9, a source electrode 10 and a drain electrode 11 are formed in a specific portion on the Schottky junction formation layer 6. In the semiconductor device, the Schottky junction formation layer 6 has such a structure that is formed by laminating InAlAsSb and InP from the InP substrate 1 side. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device such as a heterojunction field effect transistor that can be used as an active element such as an ultrahigh-speed integrated circuit, a millimeter wave, and a microwave integrated circuit, and has excellent characteristics such as high frequency, high gain, and low noise. .
[0002]
[Prior art]
[Patent Document 1]
JP-A-6-120258 [Patent Document 2]
JP-A-9-55494 [Non-Patent Document 1]
R. Palla, J .; C. Harmand, S .; Biblemont, and A.B. Clei "AlInAs / GaInAs HEMT with AlInP barrier layer", Proc. 8th Int. Conf. On Indium Phosphide and Related Materials, pp. 678-680, April 1996.
[Non-Patent Document 2]
T.A. Enoki, H .; Ito, K .; Ikuta, and Y.K. Ishii, “0.1-μm InAlAs / InGaAs HEMTs with an InP-recess-etch stopper by MOCVD”, Proc. 7th Int. Conf. On Indium Phosphide and Related Materials, pp. 81-84, May 1995.
[Non-Patent Document 3]
A. Endo, Y .; Yamasita, K .; Shinohara, M .; Higasiwaki, K. et al. Hikosaka, T .; Mimura, S .; Hiyamazu, and T.K. Matsui, “Fabrication Technology and Device Performance
of Sub-50-nm-Gate InP-Based
High Electricon Mobility Transistor ", Jpn. J. Appl. Phys., Vol, 41 (2002) pp. 1094-1098.
As a conventional technique, an example (for example, refer to Patent Document 1) of a layer structure of a heterojunction field effect transistor using InP on a generally used substrate will be described.
As shown in FIG. 2, a buffer layer 22 made of undoped InAlAs is formed on a substrate 21 made of InP, and a channel layer 23 made of undoped InGaAs is formed thereon. Further, a spacer layer 24 made of undoped InAlAs is formed on the channel layer 23, and an InAlAs carrier supply layer 25 doped with Si (bulk-doped) so as to generate n-type carriers is formed on the spacer layer 24. A Schottky junction forming layer made up of an undoped InAlAs layer 26 and an undoped InP layer 27 is formed thereon. In particular, the InP layer denoted by reference numeral 27 is a layer that forms a gate electrode during gate processing, and has a function of automatically stopping etching, and is called a recess etch stopper layer. Further, a layer including the spacer layer, the carrier supply layer, and the Schottky junction formation layer is called a barrier layer.
As a material of the recess etch stopper layer 27 shown in FIG. 2, InAlP may be used in addition to InP (see, for example, Non-Patent Document 1). In addition, a structure of only InAlAs that does not use a recess etch stopper layer as a Schottky junction formation layer is also often used in the prior art. However, when an IC is manufactured using such a structure that does not use a recess etch stopper layer, an advanced process technique for controlling the etching amount during gate processing uniformly and with high accuracy is required. On the other hand, the introduction of the InP recess etch stopper layer into the Schottky junction formation layer improves the reproducibility of the etching process and improves the uniformity of the threshold voltage (Vth) and transfer conductance (gm). There is a characteristic (for example, refer nonpatent literature 3).
[0003]
Further, a gate electrode 29 formed by a Schottky junction is disposed on the InP recess etch stopper layer 27. The source electrode 30 and the drain electrode 31 are formed by ohmic junction via a contact layer 28 made of bulk-doped n-InGaAs doped with Si as an impurity, with a predetermined interval from the gate electrode 29.
In this heterojunction field effect transistor, a two-dimensional electron gas is formed in the vicinity of the spacer layer 24 side interface in the channel layer 23 by the electrons supplied from the carrier supply layer 25. The apparatus is operated by controlling the flow of the two-dimensional electron gas between the region under the source electrode 30 and the region under the drain electrode 31 by the voltage applied to the gate electrode 29. Electrons as carriers become two-dimensional electrons and move in an undoped (low impurity) channel layer, so that scattering due to impurities is suppressed and the electrons can move at high speed. In addition to bulk-doped n-InAlAs, n-InAlP may be used for the carrier supply layer (see, for example, Patent Document 2). As described above, InP / InAlAs, InAlP / InAlAs laminated structures, and InAlAs have been used for the conventional Schottky junction formation layer.
In general, metal organic vapor phase epitaxy (MOVPE) or molecular beam epitaxy (MBE) is used to form (grow) a stacked structure of compound semiconductor crystals used in heterojunction field effect transistors and the like. . When a heterojunction field effect transistor is grown on an InP substrate, a material containing Al, such as InAlAs, is often used as a part of the constituent material. However, since Al is very active, it is easy to incorporate impurities. Generally, high-temperature growth (500 ° C. or higher) is required to obtain high-quality crystals.
In order to improve the operating speed of heterojunction field effect transistors, it is effective to shorten the gate length to shorten the distance traveled by electrons. However, when the gate length is shortened, transistor characteristics are reduced by the short channel effect. Deteriorates. In addition, in order to suppress this short channel effect and operate the transistor at high speed, it has been reported that it is effective to reduce the total thickness of the barrier layer and the channel layer (for example, non-patent literature). 3). However, the channel layer needs to maintain a certain thickness (about 10 nm) in order to accumulate the two-dimensional electron gas. For this reason, the thinning of the barrier layer is actually a key technology for speeding up.
[0004]
[Problems to be solved by the invention]
As described above, in order to improve the operation speed of the heterojunction field effect transistor, it is necessary to reduce the thickness of the barrier layer. That is, in the case of the structure shown in FIG. 2, it is necessary to thin the spacer layer 24, the carrier supply layer 25, and the Schottky junction forming layer 26 and 27.
However, since the temperature for growing the layer structure of the heterojunction field effect transistor is high as described above, impurities (usually Si) bulk-doped in the carrier supply layer actually sandwich the carrier supply layer by thermal diffusion. It spreads up and down. Therefore, for example, in the conventional structure shown in FIG. 2, when the spacer layer 24 is removed or made extremely thin, the bulk-doped Si reaches the channel layer and the impurity in the channel layer. As the scattering increases, the electron mobility of the two-dimensional electron gas decreases. Therefore, the spacer layer needs to have a certain thickness (about 1 to 3 nm). Further, as a doping method for the carrier supply layer, besides the bulk doping as described above, the planar doping in which the growth is temporarily stopped and the growth surface is doped two-dimensionally can be used. In the case of bulk doping, the thickness of the carrier supply layer to which doping is performed is usually several nanometers to several tens of nanometers. However, in the case of using planar doping, the thickness of the doping region is reduced to the ultimate atomic layer. It becomes possible to stratify.
[0005]
However, when considering further thinning of the barrier layer, it is important how the Schottky junction forming layer is thinned. The InP recess etch stopper layer 27 that forms the Schottky junction formation layer shown in FIG. 2 usually requires a film thickness of about 5 nm in order to achieve sufficient stopper performance. The stopper performance deteriorates, and it becomes difficult to obtain uniform transistor characteristics as expected. It is also conceivable that only the InAlAs layer 26 is made thin while maintaining a sufficient thickness of InP. However, since the barrier height of InP is smaller than that of InAlAs, when the thickness of InAlAs is reduced in the InP / InAlAs structure, the effective Schottky barrier height decreases and gate leakage increases. There was a problem that the device characteristics deteriorated.
[0006]
On the other hand, in the InAlP / InAlAs structure using InAlP having almost the same barrier height as InAlAs, the Schottky barrier height does not decrease as much as InP / InAlAs even if the thickness of InAlAs is reduced while maintaining the thickness of InAlP. . However, the InAlP recess etch stopper is strained (lattice mismatch with InP), and a layer containing active Al appears on the process surface. Therefore, the InAlP recess etch stopper has stable characteristics with good reproducibility compared to the InP recess etch stopper layer. It was difficult to obtain and there was a problem in reliability.
[0007]
The present invention has been proposed in order to solve the above-described problems in the prior art, and the object of the present invention is to provide a Schottky in which the characteristics of the heterojunction field effect transistor do not deteriorate due to the thinning of the barrier layer. An object of the present invention is to provide a semiconductor device in which a junction formation layer is formed.
[0008]
[Means for Solving the Problems]
In order to achieve the above object of the present invention, the present invention is configured as described in the claims. That is,
The compound semiconductor substrate according to claim 1 has a structure in which a compound semiconductor layer to be a buffer layer, a channel layer, a spacer layer, a carrier supply layer, and a Schottky junction formation layer is sequentially stacked on the compound semiconductor substrate, and the Schottky A heterojunction field effect transistor in which a gate electrode, a source electrode, and a drain electrode are formed at predetermined portions on a junction formation layer, wherein the Schottky junction formation layer has a structure in which InAlAsSb and InP are stacked from the substrate side It is a device.
[0009]
According to a second aspect of the present invention, in the first aspect, the semiconductor device uses InP for the compound semiconductor substrate.
[0010]
According to a third aspect of the present invention, in the first aspect, the channel layer is a semiconductor device made of InGaAs which is a mixed crystal of GaAs and InAs. According to a fourth aspect of the present invention, in the first aspect, the spacer layer is a semiconductor device made of InAlAs, InAlAsSb, or InAlP.
[0011]
According to a fifth aspect of the present invention, in the semiconductor device according to the first aspect, the carrier supply layer is InP, InAlP, InAlAsSb, or InAlAs in which n-type impurities are planarly doped.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
<Embodiment 1>
Here, a basic layer configuration of the heterojunction field effect transistor having excellent characteristics of the present invention will be described.
The present invention relates to a heterojunction field effect transistor, which is an active element constituting an ultrahigh-speed integrated circuit, and the Schottky junction layer is composed of an InAlAsSb layer and an InP layer in order from the substrate side. Is the point. By including the InP layer, the gate leakage current can be reduced by an order of magnitude or more by including the InAlAsSb layer while maintaining the recess etch stopper function, so that it is possible to realize high-performance transistor characteristics with high manufacturing yield. There is an effect.
[0013]
Conventionally, a stacked structure of InP / InAlAs or InAlP / InAlAs has been used for a Schottky junction formation layer having a recess etch stopper performance. In addition, in the InP / InAlAs Schottky junction formation layer using the InP recess etch stopper layer that provides good transistor properties as described above, when the thickness of the InAlAs is reduced for the purpose of thinning the barrier layer, Gate leakage increased and transistor characteristics deteriorated.
[0014]
In the InP / InAlAs stacked structure, the increase in gate leakage caused by the thinning of InAlAs is considered to be caused by the decrease in the effective Schottky barrier height as described above. That is, if a material having a higher barrier height is used for the InAlAs Schottky junction formation layer 26 shown in FIG. 2 (conventional configuration), there is a possibility that the gate leakage that has been a problem can be reduced. The Al composition of InAlAs that lattice matches with InP is 0.48. As a method for increasing the barrier height, it is conceivable to increase the Al composition. However, when the Al composition is increased, the lattice constant becomes inconsistent with InP, so there is a concern that the device characteristics may be deteriorated by strain. On the other hand, by adding Sb to InAlAs with an increased Al composition, the lattice can be lattice-matched with InP again. In other words, if a stacked structure of InP / InAlAsSb is employed, it is considered possible to form a Schottky junction formation layer that is lattice-matched to InP and has little gate leakage even by thinning.
[0015]
InAlAsSb is known to lattice match with InP with various compositions from In _0.52 Al _0.48 As to AlAs _0.46 Sb _0.54 . In order to make the barrier height of InAlAsSb larger than InAlAs, the Al composition must be 0.48 or more in atomic ratio at least. In addition, when the Al composition of InAlAsSb is increased, excessively increasing the active Al deteriorates the device characteristics. In particular, when the Al composition is about 0.8 or more, there is a problem that oxidation proceeds during the process and the device characteristics are not stabilized. Therefore, InAlAsSb having an Al composition in the range of about 0.5 to 0.8 is suitable for practical use.
[0016]
In order to reduce the thickness of the barrier layer, it is better to adopt planar doping as a doping method for the carrier supply layer as described above. Further, the material of the carrier supply layer for performing the planar doping of the n-InAlAs carrier supply layer 25 bulk-doped with Si shown in FIG. Etc. can be used. In particular, InP and InAlP can be expected to improve device reliability because there is no carrier compensation by fluorine, which is a problem with InAlAs-based materials.
[0017]
In addition to InAlAsSb, InAlAs and InAlP that have been conventionally used can be used for the spacer layer, but InP is not suitable for the spacer layer because of its band discontinuity with InGaAs.
[0018]
In the present invention, a heterojunction is formed by thinning the barrier layer in a state where the Schottky junction formation layer has a function as a recess etch stopper layer by using a laminated structure of InP / InAlAsSb for the Schottky junction formation layer. It is intended to solve the problem of deterioration of the characteristics of the type field effect transistor.
[0019]
<Embodiment 2>
Embodiment 2 of the present invention will be described below with reference to the drawings.
FIG. 1 is a schematic cross-sectional view showing an example of the configuration of a semiconductor device according to an embodiment of the present invention. In FIG. 1, a buffer layer 2 made of undoped InAlAs is formed on a substrate 1 made of InP, and a channel layer 3 made of undoped InGaAs is formed thereon.
Further, a spacer layer 4 made of undoped InAlAs is formed on the channel layer 3, an InP carrier supply layer 5 in which Si is planar-doped is formed, and then, an Inve InAlAsSb Schottky junction forming layer 6 and an Andove InP A barrier layer is formed by sequentially laminating a Schottky junction forming layer composed of a recess etch stopper layer 7. In the present embodiment, the composition of the InAlAsSb Schottky junction formation layer denoted by reference numeral 6 is In _0.4 Al _0.6 As _0.9 Sb _0.1, and the film thicknesses of the respective layers consisting of reference numerals 4, 5, 6, and 7 Were set to 3, 2, 5, and 5 nm, respectively. Further, a gate electrode 9 is formed on the uppermost InP recess etch stopper layer 7 of the barrier layer by Schottky junction. Also. A source electrode 10 and a drain electrode 11 are formed in ohmic contact with each other through a contact layer 8 made of n-InGaAs in which Si is bulk-doped at a predetermined interval from the gate electrode 9.
[0020]
In order to clarify the effect of the present invention, the epitaxial wafer having a heterojunction field effect transistor structure immediately after growth was etched with a citric acid-based etchant, and then changes in sheet carrier concentration and mobility were measured by Hall effect measurement. . The resulting change in sheet carrier concentration and mobility in etching time is shown in FIG. In FIG. 3, the sheet carrier concentration decreases and the mobility tends to increase along with the etching time of about 15 seconds, and both the sheet carrier concentration and the mobility become constant values in the etching for 15 seconds or more. At this time, the sheet carrier concentration value is constant about 2 × ¹⁰ 12 ^{cm -2,} the mobility was about 7300cm ² / Vs. The fact that the sheet carrier concentration and the mobility value become constant after etching for 15 seconds or more indicates that the etching is automatically stopped after the n-InGaAs layer is removed by etching. In addition, it is shown that the stopper performance as expected can be achieved in the embodiment using the InP / InAlAsSb of the present invention as the Schottky junction formation layer even when the etching is performed up to 150 seconds and the value does not change. ing.
[0021]
Furthermore, in order to evaluate the problematic gate leakage, current-voltage characteristics were measured between the ohmic electrode 30 and the Schottky electrode 29 shown in FIG. 2 (conventional configuration). This reverse voltage characteristic is shown in FIG. At this time, an electrode having a size of 40 μm × 40 μm was used as the Schottky electrode. For comparison, the results of the conventional configuration in which InAlAsSb, which is the layer denoted by reference numeral 6 in FIG. 1 (configuration of the present invention), is changed to InAlAs are also shown in the figure. When a conventional InP / InAlAs Schottky junction formation layer was used, the reverse current value at a voltage of −1 V was −7.7 × 10 ⁻⁴ A. On the other hand, the reverse current value when the InP / InAlAsSb Schottky junction formation layer was used was −7 × 10 ⁻⁵ A. From this result, it was confirmed that the reverse current was reduced by about an order of magnitude in the InP / InAlAsSb Schottky junction formation layer of the present invention as compared with the prior art.
[0022]
Further, the grown wafer was processed to produce a HEMT having a gate length of 0.1 μm, and its characteristics were evaluated by a three-terminal measurement method. As a result, the HEMT characteristics, which had an on voltage of 2 V, an off voltage of 5 V, and a gate-drain breakdown voltage of 4 V in the conventional structure, are an on voltage of 4 V, an off voltage of 10 V, and a gate-drain breakdown voltage of 9 V, It was confirmed that the pressure resistance characteristics of HEMT were remarkably improved.
[0023]
【The invention's effect】
According to the present invention, it is possible to realize a semiconductor device having a Schottky junction formation layer in which deterioration of heterojunction field effect transistor characteristics does not occur due to thinning.
In order to improve the operating speed of the heterojunction field effect transistor, it is effective to reduce the thickness of the Schottky junction formation layer. However, if the Schottky junction formation layer is reduced, the effective barrier height As a result, the heterojunction field effect transistor has a problem in that the characteristics deteriorate.
The present invention employs a stacked structure of InP / InAlAsSb capable of obtaining a sufficient barrier height in a state having a function as a recess etch stopper as a Schottky junction formation layer. It was made possible to solve the problem of deterioration of transistor characteristics due to thinning.
This makes it possible to obtain the device characteristics as designed even by thinning, for which good characteristics have not been obtained so far, and it has a great effect on realizing higher speed of the heterojunction field effect transistor. It is what you have.
[Brief description of the drawings]
FIG. 1 is a schematic diagram showing a cross-sectional structure of a heterojunction field effect transistor exemplified in an embodiment of the present invention.
FIG. 2 is a schematic diagram showing a cross-sectional structure of a conventional heterojunction field effect transistor.
FIG. 3 is a graph showing changes in sheet carrier concentration and mobility of a heterojunction field effect transistor when the etching time exemplified in the embodiment of the present invention is changed.
FIG. 4 is a graph showing measurement results of current-voltage characteristics between ohmic electrodes and Schottky electrodes exemplified in the embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... InP board | substrate 2 ... InAlAs buffer layer 3 ... InGaAs channel layer 4 ... InAlAs spacer layer 5 ... InP carrier supply layer 6 which doped Si planarly ... InAlAsSb Schottky junction formation layer 7 ... InP recess etch stopper layer 8 ... n-InGaAs Contact layer 9 ... Gate electrode 10 ... Source electrode 11 ... Drain electrode 21 ... InP substrate 22 ... InAlAs buffer layer 23 ... InGaAs channel layer 24 ... InAlAs spacer layer 25 ... Si bulk doped n-InAlAs carrier supply layer 26 ... InAlAs Schottky Junction forming layer 27 ... InP recess etch stopper layer 28 ... n-InGaAs contact layer 29 ... gate electrode 30 ... source electrode 31 ... drain electrode

Claims (5)

It has a structure in which a compound semiconductor layer to be a buffer layer, a channel layer, a spacer layer, a carrier supply layer, and a Schottky junction formation layer is sequentially laminated on a compound semiconductor substrate, and a gate electrode is formed on a predetermined portion on the Schottky junction formation layer. A semiconductor device comprising a heterojunction field effect transistor for forming a source electrode and a drain electrode, wherein the Schottky junction formation layer has a structure in which InAlAsSb and InP are stacked from the substrate side. 2. The semiconductor device according to claim 1, wherein InP is used for the compound semiconductor substrate. 2. The semiconductor device according to claim 1, wherein the channel layer is made of InGaAs which is a mixed crystal of GaAs and InAs. 2. The semiconductor device according to claim 1, wherein the spacer layer is InAlAs, InAlAsSb, or InAlP. 2. The semiconductor device according to claim 1, wherein the carrier supply layer is InP, InAlP, InAlAsSb, or InAlAs in which n-type impurities are planarly doped.

Images