CN115295719A - Epitaxial layer structure of indium arsenide thin film, hall device and preparation method - Google Patents
Epitaxial layer structure of indium arsenide thin film, hall device and preparation method Download PDFInfo
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Abstract
The invention provides an epitaxial layer structure of an indium arsenide film, which relates to the technical field of compound semiconductors and comprises a gallium arsenide substrate; the buffer layer covers the upper surface of the gallium arsenide substrate, is provided with an indium arsenide buffer structure and covers the buffer layer; and the indium arsenide functional layer covers the upper surface of the indium arsenide buffer structure. The technical problem that the signal-to-noise ratio of the indium arsenide Hall device is low in the prior art is solved, and the technical effect of improving the signal-to-noise ratio on the basis of not reducing the sensitivity is achieved.
Description
Technical Field
The invention relates to the technical field of compound semiconductors, in particular to an epitaxial layer structure of an indium arsenide thin film, a Hall device and a preparation method.
Background
The hall device is a magnetic sensor using hall effect, is generally used for detecting magnetic field and changes thereof, and is widely applied to industrial grade and consumer grade electronic products. Important parameters of hall devices are sensitivity and signal-to-noise ratio.
The sensitivity of the Hall device is closely related to the carrier mobility of the bulk material of the Hall device, and the Hall device with high sensitivity is easier to accurately detect a very small magnetic field and the change of the magnetic field. The existing high-sensitivity Hall device generally adopts a compound semiconductor as a bulk material, and compared with the traditional silicon material Hall device, the high sensitivity of the compound semiconductor Hall device has more advantages. Wherein, the indium antimonide Hall device has the highest sensitivity, and the carrier mobility of the bulk material can reach 78000cm 2 However, the forbidden bandwidth of indium antimonide is narrow, so the temperature coefficient of the hall device adopting the indium antimonide material is poor, and the application range is limited. The gallium arsenide Hall device has excellent temperature coefficient, but low sensitivity, and the carrier mobility of the bulk material is not more than 8500cm at most 2 and/Vs, also limits the application scope. The indium arsenide Hall device not only has good temperature coefficient, but also has carrier mobility of 40000cm as high as the maximum 2 The sensitivity of the/Vs is obviously higher than that of the GaAs Hall device, but the application of the InAs Hall device is limited due to the poor signal-to-noise ratio.
Disclosure of Invention
The invention aims to provide an epitaxial layer structure of an indium arsenide thin film, and aims to solve the technical problem that an indium arsenide Hall device in the prior art is poor in signal-to-noise ratio.
The invention provides an epitaxial layer structure of an indium arsenide thin film, which comprises the following components:
a gallium arsenide substrate;
the buffer layer is covered on the upper surface of the gallium arsenide substrate;
an indium arsenide buffer structure covering the buffer layer;
and the indium arsenide functional layer covers the upper surface of the indium arsenide buffer structure.
Further, the indium arsenide buffer structure comprises:
a first type indium arsenide layer covering the buffer layer;
a second type indium arsenide layer overlying the first type indium arsenide layer.
Further, the first type indium arsenide layer is a non-doped low-temperature indium arsenide thin film layer; and/or
The second type indium arsenide layer is a non-doped high-temperature indium arsenide thin film layer.
Further, the thickness of the first type indium arsenide layer is 10-100nm; and/or
The thickness of the second type indium arsenide layer is 100-400nm.
Furthermore, the indium arsenide functional layer is an N-type doped indium arsenide thin film layer, and the doping concentration range is 2E16-2E17cm -3 。
Further, the quotient of the thickness of the first type indium arsenide layer divided by the sum of the thicknesses of the second type indium arsenide layer and the indium arsenide functional layer ranges from 0.02 to 0.2.
Further, the buffer layer is a gallium arsenide film; and/or
The thickness of the buffer layer is 50-2000nm.
Still provide, a hall device structure, wherein, include the epitaxial layer structure as above, still include:
the protective structure covers the upper surface of the indium arsenide functional layer;
a passivation structure covering the protection structure;
and the electrode layer comprises a plurality of separated electrodes, the plurality of electrodes penetrate through the passivation structure and the protection structure from the upper surface of the passivation structure, and the bottoms of the plurality of electrodes are in contact with the indium arsenide functional layer.
Further, the protection structure includes:
an indium arsenide isolation layer covering the indium arsenide functional layer;
and the cap layer covers the indium arsenide isolation layer.
Furthermore, the indium arsenide isolation layer is a non-doped high-temperature indium arsenide thin film layer; and/or
The thickness of the indium arsenide isolation layer is 2nm-100nm.
Further, the cap layer is one of a gallium arsenide thin film layer, an indium gallium arsenide thin film layer or an aluminum gallium arsenide thin film layer; and/or
The thickness of the cap layer is 2nm-100nm.
Further, the passivation structure includes:
an inorganic passivation layer covering an upper surface of the protection structure;
and the organic passivation layer covers the inorganic passivation layer.
Further, the inorganic passivation layer is a silicon oxide or silicon nitride or a combination layer of silicon oxide and silicon nitride; and/or
The thickness of the inorganic passivation layer is 200nm-1000nm.
Further, the organic passivation layer is a cured photoresist layer.
Further, the electrode layer is of a titanium-gold composite structure; and/or
The thickness of the electrode layer is 200nm-2000nm.
Also provided is a preparation method of the indium arsenide thin film epitaxial layer, wherein the preparation method comprises the following steps:
step S1, providing a gallium arsenide substrate;
s2, forming a buffer layer on the upper surface of the gallium arsenide substrate;
s3, preparing an indium arsenide buffer structure on the upper surface of the buffer layer;
and S4, forming an indium arsenide functional layer on the upper surface of the indium arsenide buffer structure.
Further, in the step S2, the buffer layer is a gallium arsenide buffer layer, and the method for forming the gallium arsenide buffer layer includes homoepitaxially growing a gallium arsenide thin film with a first thickness on the upper surface of the gallium arsenide substrate at a first temperature.
Further, the first temperature is 600-800 ℃; and/or
The first thickness is 50nm-2000nm.
Further, the method for preparing the indium arsenide buffer structure in the step S3 includes:
step S31, heteroepitaxially growing a first indium arsenide thin film with a second thickness on the upper surface of the buffer layer at a second temperature;
step S32, a second indium arsenide thin film with a third thickness is epitaxially grown on the upper surface of the first indium arsenide thin film in a homoepitaxy mode at a third temperature, wherein the third temperature is higher than the second temperature.
Further, the second temperature is 300-500 ℃; and/or
The second thickness is 10nm-100nm.
Further, the third temperature is 500-700 ℃; and/or
The third thickness is 100nm-400nm.
Further, in the step S4, the method for forming the indium arsenide functional layer includes performing homoepitaxial growth on the upper surface of the second indium arsenide thin film at a fourth temperature to form an N-type doped indium arsenide thin film with a fourth thickness.
Further, the fourth temperature is 500-700 ℃; and/or
The fourth thickness is 200nm-1000nm; and/or
The N-type doped doping material is one or more of silicon element, tellurium element and sulfur element; and/or
The doping concentration range of the N-type indium arsenide doped thin film layer is 2E16-2E17cm -3 。
Further, the quotient of the thickness of the first indium arsenide thin film divided by the sum of the thicknesses of the second indium arsenide thin film and the N-type doped indium arsenide thin film is in the range of 0.02-0.2.
The preparation method of the hall device is also provided, wherein the preparation method of the epitaxial layer comprises the following steps:
s5, preparing a protection structure on the upper surface of the indium arsenide thin film epitaxial layer;
s6, forming a passivation layer on the upper surface of the protection structure;
step S7, forming a first mask layer on the upper surface of the passivation layer, patterning the first mask layer, and opening a window on the first mask layer at a position where a corresponding electrode is formed;
s8, etching the protection structure through the first mask layer to form a hole corresponding to the electrode position, and exposing the indium arsenide functional layer at the bottom of the hole;
step S9, removing the first mask layer, forming the electrode in the hole, and enabling the bottom of the electrode to be in contact with the indium arsenide functional layer;
step S10, forming a second mask layer on the upper surfaces of the passivation layer and the electrode, and patterning the second mask layer to open a window at the position of the second mask layer corresponding to the electrode;
and S11, curing the second mask layer.
Further, the step S5 includes:
s51, forming an indium arsenide isolation layer on the upper surface of the indium arsenide thin film epitaxial layer;
and S52, forming a cap layer on the upper surface of the indium arsenide isolation layer.
Further, in step S51, the method for forming the indium arsenide isolation layer includes homoepitaxially growing the indium arsenide isolation layer with a fifth thickness at a fifth temperature.
Further, the fifth temperature is 500-700 ℃; and/or
The fifth thickness is 2nm-100nm.
Further, in step S52, the method for forming the cap layer includes heteroepitaxially growing a cap layer with a sixth thickness at a sixth temperature.
Furthermore, the cap layer is made of one of a gallium arsenide thin film layer, an indium gallium arsenide thin film layer and an aluminum gallium arsenide thin film layer; and/or
The sixth temperature is 500-700 ℃; and/or
The sixth thickness is 2nm to 100nm.
Further, in the step S6, the passivation layer is made of silicon oxide, silicon nitride, or a combination of the silicon oxide and the silicon nitride; and/or
In the step S6, the thickness of the passivation layer is 200nm-1000nm.
Further, the electrode in the step S9 is made of a composite structure of metal titanium and gold; and/or
In the step S9, the thickness of the electrode is 200nm-2000nm.
Further, in the step S7, the first mask layer is a photoresist layer; and/or
In step S10, the second mask layer is a photoresist layer.
According to the epitaxial layer structure of the indium arsenide thin film, which is provided by the invention, the indium arsenide buffer structure is added, the carrier mobility can be improved, and the impurity doping concentration can be reduced, so that the impurity scattering is reduced, and the signal-to-noise ratio is improved on the basis of not reducing the sensitivity;
according to the Hall device structure provided by the invention, the indium arsenide buffer structure is added, the carrier mobility can be improved, the impurity doping concentration is reduced, the impurity scattering is reduced, the signal to noise ratio is improved on the basis of not reducing the sensitivity, the damage or performance change of the indium arsenide thin film in the subsequent process is avoided through the protection structure, and the carrier concentration and the mobility of the indium arsenide thin film are further ensured to be in a stable state in the subsequent process.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic structural diagram of an embodiment of an epitaxial layer structure of an indium arsenide thin film provided in the present invention;
FIG. 2 is a schematic structural diagram of an embodiment of a Hall device provided by the invention;
FIG. 3 is a flowchart illustrating steps of a method for forming an epitaxial layer of an indium arsenide thin film according to an embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating a state after step S4 is completed in the embodiment of the method for manufacturing an epitaxial layer of an indium arsenide thin film according to the present invention;
FIG. 5 is a flowchart illustrating a step S3 of an exemplary method for fabricating an epitaxial layer of an indium arsenide thin film;
FIG. 6 is a flowchart illustrating steps of a method for fabricating a Hall device according to an embodiment of the present invention
Fig. 7 is a schematic state diagram of the embodiment of the method for manufacturing a hall device according to the present invention after step S8 is completed;
fig. 8 is a schematic state diagram of the embodiment of the method for manufacturing a hall device according to the present invention after step S11 is completed;
fig. 9 is a top view of the embodiment of the method for manufacturing a hall device according to the present invention after step S12 is completed;
fig. 10 is a flowchart of steps after step S5 of the embodiment of the method for manufacturing a hall device according to the present invention.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the following embodiments, and it should be understood that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, the technical solution of the present invention includes an epitaxial layer structure of an indium arsenide thin film, which may include:
a gallium arsenide substrate 1;
a buffer layer 2 covering the upper surface of the gallium arsenide substrate 1;
an indium arsenide buffer structure 3 covering the buffer layer 2;
and the indium arsenide functional layer 4 covers the upper surface of the indium arsenide buffer structure 3.
In the above technical solution, by providing the buffer layer 2, lattice adaptation between the indium arsenide buffer structure 3 and the gallium arsenide substrate 1 can be improved, and by providing the indium arsenide buffer structure 3, carrier mobility of the indium arsenide functional layer 4 can be greatly improved, so that it is possible to reduce doping concentration of the indium arsenide functional layer 4, and then the signal-to-noise ratio of the hall device adopting the indium arsenide epitaxial structure in the technical solution can be improved on the basis of not reducing sensitivity.
On the basis of the above technical solution, further, the indium arsenide buffer structure 3 may include:
a first type indium arsenide layer 31 covering the buffer layer 2;
a second type indium arsenide layer 32 covering the first type indium arsenide layer 31.
On the basis, further, the first type indium arsenide layer 31 can adopt a non-doped low-temperature indium arsenide thin film layer; further preferably, the second type indium arsenide layer 32 may be an undoped high temperature indium arsenide thin film layer. The low-temperature indium arsenide thin film layer herein refers to an indium arsenide layer grown at 300 ℃ to 500 ℃, and the high-temperature indium arsenide thin film layer herein refers to an indium arsenide layer grown at 500 ℃ to 700 ℃.
The indium arsenide buffer structure 3 can reduce the defect density between the interfaces of the indium arsenide thin film layers, and greatly improve the carrier mobility of the indium arsenide functional layer 4, so that the possibility of reducing the doping concentration of the indium arsenide functional layer 4 is provided.
On this basis, the thickness of the first type indium arsenide layer 31 may be 10 to 100nm, and it is further preferable that the thickness of the first type indium arsenide layer 31 may be 20 to 80nm.
On this basis, the thickness of the second type indium arsenide layer 32 may be 100 to 400nm, and it is further preferable that the thickness of the second type indium arsenide layer 32 may be 100 to 300nm.
In the technical scheme baseBased on the above, further, the indium arsenide functional layer 4 may be an N-type doped indium arsenide thin film layer, and the doping concentration range of the N-type doped indium arsenide thin film layer may be 2E16-2E17cm -3 . Through the lower doping concentration, the impurity scattering of the N-type indium arsenide doped thin film layer can be effectively reduced, and therefore the signal to noise ratio of the indium arsenide functional layer 4 is improved.
Based on the above technical solution, further, the quotient obtained by dividing the thickness of the first type indium arsenide layer 31 by the sum of the thicknesses of the second type indium arsenide layer 32 and the indium arsenide functional layer 4 is in the range of 0.02 to 0.2. That is, when the thickness of the first type indium arsenide layer 31 is a, the thickness of the second type indium arsenide layer 32 is b, the thickness of the indium arsenide functional layer 4 is c, and a/(b + c) = x, and x is controlled to be in a range of 0.02 or more and 0.2 or less, the carrier mobility of the indium arsenide functional layer 4 can be maximally improved.
On the basis of the above technical solution, the buffer layer 2 may further adopt a gallium arsenide thin film, and lattice adaptation between the indium arsenide buffer structure 3 and the gallium arsenide substrate 1 may be improved by the gallium arsenide thin film, and further, other buffer structures for adjusting lattice adaptation between the indium arsenide layer and the gallium arsenide substrate, which are known to those skilled in the art, may be used as the buffer layer 2 in the above technical solution; on this basis, further, the thickness of the buffer layer may be 50 to 2000nm.
In the technical solution of the present invention, the hall device structure is further included, as shown in fig. 2, wherein the hall device structure includes the epitaxial layer structure as described above, and further includes:
a protective structure 5 covering the upper surface of the indium arsenide functional layer 4;
a passivation structure 6 covering the protection structure 5;
an electrode layer comprising a plurality of separated electrodes 7, the plurality of electrodes 7 penetrate the passivation structure 6 and the protection structure 5 from the upper surface of the passivation structure 6, and the bottom of the plurality of electrodes 7 is in contact with the indium arsenide functional layer 4.
According to the technical scheme, the protective structure 5 is provided, so that the indium arsenide functional layer 4 can be prevented from being damaged or changed in surface state in the subsequent process, and the carrier mobility of the indium arsenide functional layer is further ensured not to be reduced.
On the basis of the above technical solution, further, the protection structure 5 includes:
an indium arsenide isolation layer 51 covering the indium arsenide functional layer 4;
a cap layer 52 covering the indium arsenide isolation layer 51.
In the technical scheme, the interface defect between the indium arsenide functional layer 4 and the cap layer 52 can be reduced through the indium arsenide isolation layer 51, and further, the damage to the indium arsenide functional layer 4 caused by a subsequent chip preparation process, such as mechanical stress on the indium arsenide functional layer caused by a subsequently prepared passivation layer, and the problems of impurity diffusion in the subsequent process can be avoided through the cap layer 52.
On this basis, the indium arsenide isolation layer 51 may be an undoped high-temperature indium arsenide thin film layer; further alternatively, the thickness of the indium arsenide isolation layer may be 2nm to 100nm.
On this basis, the cap layer 52 can be one of a gallium arsenide thin film layer, an indium gallium arsenide thin film layer or an aluminum gallium arsenide thin film layer; further alternatively, the thickness of the cap layer 52 may be 2nm to 100nm.
Further, the passivation structure 6 may include:
an inorganic passivation layer 61 covering the upper surface of the protection structure 5;
an organic passivation layer 62 covering the inorganic passivation layer 61.
In the technical scheme, the passivation structure 6 plays the protection roles of impact resistance, pressure resistance, water and oxygen barrier and the like.
On this basis, the inorganic passivation layer 61 may alternatively adopt a silicon oxide or silicon nitride or a combination layer of silicon oxide and silicon nitride; further alternatively, the thickness of the inorganic passivation layer 61 may be 200nm to 1000nm. The main function of the inorganic passivation layer 61 is to provide dielectric properties and to prevent water oxygen ingress.
As a further alternative, the organic passivation layer 62 may be a cured photoresist layer, which has better impact resistance and pressure resistance than silicon oxide and silicon nitride, which are hard materials, because the photoresist layer is a soft material. In the above technical solution, the photoresist preferably has the characteristics of high dielectric constant, low stress, low thermal expansion coefficient, low water absorption, etc., and the organic passivation layer 62 is formed after the activity of the photoresist is reduced by baking at a high temperature.
On the basis of the above technical solutions, further, the electrode layer is a titanium-gold composite structure, and the titanium-gold composite structure electrode is a technique well known to those skilled in the art, and thus is not described in detail, and the electrode layer is formed in an electrode form of other structure not excluded in the present application; further alternatively, the thickness of the electrode layer may be 200nm to 2000nm.
In the technical solution of the present invention, a method for preparing an indium arsenide thin film epitaxial layer is also included, as shown in fig. 3 and 4, wherein the method includes the following steps:
step S1, providing a GaAs substrate 110;
s2, forming a buffer layer 120 on the upper surface of the GaAs substrate;
s3, preparing an indium arsenide buffer structure 130 on the upper surface of the buffer layer 120;
in step S4, an indium arsenide functional layer 140 is formed on the upper surface of the indium arsenide buffer structure 130.
In the above technical solution, by providing the buffer layer 120, lattice adaptation between the indium arsenide buffer structure 130 and the gallium arsenide substrate 110 can be improved, and by providing the indium arsenide buffer structure 130, carrier mobility of the indium arsenide functional layer 140 can be greatly improved, so that it is possible to reduce doping concentration of the indium arsenide functional layer 140, and further, signal-to-noise ratio of the hall device adopting the indium arsenide epitaxial structure in the technical solution can be improved on the basis of not reducing sensitivity.
Based on the above technical solution, further, in step S2, the buffer layer 120 is a gaas buffer layer, and the method for forming the gaas buffer layer 120 includes epitaxially growing a gaas film with a first thickness on the upper surface of the gaas substrate 110 at a first temperature. Lattice adaptation between the indium arsenide buffer structure 130 and the gallium arsenide substrate 110 may be improved by the gallium arsenide thin film.
Further on, the first temperature may be 600 ℃ to 800 ℃.
Further, the first thickness may be 50nm to 2000nm.
In a preferred embodiment, the gallium arsenide thin film may be grown by a metal organic chemical vapor deposition process, and the specific method may include performing epitaxial growth by using arsine or tert-butylarse as an arsenic source, trimethyl gallium as a gallium source, hydrogen as a carrier gas, at a growth temperature of 600 ℃ to 800 ℃, at a pressure of 50mbar to 500mbar, and at a v/III ratio of 20 to 200.
Based on the above technical solution, as shown in fig. 5, the method for preparing the indium arsenide buffer structure 130 in step S3 may include:
step S31, heteroepitaxially growing a first indium arsenide thin film 131 with a second thickness on the upper surface of the buffer layer 120 at a second temperature;
in step S32, a second indium arsenide thin film 132 with a third thickness is epitaxially grown on the upper surface of the first indium arsenide thin film 131 at a third temperature, where the third temperature is higher than the second temperature.
Further, the second temperature may be 300 ℃ to 500 ℃.
On this basis, the second thickness may optionally be 10nm to 100nm.
Further, the third temperature may be 500 ℃ to 700 ℃.
On this basis, the third thickness may optionally be from 100nm to 400nm.
By the indium arsenide buffer structure 130, the defect density between the interfaces of the indium arsenide thin film layers can be reduced, and the carrier mobility of the indium arsenide functional layer 140 can be greatly improved, so that the possibility of reducing the doping concentration of the indium arsenide functional layer 140 is provided.
In a preferred embodiment, the first indium arsenide thin film 131 may be grown using a mocvd (metal organic chemical vapor deposition) process, and the specific method may include performing epitaxial growth using arsine or tertiarybutylarsene as an arsenic source, trimethylgallium indium as an indium source, at a temperature of 300 ℃ to 500 ℃, at a pressure of 50mbar to 500mbar, and at a v/III ratio of 20 to 200.
In a preferred embodiment, the first indium arsenide thin film 132 may be grown using a metal organic chemical vapor deposition process, and the specific method may include performing epitaxial growth by using arsine or tert-butylarse as an arsenic source, using indium gallium trimethyl oxide as an indium source, at a growth temperature of 500 ℃ to 700 ℃, at a pressure of 50mbar to 500mbar, and at a v/III ratio of 20 to 200.
Based on the above technical solution, further, in step S4, the method for forming the indium arsenide functional layer 140 may include performing homoepitaxial growth on the upper surface of the second indium arsenide thin film 132 at a fourth temperature to form an N-type doped indium arsenide thin film with a fourth thickness.
Further, the fourth temperature may be 500 ℃ to 700 ℃.
On the basis, the fourth thickness is 200nm-1000nm.
Further optionally, the N-type doped material is one or more of silicon, tellurium and sulfur.
Further optionally, the doping concentration range of the N-type doped indium arsenide thin film layer is 2E16-2E17cm -3 。
Through the lower doping concentration, the impurity scattering of the N-type indium arsenide doped thin film layer can be effectively reduced, so that the signal-to-noise ratio of the indium arsenide functional layer 140 is improved.
Based on the above technical solution, further, the quotient obtained by dividing the thickness of the first indium arsenide thin film 131 by the sum of the thicknesses of the second indium arsenide thin film 132 and the N-type doped indium arsenide thin film is in the range of 0.02-0.2. That is, when the thickness of the first type indium arsenide layer 31 is a, the thickness of the second type indium arsenide layer 32 is b, the thickness of the N-type doped indium arsenide thin film is c, and a/(b + c) = x, and x is controlled to be greater than or equal to 0.02 and less than or equal to 0.2, the carrier mobility of the indium arsenide functional layer 140 can be improved to the maximum extent.
In the technical solution of the present invention, a method for manufacturing a hall device is further included, where the method includes the above method for manufacturing an epitaxial layer, as shown in fig. 6, and may further include:
s5, preparing a protective structure 150 on the upper surface of the indium arsenide thin film epitaxial layer;
step S6, forming a passivation layer 161 on the upper surface of the protection structure;
step S7, forming a first mask layer 101 on the upper surface of the passivation layer 161, and patterning the first mask layer 101, so that the first mask layer 101 opens a window at a position where the corresponding electrode is formed;
step S8, etching the protection structure 150 through the first mask layer 101 to form a hole corresponding to the electrode position, and exposing the indium arsenide functional layer 140 at the bottom of the hole to form the structure shown in fig. 7;
step S9, removing the first mask layer 101, and forming an electrode 170 in the hole, so that the bottom 170 of the electrode is in contact with the indium arsenide functional layer 140;
step S10, forming a second mask layer 162 on the upper surfaces of the passivation layer 161 and the electrode 170, and patterning the second mask layer 162 to open a window in the second mask layer 162 corresponding to the electrode 170;
in step S11, the second mask layer 162 is cured to form the structure shown in fig. 8, and the hall device structure shown in fig. 9 is formed.
According to the technical scheme, the protective structure 150 is provided, so that the indium arsenide functional layer 140 can be prevented from being damaged or changed in performance in the subsequent process, and the carrier mobility of the indium arsenide functional layer is further ensured not to be reduced.
On the basis of the above technical solution, as shown in fig. 10, step S5 may include:
s51, forming an indium arsenide isolation layer 151 on the upper surface of the indium arsenide thin film epitaxial layer;
in step S52, a cap layer 152 is formed on the top surface of the InAs isolation layer.
On the basis, in step S51, the method for forming the indium arsenide isolation layer 151 may further include homoepitaxially growing a fifth thickness of the indium arsenide isolation layer 151 at a fifth temperature.
On the basis, the fifth temperature is 500-700 ℃.
On the basis, the fifth thickness is 2nm-100nm.
On the basis, in step S52, the method for forming the cap layer 152 may further include heteroepitaxially growing a sixth thickness of the cap layer 152 at a sixth temperature.
On this basis, the cap layer 152 may be made of one of a gallium arsenide thin film layer, an indium gallium arsenide thin film layer, and an aluminum gallium arsenide thin film layer.
On this basis, the sixth temperature is optionally 500 ℃ to 700 ℃.
On the basis, the sixth thickness is 2nm-100nm.
In the technical scheme, the interface defect between the indium arsenide functional layer 140 and the cap layer 152 can be reduced through the indium arsenide isolation layer 151, and further, damage and performance change of the subsequent chip preparation process to the indium arsenide functional layer 140, such as mechanical stress of the subsequently prepared passivation layer 161 to the indium arsenide functional layer 140, impurity diffusion in the subsequent process and the like can be avoided through the cap layer 152.
In a preferred embodiment, the indium arsenide isolation layer 151 may be grown using a metal organic chemical vapor deposition process, and the specific method may include performing epitaxial growth by using arsine or tert-butylarse as an arsenic source and indium gallium trimethyl oxide as an indium source, and setting the growth temperature to 500 ℃ to 700 ℃, the pressure to 50mbar to 500mbar, and the v/III ratio to 20 to 200.
In a preferred embodiment, when a gallium arsenide thin film is used as the cap layer 152, the gallium arsenide thin film can be grown by a metal organic chemical vapor deposition process, and the method includes performing epitaxial growth by using arsine or tert-butylarse as an arsenic source, using trimethylgallium as a gallium source, setting the growth temperature to 500 ℃ -700 ℃, setting the pressure to 50mbar-500mbar, and setting the v/III ratio to 20-200.
Based on the above technical solution, further, in step S6, the passivation layer 161 may be made of silicon oxide, silicon nitride, or a combination of the two.
On the basis, in step S6, the thickness of the passivation layer may be 200nm to 1000nm.
In this technical solution, the passivation layer 161 can play a role in protection against impact, stress, water and oxygen.
In a preferred embodiment, the passivation layer 161 may be formed using a plasma enhanced chemical vapor deposition process, and when the passivation material is silicon nitride, the passivation temperature may be set to 200 ℃ to 400 ℃.
In a preferred embodiment, in step S7, the first mask layer 101 may be a photoresist layer, the first mask layer 101 may be formed on the upper surface of the passivation layer 161 by using a photoresist spin-coating process, further, the first mask layer 101 may be exposed by using a patterned photomask, the pattern of the photomask may correspond to the formation position of the electrode 170, and then the photoresist at the position of the window may be removed by a developing process to open the window corresponding to the formation position of the electrode 170.
On the basis of the above preferred embodiment, further, in step S8, the passivation layer 161 exposed by the window may be removed by BOE (buffered oxide etching solution), and the cap layer 152 and the indium arsenide isolation layer 151 exposed subsequently may be further removed by BOE until the indium arsenide functional layer 140 is exposed in the window.
Based on the above technical solution, further, in step S9, the material of the electrode 170 may be a titanium-gold composite structure, and the titanium-gold composite structure electrode is well known to those skilled in the art, so that details are not described herein, and the electrode form of other structures is not excluded in the present application to form the electrode layer.
On this basis, optionally, in step S9, the thickness of the electrode may be 200nm to 2000nm.
In a preferred embodiment, in step S9, the first mask layer 101 may be removed by a photoresist stripping process, and then a titanium-gold composite structure layer is vapor-deposited on the indium arsenide functional layer 140 exposed in the window by using a metal vapor deposition process to form the electrode 170.
In a preferred embodiment, in step S10, the second mask layer 162 may be a photoresist layer, the second mask layer 162 may be formed on the upper surfaces of the passivation layer 161 and the electrode 170 by using a photoresist spin coating process, further, the second mask layer 162 may be exposed by using a mask used in the previous exposure of the first mask layer, and then the photoresist at the window position may be removed by a developing process to open the window corresponding to the formation position of the electrode 170. In step S11, after the second mask layer 162 is formed, the second mask layer 162 may be cured by a high temperature baking process to serve as an organic passivation layer. Since the photoresist is a soft material, it has better impact resistance and stress resistance than silicon oxide and silicon nitride which are hard materials. In an embodiment, the photoresist is preferably a photoresist having characteristics such as high dielectric constant, low stress, low thermal expansion coefficient, and low water absorption, and the photoresist activity can be reduced by baking at a high temperature.
The beneficial effects of the above technical solutions are described below by the test data of two sets of samples, and it should be noted that the sample specification in the test is only used for illustrating the feasibility and the beneficial effects, and the protection scope of the present application is not limited thereby.
1. Sensitivity contrast
Sample a: an indium arsenide hall device adopting the structure and process of the above embodiment, wherein Rin (input resistance) = Rout (output resistance) =400 Ω;
sample B: in the indium arsenide hall device, in comparison with sample a, which lacks the indium arsenide buffer structure, rin (input resistance) = Rout (output resistance) =400 Ω.
Both sample a and sample B were driven using a 2.5V constant voltage.
Comparing test data of the samples A and B:
| low temperature indium arsenide thin film Buffer layer thickness (n)m) | High temperature indium arsenide film buffer Strike layer thickness (nm) | N-type indium arsenide functional layer Thickness (nm) | Mobility of N-type indium arsenide functional layer ( cm 2 /Vs) | Sensitivity (mV- V/Gs) | |
| Sample A | 50 | 300 | 600 | 12000 | 0.035 |
| Sample B | 0 | 0 | 600 | 8000 | 0.023 |
2. Signal-to-noise ratio comparison using different epitaxial layers
Sample a: an indium arsenide hall device adopting the structure and process of the above embodiment, wherein Rin (input resistance) = Rout (output resistance) =400 Ω;
sample B: in the indium arsenide hall device, in comparison with sample a, which lacks the indium arsenide buffer structure, rin (input resistance) = Rout (output resistance) =400 Ω.
Sample C: gallium arsenide hall device, rin (input resistance) = Rout (output resistance) =400 Ω.
Samples a, B, C were all driven using a 2.5V constant voltage.
Comparing test data of the samples A, B and C:
| bias voltage (V) | Sensitivity (mV/V/Gs) | Noise spectral density @1Hz (nV/√ Hz) | Sensitivity signal-to-noise ratio (sample A signal-to-noise ratio is taken as reference value 1) | |
| Sample A | 2.5 | 0.035 | 200 | 1 |
| Sample B | 2.5 | 0.023 | 400 | 0.4 |
| Sample C | 2.5 | 0.020 | 700 | 0.2 |
3. Signal-to-noise ratio comparison of different doping concentrations of indium arsenide functional layer
Sample a: the indium arsenide hall device adopting the structure and process of the above embodiment, wherein the doping concentration of the N-type doped indium arsenide layer is 5E16-1e17, rin (input resistance) = Rout (output resistance) =400 Ω;
sample B: the indium arsenide hall device adopting the structure and the process of the above embodiment, wherein the doping concentration of the N-type doped indium arsenide layer is 2E17-2.5E17, rin (input resistance) = Rout (output resistance) =400 Ω;
sample C: an indium arsenide hall device, which is less in indium arsenide buffer structure than sample a, wherein the doping concentration of the N-type doped indium arsenide layer is 5E 16-1ee17, rin (input resistance) = Rout (output resistance) =400 Ω;
samples a, B, C were all driven using a 2.5V constant voltage.
Comparing test data of samples A, B and C:
| bias voltage (V) | Sensitivity (mV/V/Gs) | Noise spectral density @1Hz (nV/√ Hz) | Sensitivity signal-to-noise ratio (sample A signal-to-noise ratio is taken as reference value 1) | |
| Sample A | 2.5 | 0.035 | 200 | 1 |
| Sample B | 2.5 | 0.045 | 550 | 0.6 |
| Sample C | 2.5 | 0.023 | 400 | 0.4 |
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and these modifications or substitutions do not depart from the spirit of the corresponding technical solutions of the embodiments of the present invention.
Claims (33)
1. An epitaxial layer structure of an indium arsenide thin film, comprising:
a gallium arsenide substrate;
the buffer layer covers the upper surface of the gallium arsenide substrate;
an indium arsenide buffer structure covering the buffer layer;
and the indium arsenide functional layer covers the upper surface of the indium arsenide buffer structure.
2. The epitaxial layer structure of claim 1, wherein the indium arsenide buffer structure comprises:
a first type indium arsenide layer covering the buffer layer;
a second type indium arsenide layer overlying the first type indium arsenide layer.
3. The epitaxial layer structure of claim 2, wherein the first type indium arsenide layer is an undoped low temperature indium arsenide thin film layer; and/or
The second type indium arsenide layer is an undoped high-temperature indium arsenide thin film layer.
4. The epitaxial layer structure of claim 2, wherein the first type indium arsenide layer has a thickness of 10 to 100nm; and/or
The thickness of the second type indium arsenide layer is 100-400nm.
5. The epitaxial layer structure of claim 2, wherein the indium arsenide functional layer is an N-type doped indium arsenide thin film layer with a doping concentration in the range of 2E16-2E17cm -3 。
6. The epitaxial layer structure of claim 2, wherein a quotient of the thickness of the first type indium arsenide layer divided by the sum of the thicknesses of the second type indium arsenide layer and the indium arsenide functional layer is in a range of 0.02 to 0.2.
7. The epitaxial layer structure of claim 1, wherein the buffer layer is a gallium arsenide thin film; and/or
The thickness of the buffer layer is 50-2000nm.
8. A hall device structure comprising the epitaxial layer structure of any one of claims 1-7, further comprising:
the protective structure is covered on the upper surface of the indium arsenide functional layer;
a passivation structure covering the protection structure;
and the electrode layer comprises a plurality of separated electrodes, the plurality of electrodes penetrate through the passivation structure and the protection structure from the upper surface of the passivation structure, and the bottoms of the plurality of electrodes are in contact with the indium arsenide functional layer.
9. The hall device structure of claim 8 wherein the protective structure comprises:
an indium arsenide isolation layer covering the indium arsenide functional layer;
and the cap layer covers the indium arsenide isolation layer.
10. The hall device structure of claim 9 wherein the indium arsenide isolation layer is an undoped high temperature indium arsenide thin film layer; and/or
The thickness of the indium arsenide isolation layer is 2nm-100nm.
11. The hall device structure of claim 9 wherein the cap layer is one of a gallium arsenide thin film layer, an indium gallium arsenide layer, or an aluminum gallium arsenide layer; and/or
The thickness of the cap layer is 2nm-100nm.
12. The hall device structure of claim 8 wherein the passivation structure comprises:
an inorganic passivation layer covering an upper surface of the protection structure;
and the organic passivation layer covers the inorganic passivation layer.
13. The hall device structure of claim 12 wherein the inorganic passivation layer is a silicon oxide or silicon nitride or a combination of silicon oxide and silicon nitride; and/or
The thickness of the inorganic passivation layer is 200nm-1000nm.
14. The hall device structure of claim 12 wherein the organic passivation layer is a cured photoresist layer.
15. The hall device structure of claim 12 wherein the electrode layer is a titanium-gold composite structure; and/or
The thickness of the electrode layer is 200nm-2000nm.
16. A preparation method of an indium arsenide thin film epitaxial layer is characterized by comprising the following steps:
step S1, providing a gallium arsenide substrate;
s2, forming a buffer layer on the upper surface of the gallium arsenide substrate;
s3, preparing an indium arsenide buffer structure on the upper surface of the buffer layer;
and S4, forming an indium arsenide functional layer on the upper surface of the indium arsenide buffer structure.
17. The method of claim 16, wherein in step S2, the buffer layer is a gaas buffer layer, and the step of forming the gaas buffer layer comprises homoepitaxially growing a gaas film of a first thickness on the upper surface of the gaas substrate at a first temperature.
18. The method of claim 17, wherein the first temperature is 600 ℃ to 800 ℃; and/or
The first thickness is 50nm to 2000nm.
19. The method of claim 16, wherein the step S3 of fabricating the indium arsenide buffer structure comprises:
step S31, heteroepitaxially growing a first indium arsenide thin film with a second thickness on the upper surface of the buffer layer at a second temperature;
step S32, a second indium arsenide thin film with a third thickness is epitaxially grown on the upper surface of the first indium arsenide thin film in a homoepitaxy mode at a third temperature, wherein the third temperature is higher than the second temperature.
20. The method of claim 19, wherein the second temperature is from 300 ℃ to 500 ℃; and/or
The second thickness is 10nm-100nm.
21. The method of claim 19, wherein the third temperature is from 500 ℃ to 700 ℃; and/or
The third thickness is 100nm-400nm.
22. The method of claim 19, wherein in step S4, the step of forming the functional indium arsenide layer comprises homoepitaxially growing an N-type doped indium arsenide thin film of a fourth thickness on the top surface of the second indium arsenide thin film at a fourth temperature.
23. The method of claim 22, wherein the fourth temperature is from 500 ℃ to 700 ℃; and/or
The fourth thickness is 200nm-1000nm; and/or
The N-type doped material is one or more of silicon element, tellurium element and sulfur element; and/or
The doping concentration range of the N-type indium arsenide doped thin film layer is 2E16-2E17cm -3 。
24. The method of claim 22, wherein the quotient of the thickness of the first indium arsenide thin film divided by the sum of the thicknesses of the second indium arsenide thin film and the N-type doped indium arsenide thin film is in the range of 0.02 to 0.2.
25. A method for manufacturing a hall device comprising the method for manufacturing an epitaxial layer according to any one of claims 16 to 24, further comprising:
s5, preparing a protection structure on the upper surface of the indium arsenide thin film epitaxial layer;
s6, forming a passivation layer on the upper surface of the protection structure;
s7, forming a first mask layer on the upper surface of the passivation layer, and patterning the first mask layer to open a window at the position where the first mask layer is formed corresponding to the electrode;
step S8, etching the protection structure through the first mask layer to form a hole corresponding to the electrode position, and exposing the indium arsenide function layer at the bottom of the hole;
step S9, removing the first mask layer, forming the electrode in the hole, and enabling the bottom of the electrode to be in contact with the indium arsenide functional layer;
step S10, forming a second mask layer on the upper surfaces of the passivation layer and the electrode, and patterning the second mask layer to open a window at the position of the second mask layer corresponding to the electrode;
and S11, curing the second mask layer.
26. The method of claim 25, wherein the step S5 comprises:
s51, forming an indium arsenide isolation layer on the upper surface of the indium arsenide thin film epitaxial layer;
and S52, forming a cap layer on the upper surface of the indium arsenide isolation layer.
27. The method of claim 26, wherein the step S51 of forming the indium arsenide isolation layer comprises homoepitaxially growing a fifth thickness of the indium arsenide isolation layer at a fifth temperature.
28. The method of claim 27, wherein the fifth temperature is 500 ℃ to 700 ℃; and/or
The fifth thickness is 2nm-100nm.
29. The method of claim 26, wherein the step S52, forming the cap layer comprises heteroepitaxially growing a sixth thickness of the cap layer at a sixth temperature.
30. The method according to claim 29, wherein the cap layer is made of one of a gallium arsenide film layer, an indium gallium arsenide layer and an aluminum gallium arsenide layer; and/or
The sixth temperature is 500-700 ℃; and/or
The sixth thickness is 2nm to 100nm.
31. The method of claim 25, wherein in step S6, the passivation layer is made of silicon oxide, silicon nitride or a combination thereof; and/or
In the step S6, the thickness of the passivation layer is 200nm-1000nm.
32. The method according to claim 25, wherein the electrode in step S9 is made of a titanium-gold composite structure; and/or
In the step S9, the thickness of the electrode is 200nm-2000nm.
33. The method according to claim 25, wherein in step S7, the first mask layer is a photoresist layer; and/or
In step S10, the second mask layer is a photoresist layer.
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| JPH03288482A (en) * | 1990-04-04 | 1991-12-18 | Asahi Chem Ind Co Ltd | Highly reliable and highly sensitive inas hall element |
| JP2008066582A (en) * | 2006-09-08 | 2008-03-21 | Asahi Kasei Electronics Co Ltd | Hall element |
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