CN204332968U - A kind of plane indium gallium arsenic photosensor chip improving surface passivation - Google Patents
A kind of plane indium gallium arsenic photosensor chip improving surface passivation Download PDFInfo
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- CN204332968U CN204332968U CN201420770646.3U CN201420770646U CN204332968U CN 204332968 U CN204332968 U CN 204332968U CN 201420770646 U CN201420770646 U CN 201420770646U CN 204332968 U CN204332968 U CN 204332968U
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- indium gallium
- gallium arsenic
- silicon nitride
- layer
- passivation
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Abstract
This patent discloses a kind of plane indium gallium arsenic photosensor chip improving surface passivation, the structure of plane indium gallium arsenic photosensor chip is: in semi-insulating InP substrate, grows N-type InP layer successively, indium gallium arsenic Intrinsic Gettering layer, N-type InP cap layers, silicon nitride (SiN
x) passivation layer, P electrode and add thick electrode (8).Preparation technology improves and obtains on original Process ba-sis, comprises the removal of diffusion mask, sulfuration and inductively coupled plasma chemical vapor deposition (ICPCVD) technology growth silicon nitride passive film.The advantage of this patent is: the passivation layer structure of chip is more even; The surface density of states of effective minimizing device, and the sulfide film that surface is formed can avoid surface again oxidized; Technique is little to material surface damage, and Stress match between film densification and substrate, element becomes bonded state good, and passivation effect is excellent.
Description
Technical field
This patent relates to infrared detector fabricating technology, specifically refers to a kind of the plane indium gallium arsenic photosensor chip and the preparation method that improve surface passivation effect, and it is applicable to the plane indium gallium arsenic detector preparing high sensitivity, high reliability.
Background technology
Indium gallium arsenic short-wave infrared detector at room temperature, just can obtain good performance, and this makes it have a wide range of applications at civilian, military and aerospace field.Because plane technique is the preparation of device bring lower damage into, this makes planar device have more excellent performance, is realizing having stronger competitiveness in the high-performance of system, miniaturization, low-power consumption.
As shown in Figure 1, it is by InP substrate 1, N-type InP layer 2, indium gallium arsenic absorbed layer 3, N-type InP cap layers 4, photosensitive diffusion region 5, silicon nitride passivation 6, P electrode 7 and add thick electrode 8 and form for the cross-section structure of plane indium gallium arsenic detector chip.At present, plane technique mainly comprises following 6 large steps:
Step 1. prepares diffusion mask on epitaxial wafer;
Step 2. forms PN junction by Closed Tube Diffusion in epitaxial loayer;
Step 3. opens N groove by being etched on epitaxial wafer;
Step 4. is at device surface deposit silicon nitride passivating film;
Step 5. sputters growth P electrode on the surface in P district;
Step 6. is on surface, N district and P electrode, and sputter Cr, Au metal film is as contact electrode district.
In existing plane indium gallium arsenic detector chip preparation process, epitaxial material not only will experience and expose in atmosphere, and to the pyroprocesses such as diffusion be experienced, the surface passivation effect of silicon nitride diffusion mask can be made to decrease on the one hand, the InP surface that mask window exposes on the other hand also can be subject to serious oxidation.In addition, in the technique of deposit silicon nitride passivating film, the plasma cognition that plasma-reinforced chemical vapor deposition technology (PECVD) produces externally is prolonged material surface and is caused larger damage.These problems in technique all limit the raising of detector dark current performance, therefore need to carry out improvement and bring new ideas in technique, and the performance of detector is got a promotion.
Summary of the invention
Based on Problems existing in above-mentioned planar type detector chip preparing process, this patent proposes a kind of plane indium gallium arsenic photosensor chip promoting surface passivation effect innovatively, improve the passivation of device surface in technique, reduce surface density of states, realize detector dark current and reduce further.
Improve a plane indium gallium arsenic photosensor chip for surface passivation, its structure is: in semi-insulating InP substrate 1, grows N-type InP layer 2 successively, indium gallium arsenic Intrinsic Gettering layer 3, N-type InP cap layers 4, silicon nitride (SiN
x) passivation layer 6, P electrode 7 and add thick electrode 8; Wherein:
One deck silicon nitride (SiN is had in described plane indium gallium arsenic photosensor chip surface coverage
x) passivation layer 6, this passivation layer is the thickness in monolayer homogeneous silicon nitride layer not comprising mask layer.
This patent improves on existing technology basis.First, after opening N groove, introduce and remove diffusion mask and wet method sulfuration two-step process; Secondly, improve at the growing technology of silicon nitride passive film, become ICPCVD technology by original PECVD technological improvement.As shown in Figure 2, concrete technology process step is as follows:
1 epitaxial wafer material clean, adopt chloroform, ether, acetone, MOS level ethanol purge successively, nitrogen dries up;
2 deposit silicon nitride diffusion mask, as diffusion mask layer, it is the silicon nitride of 230nm that using plasma strengthens chemical vapor deposition (PECVD) deposition techniques thickness, and underlayer temperature is 330 DEG C, RF power is 40W, gas flow is SiH
4: N
2=50mL/min:900mL/min;
3 open diffusion window, and adopt inductively coupled plasma (ICP) lithographic technique etch silicon nitride, etching condition is: ICP power is 2000W, RF power is 40W, SF
6gas flow 45sccm, chamber pressure are 9.4mTorr, temperature is 5 DEG C, then at room temperature corrode 10s with buffered hydrofluoric acid solution, and corrosive liquid volume ratio is HF:NH
4f:H
2o=3:6:10;
4 Closed Tube Diffusion, form photosensitive diffusion region 5, adopt Powdered Zn
3p
2as diffuse source, vacuum degree is 3 × 10
-4pa, diffusion conditions is: retention time 12min at 300 DEG C of temperature, then at 530 DEG C of temperature, retention time 9min;
5 open N groove, with buffered hydrofluoric acid solution at room temperature corroding silicon nitride mask, and corrosive liquid proportioning and step 4) identical, adopt argon ion etching technology etching N groove, etching condition is: ion energy 300eV, line 80cm
-3, then wet etching indium gallium arsenic, corrosive liquid volume ratio is tartaric acid solution: H
2o
2=5:1, corrosion temperature remains on 35 DEG C;
6 remove diffusion mask, adopt buffered hydrofluoric acid solution wet etching, corrosive liquid proportioning and step 3) identical;
7 sulfurations, adopt wet method sulfuration, sulfidising solution is sulfur content is 8% ammonium sulfide solution, at ambient temperature, cure time 50 minutes;
8 deposit silicon nitride passivating films, adopt the silicon nitride of inductively coupled plasma chemical vapor deposition (ICPCVD) technology growth 400nm as passivating film 6, growth conditions is: ICP power is 750W, underlayer temperature 75 DEG C, pressure range 12mtorr, gas flow SiH
4: N
2scope is 15.5mL/min:12.5mL/min;
9 open P electrode hole, adopt process conditions and step 3) identical;
10 growth P electrode, as P electrode 7, adopt ion beam sputtering process deposition thickness to be the Au of 50nm, vacuum degree is 3 × 10
-2pa, ion beam energy is 100eV;
11 rapid thermal annealings, annealing conditions is: nitrogen protection atmosphere, and annealing temperature is 450 DEG C, and temperature hold-time is 35s;
12 open N electrode hole, adopt process conditions and step 3) identical;
13 growths add thick electrode, and as adding thick electrode 8, employing ion beam sputtering process successively deposition thickness is respectively Cr, Au of 20nm, 400nm, deposition conditions and step 10) identical;
14 scribings;
15 tests, are tested by spun gold extraction electrode.
The advantage of this patent is:
1 wet method removes the passivation that diffusion mask can strengthen new deposit silicon nitride, because diffusion mask have passed through the destruction of High temperature diffusion, this can make the passivation of diffusion mask itself reduce, and the SiN passivating film passivation of deposit subsequently can be hindered, selective wet etching does not corrode epitaxial material because of this corrosive liquid corroding silicon nitride, damage can not be brought to epitaxial loayer surface, remove the passivation that diffusion mask can strengthen new deposit silicon nitride in a wet process.
2 wet method sulfuration process, wet method sulfuration can remove the oxide layer on InP surface, in and dangling bonds; the surface density of states of effective minimizing device, in addition, sulfuration can form the very thin sulfuric horizon of one deck in epi-layer surface; this sulfuric horizon can protect surface, avoids surperficial oxidation by air.
The technique of deposit silicon nitride passivating film has by 3, and plasma enhanced CVD technique (PECVD) changes inductively coupled plasma chemical vapor deposition method (ICPCVD) into.This is because ICPCVD can low-temperature epitaxy, the stress of film is little; The lower destruction to material surface of energy of plasma produced is smaller; The silicon nitride film of growth is finer and close, and nitrogen becomes bonded state better with silicon.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of the indium gallium arsenic detector chip of this patent.
Fig. 2 is the plane indium gallium arsenic detector chip step of preparation process flow chart of this patent;
In figure:
1---semi-insulating InP substrate;
2---N-type InP layer;
3---indium gallium arsenic Intrinsic Gettering layer;
4---N-type InP cap layers;
5---photosensitive diffusion region;
6---silicon nitride (SiN
x) passivation layer;
7---P electrode;
8---add thick electrode.
Embodiment
Be described in detail below in conjunction with the specific implementation method of accompanying drawing to this patent.
As shown in Figure 1, the present embodiment epitaxial wafer used is for adopting metal organic chemical vapor deposition (MOCVD) technology, be that in the semi-insulating InP substrate 1 of 350 μm, growth thickness is the N-type InP layer 2 of 0.5 μm successively, carrier concentration >2 × 10 at thickness
18cm
-3; Thickness is the indium gallium arsenic Intrinsic Gettering layer 3 of 2.5 μm, and carrier concentration is 5 × 10
16cm
-3; Thickness is the N-type InP cap layers 4 of 1 μm, and carrier concentration is 5 × 10
16cm
-3.The plane indium gallium-arsenide infrared detector chip preparing process of the present embodiment is on existing Process ba-sis, after Closed Tube Diffusion, adds nitrogen atmosphere process of thermal treatment; Before deposit silicon nitride passivating film, introduce the technique removing diffusion mask and sulfuration, and change the depositing technics of passivating film into inductively coupled plasma chemical vapor deposition method by plasma enhanced CVD technique.
Concrete technology flow process prepared by the present embodiment detector chip is:
1 epitaxial wafer material clean, adopt chloroform, ether, acetone, MOS level ethanol purge successively, nitrogen dries up;
2 deposit silicon nitride diffusion mask, as diffusion mask layer, it is the silicon nitride of 230nm that using plasma strengthens chemical vapor deposition (PECVD) deposition techniques thickness, and underlayer temperature is 330 DEG C, RF power is 40W, gas flow is SiH
4: N
2=50mL/min:900mL/min;
3 open diffusion window, and adopt inductively coupled plasma (ICP) lithographic technique etch silicon nitride, etching condition is: ICP power is 2000W, RF power is 40W, SF
6gas flow 45sccm, chamber pressure are 9.4mTorr, temperature is 5 DEG C, then at room temperature corrode 10s with buffered hydrofluoric acid solution, and corrosive liquid volume ratio is HF:NH
4f:H
2o=3:6:10;
4 Closed Tube Diffusion, form photosensitive diffusion region 5, adopt Powdered Zn
3p
2as diffuse source, vacuum degree is 3 × 10
-4pa, diffusion conditions is: retention time 12min at 300 DEG C of temperature, then at 530 DEG C of temperature, retention time 9min;
5 open N groove, with buffered hydrofluoric acid solution at room temperature corroding silicon nitride mask, and corrosive liquid proportioning and step 4) identical, adopt argon ion etching technology etching N groove, etching condition is: ion energy 300eV, line 80cm
-3, then wet etching indium gallium arsenic, corrosive liquid volume ratio is tartaric acid solution: H
2o
2=5:1, corrosion temperature remains on 35 DEG C;
6 remove diffusion mask, adopt buffered hydrofluoric acid solution wet etching, corrosive liquid proportioning and step 3) identical;
7 sulfurations, adopt wet method sulfuration, sulfidising solution is sulfur content is 8% ammonium sulfide solution, at ambient temperature, cure time 50 minutes;
8 deposit silicon nitride passivating films, adopt the silicon nitride of inductively coupled plasma chemical vapor deposition (ICPCVD) technology growth 400nm as passivating film 6, growth conditions is: ICP power is 750W, underlayer temperature 75 DEG C, pressure range 12mtorr, gas flow SiH
4: N
2scope is 15.5mL/min:12.5mL/min;
9 open P electrode hole, adopt process conditions and step 3) identical;
10 growth P electrode, as P electrode 7, adopt ion beam sputtering process deposition thickness to be the Au of 50nm, vacuum degree is 3 × 10
-2pa, ion beam energy is 100eV;
11 rapid thermal annealings, annealing conditions is: nitrogen protection atmosphere, and annealing temperature is 450 DEG C, and temperature hold-time is 35s;
12 open N electrode hole, adopt process conditions and step 3) identical;
13 growths add thick electrode, and as adding thick electrode 8, employing ion beam sputtering process successively deposition thickness is respectively Cr, Au of 20nm, 400nm, deposition conditions and step 10) identical;
14 scribings;
15 tests, are tested by spun gold extraction electrode.
Claims (1)
1. one kind is improved the plane indium gallium arsenic photosensor chip of surface passivation, its structure is: in semi-insulating InP substrate (1), grows N-type InP layer (2) successively, indium gallium arsenic Intrinsic Gettering layer (3), N-type InP cap layers (4), silicon nitride (SiN
x) passivation layer (6), P electrode (7) and add thick electrode (8); It is characterized in that:
One deck silicon nitride (SiN is had in described plane indium gallium arsenic photosensor chip surface coverage
x) passivation layer (6), this passivation layer is the individual layer homogeneous silicon nitride layer not comprising mask layer.
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|---|---|---|---|
| CN201420770646.3U CN204332968U (en) | 2014-12-09 | 2014-12-09 | A kind of plane indium gallium arsenic photosensor chip improving surface passivation |
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|---|---|---|---|
| CN201420770646.3U CN204332968U (en) | 2014-12-09 | 2014-12-09 | A kind of plane indium gallium arsenic photosensor chip improving surface passivation |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104538463A (en) * | 2014-12-09 | 2015-04-22 | 中国科学院上海技术物理研究所 | Planar indium gallium arsenic light-sensitive chip with surface passivation improved and manufacturing method |
| CN109994368A (en) * | 2017-12-29 | 2019-07-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
-
2014
- 2014-12-09 CN CN201420770646.3U patent/CN204332968U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104538463A (en) * | 2014-12-09 | 2015-04-22 | 中国科学院上海技术物理研究所 | Planar indium gallium arsenic light-sensitive chip with surface passivation improved and manufacturing method |
| CN109994368A (en) * | 2017-12-29 | 2019-07-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
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| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20150513 Effective date of abandoning: 20160706 |
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| AV01 | Patent right actively abandoned |
Granted publication date: 20150513 Effective date of abandoning: 20160706 |
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| C25 | Abandonment of patent right or utility model to avoid double patenting |