JP2662039B2 - Bipolar transistor - Google Patents

Bipolar transistor

Info

Publication number
JP2662039B2
JP2662039B2 JP1182953A JP18295389A JP2662039B2 JP 2662039 B2 JP2662039 B2 JP 2662039B2 JP 1182953 A JP1182953 A JP 1182953A JP 18295389 A JP18295389 A JP 18295389A JP 2662039 B2 JP2662039 B2 JP 2662039B2
Authority
JP
Japan
Prior art keywords
layer
emitter
bipolar transistor
resistor
collector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP1182953A
Other languages
Japanese (ja)
Other versions
JPH0346334A (en
Inventor
啓二郎 板倉
大助 上田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP1182953A priority Critical patent/JP2662039B2/en
Publication of JPH0346334A publication Critical patent/JPH0346334A/en
Application granted granted Critical
Publication of JP2662039B2 publication Critical patent/JP2662039B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、大電流のスイッチングに用いられるバイポ
ーラトランジスタに関するものである。
Description: TECHNICAL FIELD The present invention relates to a bipolar transistor used for switching a large current.

従来の技術 バイポーラトランジスタ、特に電力用バイポーラトラ
ンジスタが有する問題の1つとして熱暴走がある。バイ
ポーラトランジスタに起こる熱暴走は、ベース・エミッ
タ間の障壁電位VBEが温度上昇に伴って低下し、これに
よってコレクタ電流が増加し、さらにこのコレクタ電流
の増加によりバイポーラトランジスタ温度が上昇するこ
とから生じる正帰還的な破壊である。電力用の大面積の
素子では特にこの熱暴走が生じやすい。熱暴走を防ぐ方
法として、エミッタ領域に抵抗値の温度係数が正の抵抗
体を形成し、温度上昇によって生ずるVBEの低下分を、
この抵抗体の抵抗値の増加分とエミッタ電流との積で表
される電圧の増分変で補償する方法がある。従来、この
抵抗体はNi/Cr等の金属を数百Åの厚さに蒸着して、形
成されていた。
2. Description of the Related Art One of the problems of bipolar transistors, particularly power bipolar transistors, is thermal runaway. The thermal runaway that occurs in a bipolar transistor results from the fact that the base-emitter barrier potential V BE decreases with increasing temperature, thereby increasing the collector current and further increasing the bipolar transistor temperature due to the increase in the collector current. Positive feedback destruction. This thermal runaway is particularly likely to occur in a large-area element for power. As a method of preventing thermal runaway, a resistor with a positive temperature coefficient of resistance is formed in the emitter region, and the decrease in V BE caused by temperature rise is
There is a method of compensating for the voltage by an incremental change expressed by the product of the increase in the resistance value of the resistor and the emitter current. Conventionally, this resistor has been formed by evaporating a metal such as Ni / Cr to a thickness of several hundreds of meters.

以下、図面を参照しながら従来のバイポーラトランジ
スタ構造について説明する。
Hereinafter, a conventional bipolar transistor structure will be described with reference to the drawings.

第2図は、従来のバイポーラトランジスタの斜視図で
ある。第2図において、1はコレクタ層、2はベース
層、3はエミッタ層であり、4はNi/Crの蒸着により形
成された抵抗体である。5はコレクタ電極、6はベース
電極、7はエミッタ電極である。
FIG. 2 is a perspective view of a conventional bipolar transistor. In FIG. 2, 1 is a collector layer, 2 is a base layer, 3 is an emitter layer, and 4 is a resistor formed by vapor deposition of Ni / Cr. 5 is a collector electrode, 6 is a base electrode, and 7 is an emitter electrode.

温度をTとするとVBE,Ni/Crバラスト抵抗の抵抗値re,
エミッタ電流Ieの間には という関係があり、 となるためには なる条件が必要である。
When the temperature is T, V BE , the resistance value of the Ni / Cr ballast resistor re,
Between the emitter current Ie There is a relationship, To become Conditions are required.

この関係により、あるエミッタ電流Ieに対し、適当な
抵抗値reを設定すれば、熱暴走を防止できることがわか
る。
From this relationship, it is understood that thermal runaway can be prevented by setting an appropriate resistance value re for a certain emitter current Ie.

発明が解決しようとする課題 しかしながら、上述のように金属薄膜からなる抵抗体
を有する構造では、膜厚が極めて薄いため、膜厚の制御
が困難であり、抵抗体の抵抗値の再現性が極めて悪いと
いう欠点を有していた。
However, in the structure having a resistor made of a metal thin film as described above, since the film thickness is extremely thin, it is difficult to control the film thickness, and the reproducibility of the resistance value of the resistor is extremely low. It had the disadvantage of being bad.

課題を解決するための手段 上記欠点に鑑み、本発明のバイポーラトランジスタ
は、ベース層を挟んでその両側にそれぞれコレクタ層と
エミッタ層が形成され、同エミッタ層の上に同エミッタ
層と同一の導電型で、前記エミッタ層よりも不純物濃度
が低く、かつ前記エミッタ層と組成の異なる抵抗体層が
形成され、同抵抗体層の上に同抵抗体層と同一の導電型
で、前記抵抗体層よりも不純物濃度が高いコンタクト層
が形成され、同コンタクト層の上にエミッタ電極が形成
されているものである。
Means for Solving the Problems In view of the above drawbacks, the bipolar transistor of the present invention has a collector layer and an emitter layer formed on both sides of a base layer, and has the same conductive layer as the emitter layer on the emitter layer. A resistor layer having a lower impurity concentration than that of the emitter layer and a composition different from that of the emitter layer, and having the same conductivity type as the resistor layer on the resistor layer; A contact layer having a higher impurity concentration is formed, and an emitter electrode is formed on the contact layer.

作用 この構成により、エミッタ層とエミッタ電極との間に
形成された半導体層の抵抗値の温度係数が正であるため
に、温度上昇に伴うVBEの低下を、温度変化に従って起
る半導体層の抵抗値の増加分と半導体層を流れる電流と
の積であらわされる電圧の増分で補償することができ、
バイポーラトランジスタの熱暴走を防止することとな
る。また、この半導体層は、エピタキシャル成長技術を
用いて、制御性良く形成することができ、さらに1回の
エピタキシャル成長で、再現性良くバイポーラトランジ
スタを製造することが可能となる。
Operation With this configuration, since the temperature coefficient of the resistance value of the semiconductor layer formed between the emitter layer and the emitter electrode is positive, the decrease in V BE due to the temperature rise causes It can be compensated for by the voltage increment represented by the product of the increase in the resistance value and the current flowing through the semiconductor layer,
This prevents thermal runaway of the bipolar transistor. Further, this semiconductor layer can be formed with good controllability by using an epitaxial growth technique, and a bipolar transistor can be manufactured with good reproducibility by one epitaxial growth.

実施例 以下、図面を参照しながら本発明の一実施例について
説明する。第1図は、本発明の一実施例におけるバイポ
ーラトランジスタの断面図である。
Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of a bipolar transistor according to one embodiment of the present invention.

第1図において、11はコレクタ層となる不純物濃度
が、1×1016/cm3,厚みが0.3μmのn型GaAs層、12はベ
ース層となる不純物濃度が1×1018/cm3,厚みが0.1μm
のP型GaAs層、13はエミッタ層となる不純物濃度が5×
1017/cm3,厚みが0.25μmのn型Al0.3Ga0.7As層、14は
抵抗体となる不純物濃度が1×1016/cm3,厚みが0.4μm
のn型GaAs層、15,16はいずれもオーミック電極をとる
ための高濃度n型GaAs層、17はコレクタ電極となるAuGe
/Au膜、18はベース電極となるTi/Pt/Au膜、19はエミッ
タ電極となるAuGe/Au膜、20はアンドープのGaAs基板で
ある。
In FIG. 1, reference numeral 11 denotes an n-type GaAs layer having an impurity concentration of 1 × 10 16 / cm 3 and a thickness of 0.3 μm as a collector layer, and reference numeral 12 denotes an impurity concentration of 1 × 10 18 / cm 3 as a base layer. 0.1 μm thick
P-type GaAs layer 13 has an emitter concentration of 5 ×
An n-type Al 0.3 Ga 0.7 As layer having a thickness of 10 17 / cm 3 and a thickness of 0.25 μm. An impurity concentration 14 serving as a resistor is 1 × 10 16 / cm 3 and a thickness of 0.4 μm.
N-type GaAs layer, 15 and 16 are high-concentration n-type GaAs layers for taking ohmic electrodes, and 17 is AuGe to be
A / Au film, 18 is a Ti / Pt / Au film serving as a base electrode, 19 is an AuGe / Au film serving as an emitter electrode, and 20 is an undoped GaAs substrate.

以下に、本発明の一実施例におけるバイポーラトラン
ジスタの製造方法について述べる。
Hereinafter, a method for manufacturing a bipolar transistor according to one embodiment of the present invention will be described.

上記の半導体層は、まず、アンドープのGaAs基板20上
にMBEを用いて高濃度を用いて高濃度GaAs層16,コレクタ
層11,ベース層12,エミッタ層13,抵抗体層14,高濃度GaAs
層15を連続的にエピ成長する。
The above-mentioned semiconductor layer is first formed on an undoped GaAs substrate 20 by using MBE to form a high concentration GaAs layer 16, a collector layer 11, a base layer 12, an emitter layer 13, a resistor layer 14, and a high concentration GaAs.
Layer 15 is continuously epitaxially grown.

次に、エミッタ領域をフォトレジストでカバーし、高
濃度GaAs層15および抵抗となるGaAs層14をCCl2H2/H2
ス用いたRIEにより選択的にエッチングし、次に、ヨー
ド形エッチング液を用いてAl0.3Ga0.7As層13を選択的に
エッチングし、ベース増12を露出させる。次に、エミッ
タ領域とベース領域をフォトレジストでカバーし高濃度
n型GaAs層を露出させるために、りん酸系エッチング液
でコレクタ層11をエッチングする。この後、エミッタ電
極19をコレクタ電極17として、厚さ0.05μmのAuGe膜と
厚さ0.25μmのAu膜からなるAuGe/Au膜をリフトオフ法
により形成し、450℃,5分間のアニールを行い、オーミ
ック接合をとる。
Next, the emitter region is covered with a photoresist, and the high-concentration GaAs layer 15 and the GaAs layer 14 serving as a resistor are selectively etched by RIE using CCl 2 H 2 / H 2 gas. Is used to selectively etch the Al 0.3 Ga 0.7 As layer 13 to expose the base 12. Next, the collector layer 11 is etched with a phosphoric acid-based etchant in order to cover the emitter region and the base region with a photoresist and expose the high concentration n-type GaAs layer. Thereafter, using the emitter electrode 19 as the collector electrode 17, an AuGe / Au film composed of a 0.05 μm thick AuGe film and a 0.25 μm thick Au film is formed by a lift-off method, and annealed at 450 ° C. for 5 minutes. Take ohmic junction.

次に、ベース電極18として、Ti膜,Pt膜,Au膜、それぞ
れの厚みが0.05μm,0.01μm,0.15μのTi/Pt/Au膜をリフ
トオフ法により形成し、300℃5分間のアニールを行な
いオーミック接合をとる。
Next, as a base electrode 18, a Ti film, a Pt film, and an Au film, Ti / Pt / Au films each having a thickness of 0.05 μm, 0.01 μm, and 0.15 μm are formed by a lift-off method, and annealed at 300 ° C. for 5 minutes. Perform ohmic junction.

次に、この一実施例バイポーラトランジスタにおける
作用を説明する。
Next, the operation of the bipolar transistor of this embodiment will be described.

本実施例で抵抗層14の単位面積当りの抵抗値は約8×
10-6−Ω1−cm2となる。本実施例のバイポーラトラン
ジスタでは、電流密度が約10-5A/cm2であるため、動作
時には、この抵抗体14による電圧降下には約0.8Vとな
る。GaAs層で形成された抵抗体の温度係数は約、13×10
-3/degであるため、この抵抗体による電圧降下の温度係
数は1.04mV/degとなる。一方、本実施例のベース・エミ
ッタ間、障壁電圧VBEの温度係数は約−1.0mV/degとなっ
ている。したがって、この抵抗による電圧降下の温度係
数とベース・エミッタ間障壁電圧VBEの温度係数は負号
が逆で、絶対値がほぼ等しいことから、温度変化に伴
う、コレクタ電流の増加によって起きる正帰還的な破壊
が防げることとなる。
In this embodiment, the resistance value per unit area of the resistance layer 14 is about 8 ×
10 −6 −Ω1-cm 2 . In the bipolar transistor according to the present embodiment, the current density is about 10 −5 A / cm 2 , so that the voltage drop due to the resistor 14 is about 0.8 V during operation. The temperature coefficient of the resistor formed of the GaAs layer is about 13 × 10
Since it is −3 / deg, the temperature coefficient of the voltage drop by this resistor is 1.04 mV / deg. On the other hand, the temperature coefficient of the barrier voltage V BE between the base and the emitter in this embodiment is about −1.0 mV / deg. Therefore, the temperature coefficient of the voltage drop due to this resistor and the temperature coefficient of the base-emitter barrier voltage V BE have opposite signs, and their absolute values are almost the same, so the positive feedback caused by the increase in collector current due to temperature change Damage can be prevented.

本実施例の効果を調べるために、本実施例のバイポー
ラトランジスタと抵抗層14なしのバイポーラトランジス
タについて、素子の破壊される最大コレクタ電流を測定
した結果、抵抗層14なしのバイポーラトランジスタはコ
レクタ電流500mA以下で破壊されたのに対して、本実施
例バイポーラトランジスタは、約2Aまで破壊されなかっ
た。
In order to investigate the effect of the present embodiment, as a result of measuring the maximum collector current at which the element is destroyed for the bipolar transistor of the present embodiment and the bipolar transistor without the resistive layer 14, the bipolar transistor without the resistive layer 14 has a collector current of 500 mA. The bipolar transistor of the present example was not destroyed up to about 2 A, while it was destroyed below.

発明の効果 以上のように、本発明はバイポーラトランジスタの熱
暴走を防ぐための抵抗を、半導体層により形成したもの
であり、その抵抗値の再現性は極めて高く、実用的効果
は大なるものがある。
As described above, in the present invention, the resistance for preventing thermal runaway of the bipolar transistor is formed by the semiconductor layer, and the reproducibility of the resistance value is extremely high, and the practical effect is large. is there.

【図面の簡単な説明】[Brief description of the drawings]

第1図は本発明の一実施例におけるバイポーラトランジ
スタの断面図、第2図は従来のバイポーラトランジスタ
の斜視図である。 1,11……コレクタ層、2,12……ベース層、3,13……エミ
ッタ層、4……Ni/Crバラスト抵抗、5,17コレクタ電
極、6,18……ベース電極、7,19……エミッタ電極、14…
…低濃度n型GaAs層、15,16……高濃度n型GaAs層。
FIG. 1 is a sectional view of a bipolar transistor according to an embodiment of the present invention, and FIG. 2 is a perspective view of a conventional bipolar transistor. 1,11 ... collector layer, 2,12 ... base layer, 3,13 ... emitter layer, 4 ... Ni / Cr ballast resistor, 5,17 collector electrode, 6,18 ... base electrode, 7,19 …… Emitter electrode, 14…
... Low-concentration n-type GaAs layer, 15, 16 ... High-concentration n-type GaAs layer.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】ベース層を挟んでその両側にそれぞれコレ
クタ層とエミッタ層が形成され、同エミッタ層の上に同
エミッタ層と同一の導電型で、前記エミッタ層よりも不
純物濃度が低く、かつ前記エミッタ層と組成の異なる抵
抗体層が形成され、同抵抗体層の上に同抵抗体層と同一
の導電型で、前記抵抗体層よりも不純物濃度が高いコン
タクト層が形成され、同コンタクト層の上にエミッタ電
極が形成されていることを特徴とするバイポーラトラン
ジスタ。
A collector layer and an emitter layer are formed on both sides of a base layer, respectively, and have the same conductivity type as the emitter layer on the emitter layer, have a lower impurity concentration than the emitter layer, and A resistor layer having a composition different from that of the emitter layer is formed. A contact layer having the same conductivity type as the resistor layer and a higher impurity concentration than the resistor layer is formed on the resistor layer. A bipolar transistor, wherein an emitter electrode is formed on a layer.
JP1182953A 1989-07-14 1989-07-14 Bipolar transistor Expired - Fee Related JP2662039B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1182953A JP2662039B2 (en) 1989-07-14 1989-07-14 Bipolar transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1182953A JP2662039B2 (en) 1989-07-14 1989-07-14 Bipolar transistor

Publications (2)

Publication Number Publication Date
JPH0346334A JPH0346334A (en) 1991-02-27
JP2662039B2 true JP2662039B2 (en) 1997-10-08

Family

ID=16127236

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1182953A Expired - Fee Related JP2662039B2 (en) 1989-07-14 1989-07-14 Bipolar transistor

Country Status (1)

Country Link
JP (1) JP2662039B2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2958213B2 (en) * 1993-06-08 1999-10-06 シャープ株式会社 Heterojunction bipolar transistor
JP2953966B2 (en) * 1994-10-14 1999-09-27 日本電気株式会社 Manufacturing method of bipolar transistor
JP4626893B2 (en) * 1996-08-16 2011-02-09 クリー、インコーポレイテッド Bipolar semiconductor device having a semiconductor layer composed of SiC and method of manufacturing a semiconductor device composed of SiC
JP2000260784A (en) 1999-03-12 2000-09-22 Sharp Corp Heterojunction bipolar transistor, semiconductor device using the same, and manufacture of the heterojunction bipolar transistor
US9171977B2 (en) * 2011-06-17 2015-10-27 Cree, Inc. Optically assist-triggered wide bandgap thyristors having positive temperature coefficients

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4871571A (en) * 1971-12-25 1973-09-27
JPS61123176A (en) * 1984-11-20 1986-06-11 Toshiba Corp Hetero-junction bipolar transistor
JPS6265368A (en) * 1985-09-17 1987-03-24 Toshiba Corp Hetero-junction bipolar transistor

Also Published As

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JPH0346334A (en) 1991-02-27

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