GB2051476A

GB2051476A - Field effect transistor devices

Info

Publication number: GB2051476A
Application number: GB8013051A
Authority: GB
Original assignee: Nippon Telegraph and Telephone Corp
Current assignee: Nippon Telegraph and Telephone Corp
Priority date: 1979-04-21
Filing date: 1980-04-21
Publication date: 1981-01-14
Also published as: NL188776C; NL8002257A; DE3015158A1; NL188776B; GB2051476B

Abstract

A field effect transistor device (10) is constituted by a semi-insulating substrate (11) consisting of a compound semiconductor, a semiconductor layer (12) formed on the substrate, a plurality of semiconductor gate regions (17a to 17d), of a conductivity type different from that of the layer (12), extending through the semiconductor layer (12) to reach the substrate (11), source and drain electrodes (13 and 14) disposed on the semiconductor layer (12) on opposite sides of the drain regions, and a gate electrode (17) connected to said gate regions but insulated from the surface of the semiconductor layer (12). Two gate regions (17a and 17d) at opposite ends of the array may be in contact with the boundary region of the transistor. <IMAGE>

Description

SPECIFICATION Field effect transistor devices and methods of manufacturing such devices This invention relates to a field effect transistor, more particularly a field effect transistor device in which function regions which constitute the field effect transistor are disposed in a compound semiconductor layer on a semiinsulating substrate made of a similar compound semiconductor and a method of manufacturing such transistor.

An ordinary field effect transistor now being used widely is constructed such that an N type semiconductor layer made of such compound semiconductor as GaAs is epitaxially grown on a semiinsulating substrate made of the similar compound semiconductor, that a source electrode and a drain electrode having a predetermined spacing are attached to the surface of the semiconductor layer with ohmic contacts and that a gate electrode in a Schottky junction with the semiconductor layer is disposed between the source and drain electrodes. Such a construction is disclosed in a Charles A. Liechti's paper entitled "Microwave Field-Effect Transistor~1976", I.E.E.E. Transaction on Microwave Theory and Techniques, Vol. MTT-24, No.6 pages 279-300, June, 1976.

In a transistor of this construction, a depletion layer extends into the semiconductor layer from the Schottky junction according to the magnitude of a control voltage impressed across the gate and source electrodes so that the cross-sectional area of a drain current path in the semiconductor layer is narrowed in accordance with the gate control voltage.

Moreover, the transistor constructed as above described involves the following problems.

Firstly, as the semiconductor layer is epitaxially grown on the semiinsulating substrate, in most cases, portions of the semiconductor layer near the substrate have crystal defects.

In addition, since these portions are formed at the initial stage of epitaxial growth, the impurity concentration is difficult to make uniform due to manufacturing technique. For this reason it is extremely difficult to make uniform the characteristics of the transistor at or near cutting off the drain current (gate pinch off) regardless of an accurate control of the thickness of the semiconductor layer as the subsequent process for manufacturing steps of the transistor. Thus, this problem is one of the factors that decreases the yield of satisfactory transistors. This is more particularly true in transistors assembled into an integrated circuit.For example, it is desired to ON/OFF control the drain current with relatively small gate control voltage of about i 1 volt, the thickness of the semiconductor layer becomes about 0.1-0.1 micron for 1 x 10'7~5 X 10'6cm~3 of N type impurity concentration in GaAs so that the problem caused by the construction described above results in a large dispersion in the gate pinch off voltage.

For this reason, it is difficult to assemble transistors into an integrated circuit for commercial use.

Furthermore, the transistor of this type is manufactured by the steps of forming a semiconductive layer of one conductivity type by implanting ions of an impurity into one surface of a semiinsulating substrate made of such compound as GaAs, forming source and drain electrodes in an ohmic contact with the surface of the substrate, and then forming a gate electrode to form a Schottky junction.

Transistors prepared by this method are disclosed in a B. M. Welch et al paper entitled "Gallium Arsenide Field-Effect Transistors by ion Implantation", Journal of Applied Physics, vol. 45, No. 8, pages 3685-3687, Aug.

1974 and a R.G. Hunsperger et al paper entitled "lon-lmplanted Microwave Field Effect Transistors in GaAs, Solid State Electronics, Vol. 18, pages 349-353.

With the transistor of the construction described above, for the purpose of recovering distorted crystal structure caused by the implanted ions which are implanted into the semiconductor substrate for forming the semiconductor layer and of electrically activating the implanted ions of an impurity it is necessary to subject the implanted substrate to an annealing treatment in which the substrate is heated to a high temperature of 800-900 C.

However, such annealing treatment encounters the following problem. Such residual impurities as chromium, silicon, etc. contained in the substrate at the time of preparing the semiinsulating semiconductor substrate tend to diffuse or unwanted external impurities might be incorporated, or impurities implanted into a predetermined portion at a predetermined concentration tend to diffuse.

In addition, when the surface of the semiinsulating semiconductor substrate is subjected to the high temperature described above, such surface of compound semiconductor as GaAs often decomposes. Due to various phenomena appearing at the time of annealing it is difficult to obtain at a high reproducability a semiconductor having a uniform thickness and containing an impurity at a uniform concentration. This also causes dispersion in the pinch off voltage of the resulting transistor thus decreasing the yield.

Accordingly, it is a principal object of this invention to provide a field effect transistor and a method of manufacturing the same at a high yield which is suitable to assemble an integrated circuit.

Another object of this invention is to provide a field effect transistor device and a method of manufacturing the same capable of reducing dispersion in the gate pinch off voltage.

Still another object of this invention is to provide an improved field effect transistor device suitable for use in a logic circuit consuming only a little electric power.

A field effect transistor device according to the invention comprises a semiinsulating layer made of a compound semiconductor; a compound semiconductor layer of a first conductivity type and formed on said semiinsulating layer; at least two spaced semiconductor gate regions having a second conductivity type different from said first conductivity type and extending to or near said semiinsulating layer from a main surface of said semiconductor layer; source and drain electrodes disposed on opposite sides of said semiconductor gate regions, said source and drain electrodes being in ohmic contact with said semiconductor layer; and gate electrode means in ohmic contact with said semiconductor gate regions and electrically insulated from regions of said semiconductor layer other than said gate regions, a periphery of a resulting transistor being in contact with at least two of said semiconductor gate regions.

A method according to the invention of manufacturing a field effect transistor comprises the steps of forming a semiinsulating layer made of a compound semiconductor and a compound semiconductor layer which is disposed on said semiinsulating layer; implanting ions of an impurity into the main surface of said compound semiconductor layer to form at least two semiconductor gate regions which extend from the main surface to substantially reach said semiinsulating layer and are disposed with a predetermined interval, said impurity being of a second conductivity type different from the first conductivity type; and sintering metallic layers on the semiconductor gate region in ohmic contact and on opposite sides of the semiconductor layers with said semiconductor gate regions being interposed therebetween to form a gate, a source and a drain electrodes; said second step further comprising a step of positioning at least two of said semiconductor gate regions such that said gate regions come in contact with the boundary region of the transistor to be constructed.

In the accompanying drawings: Figure 1 is a perspective view showing one embodiment of a field effect transistor device embodying the invention; Figure 2 is a cross-sectional view taken along a line ll-ll shown in Fig. 1; Figure 3 is a longitudinal sectional view taken along a line Ill-Ill shown in Fig. 1; Figure 3A is a detailed sectional view showing a manner of extending of a depletion layer shown in Fig. 3; Figures 4A through 4E show successive steps of one method of manufacturing the transistor shown in Fig. 1; Figures 5 through 10 show another embodiments of the field effect transistor device embodying the invention; Figures 1 1A through 1 1J show successive steps of another method of manufacturing transistor according to the invention; and Figures 12, 13A and 13B show modifications of the manufacturing method shown in Fig. 11.

A preferred embodiment of the field effect transistor 10 shown in Fig. 1 comprises a semiconductor substrate 11 made of such compounds as GaAs, or InP. The substrate 11 has a thickness of about 200-400 microns and a high specific resistivity of 106 or more ohm-centimeter. On the substrate 11 is formed an N type similar compound semiconductor layer 12, for example made of GaAs by epitaxial growth technique. The semiconductor layer 12 has an N type impurity concentration of 5 x 1016 atoms/cm3, for example, and a thickness of O. 1-1 micron.Layer 13 and 14 of such metals as gold-tin and gold-germanium are applied in parallel on the main surface of the semiconductor layer 12 with a suitable spacing, for example 5-10 ym, to form source and drain electrodes, and these metal layers are in an ohmic contact with the semiconductor layer 12.

A plurality of P type semiconductor gate regions 15a-15d are formed in the semiconductor layer 12 along a straight line at about the center between the metal layers 13 and 14 and extending in parallel therewith. These semiconductor gate regions 15a-15d are formed by implanting ions of Be, for example, into the semiconductor layer 12 and have a circular cross-sectional configuration and reach to the interface between the semiconductor layer 12 and the semiinsulating substrate 11 or extend beyond the interface into the substrate 11.Temperature of the annealing treatment after the above described Be implantation to recover the crystal structure damaged by the implantation and to electrically activate Be ions to P type impurities is ranged at extremely low, for example 550~600 C is available, comparing to the annealing temperature for N type impurity implantation. Therefore unwanted phenomena introduced during the high temperature annealing treatment after N type impurity implantation is annihilated in case of Be implantation for P type case. The portions of these gate regions exposed on the semiconductor layer 12 are connected by ohmic contact to a metal layer 17 made of gold-zinc and acting as a gate electrode. The metal layer 17 is covered by such insulating layer 18 as SiO2 and separated from the main surface of the semiconductor layer 12 except those portions 17a-17d in contact with the gate regions 1 5a-1 5d respectively. In the example shown, the insulating layer 18 covers the exposed surface of the semiconductor layer 12 and the metal layers 13 and 14.

In this embodiment, for the purpose of isolating various elements, a portion of the semiconductor layer 12 is etched in the form of a mesa to expose a portion of the semiinsulating substrate 11. In this case, the etched portion of the semiconductor layer 12 would come into contact with a semiconductor gate region, (in the example shown in Fig. 1, region 15a). For this reason, the metal layer 17 also makes ohmic contact with semiconductor gate region 15a at a side wall of the mesa.

This transistor operates as follows. When a predetermined bias source (not shown) is connected between the source electrode 13 and the drain electrode 14, drain current would flow through a path tracing through drain electrode 1 semiconductor layer 12~por- tions thereof between respective semiconductor gate regions-semiconductor layer 12~source electrode 13. Under these conditions, when a control voltage is impressed across the gate electrodes 17a-17d and the source electrode 13 such that the PN junctions formed between the semiconductor layer 12 and respective gate regions would be biased reversely, depletion layers 20a, 20b, 20c and 20d (shown by dotted lines in Figs.

2 and 3 would extend toward the semiconductor layer 12 from respective semiconductor gate regions 1 Sa- 1 Sd as shown by arrow in Figs. 2 and 3. As a consequence, in regions 1 2a-1 2c (See Fig. 3) of the semiconductor layer 12 through which the drain current flows between respective semiconductor gate regions 1 Sa- 1 Sd depletion layers extend from the semiconductor gate regions 15a and 15b, 15b and 15c, and 1 Sc and 1 Sd to adjacent respective regions 1 2a-1 2c thus decreasing the width of these regions according to the reversely applied gate voltage.Accordingly, the drain current flowing through these regions decreases gradually with the increase in the reversing biased gate control voltage, and is finally cut off.

The field effect transistor constructed as above described has the following advantages.

(1) Since a plurality of semiconductor gate regions are formed through a semiconductor layer consisting of a compound semiconductor formed on a semiinsulating semiconductor layer made of similar compound from the main surface of the semiconductor layer to the semiinsulating semiconductor it is possible to obtain field effect transistors of uniform quality at a high yield, which are suitable to fabricate integrated circuits. More particularly, the depletion layers extending from the semiconductor gate regions formed substantially at right angles to the semiconductor layer 12 are formed substantially in parallel with the direction of thickness of the semiconductor layer and extend toward the opposed semiconductor gate regions. For example, the state of the depletion layer will be described in more detail with reference to Fig. 3A.The depletion layer is more or less deformed at a portion of the semiconductor layer 12a close to the substrate due to crystal defects or nonuniform concentration of the impurity, and under a normal state the depletion layer extends longer than other portions because of the less concentration of N type impurities. For this reason, these portions 20a1 and 20b1 are connected together a little earlier than other portions. These portions are located near the substrate by a few hundred Angstroms which is much smaller than the thickness (1 micron, for example) of the semiconductor layer 12.

For this reason, regardless of a variation in the characteristics of these portions 20a1 and 20b1, the control of the drain current, that is the gate characteristic, is determined by the state of elongation of relatively uniform depletion layers at portions other than the portions 20a1 and 20b1. Thus, it is possible to obtain transistors having uniform characteristics. Furthermore, according to this invention, since the depletion layers extend in the opposite directions, even when the thickness of the semiconductor layer is reduced to several hundred Angstroms, for example, for the purpose of obtaining logic transistors of a low power consumption, the gate pinch off characteristics of the transistors are not affected by the crystal defects or nonuniform concentration of the impurity in the direction of thickness.

Thus, it is possible to obtain field effect transistors consuming less power than the prior art transistors.

(2) Furthermore, as it is possible to determine the width of the channel according to the space between the semiconductor gate regions the gate control characteristic of the transistor can be determined by the accuracy of a mask utilized to form the gate regions.

Moreover, as the thickness of the semiconductor layer is not predetermined for the purpose of determining the width of the channel as has been the prior art practice, it is possible to select any desired thickness for the semiconductor layer thus readily producing a field effect transistor of a desired current value.

(3) In addition, according to this invention, the semiconductor gate regions at both ends of an array of the gate regions are positioned at peripheries or boundary regions of the transistor region, so that it is possible to obtain a transistor that would not be influenced by the construction at the periphery of the transistor region.

(4) As above described since the semiconductor gate regions at both ends of the array thereof are positioned at the peripheries of the transistor region, it is possible to prevent the gate control characteristic from being affected by the side walls formed when the transistor is formed as a mesa type.

(5) In addition, by positioning the semiconductor gate regions at the peripheries of the transistor region, even when the accuracy of positioning a mask utilized to form the peripheries of the transistor may decrease more or less, it is possible to obtain at a high yield transistors having desired characteristics. This advantage can be enhanced by increasing the dimension of the semiconductor gate regions in contact with the periphery in the direction of alignment of the gate regions.

The field effect transistor having a construction described above can be prepared by the following method: At first a semiinsulating substrate 31 made of a compound semiconductor, GaAs, having a resistivity of more than 106 ohm-cm and a thickness of 300 microns is prepared. Then, a semiconductor layer 32 made of GaAs containing such N type impurity as Si, S or Se at a concentration of 5 X 1016 atoms/cm3 is epitaxially grown on one surface of the substrate 31 to a thickness of 1 micron. Unwanted portions of the semiconductor layer 32 are removed by a local etching process to form a semiconductor layer 32b having side walls 32a of a mesa construction. Then, a portion of the semiinsulating substrate 31 would be exposed as shown in Fig. 4A.

Then, ions of such P type impurity as Be are implanted by a well known ion implanting technique to form P type semiconductor gate regions 34a, 34b, 34c and 34d extending from the main surface of the semiconductor layer 32b to the semiinsulating substrate 31.

The region 34a is formed at the position of one periphery of a transistor to be formed. In this embodiment, the semiconductor gate regions 34b-34d have the form of cylinders whereas the gate region 34a takes the form of an ellipse having a major axis in the direction of alignment and a minor axis having the same length as the diameter of another gate regions 34b-34d. With this construction, at the periphery of the transistor region, as the semiconductor layer 32b has side walls 32a of mesa construction, the P type ions implanted to form the gate region 34a penetrate deeper into the substrate 31 than those utilized to form another gate regions 34b-34d.

However, as the substrate 31 does not contribute to the operating characteristics of the resulting transistor deep penetration of the implanted ions does not affect the characteristics. This state is shown in Fig. 4B.

Then metal layers 36a and 36b made of gold-germanium, for example, are formed by a a known method at portions at which the source and drain electrodes of a field effect transistors are to be formed. This state is shown in Fig. 4C. Alternatively, the metal layers 36a and 36b may be formed by vapordepositing metal on the entire exposed surface and then photo-etching the deposited metal layer so as to cause to remain only the portions therof acting as the source and drain electrodes. Thereafter, the remaining portions are sintered at a temperature of 450 C for 30 seconds to cause the gold-germanium to form alloys with GaAs to cause them to have ohmic contacts with the N type GaAs. In this manner, source and drain electrodes in ohmic contact with the semiconductor 32b can be obtained.

Then, an insulating film 38 such as a SiO2 < or Si3N4 film is formed on all surfaces of the exposed semiinsulating substate 31, the semiconductor layer 32b and the side walls 32a thereof to a thickness of 0.2 to 1 micron.

Then windows 38a-38d smaller than the gate regions 34a-34d are formed through the insulating film to expose the top portions of the gate regions as shown in Fig. 4D. In this example, a portion 38e of the insulating film 38 overlying the side wall 34a contiguous to the exposed gate region 34a and a portion 38f overlying the semiinsulating substrate 31 are also removed. Finally a metal layer Au-Zn, for example, is vapor-deposited on the portion of the insulating film at portions 38a-38f at which the insulating film 38 has been removed and on the portion of the insulating film between these portions 38a-38f to form a gate electrode 40. Alternatively, the gate electrode 40 may be formed by vapor-depositing a metal layer onto the entire surface subsequent to the step shown in Fig. 4D and then removing unwanted portions by photoetching technique to form a gate electrode as shown in Fig. 1.Thereafter, unnecessary insulating film 38 is removed. In this example, portions of the insulating film on the source and drain electrodes are removed, and this state is shown in Fig. 4E.

The field effect transistor device thus obtained has a construction as shown in Fig. 1.

It should be understood that the invention is not limited to a specific embodiment described above and that many changes and modifications can be made without departing the scope of the invention.

For example, although in the embodiment shown in Figs. 1 to 4, the surface of the field effect transistor device was covered by an insulating film, it is also possible to electrically insulate and isolate portions interconnecting respective semiconductor regions of the gate electrode from the semiconductor layer 32b without using the insulating film. Such construction can be obtained by substituting the step of forming the insulating film 38 shown in Fig. 4D with a step of forming a photoresist layer and after forming the gate electrode shown in Fig. 4E the photoresist layer is etched off. This state is shown in Fig. 5 in which elements corresponding to those shown in Fig. 1 are designated by the same refer ence characters.

Fig. 6 shows a modified field effect transis or device of this invention having an inverter function in which a bias feed connection electrode 50 is disposed in ohmic contact with the semiconductor layer 12 on the side opposite the source electrode 13 at a predetermined distance from the drain electrode 14 of the transistor shown in Fig. 1. This construction makes it possible to use the semiconductor region 12f between the drain electrode 14 and the bias feed connection electrode 50 as a load resistor of the transistor thus maintaining the output voltage derived from the drain electrode at a constant value.

More particularly, the output voltage Vout of the transistor can be expressed by an equation Vout =lxR where R represents the value of the load resistor, and I the drain current flowing through the load resistor. According to this invention, since the load resistor region is formed in the direction of the thickness of the semiconductor layer, the current I varies in proportion to the thickness of the semiconductor layer. In contrast, the load resistor is proportional to the length of the semiconductor layer and inversely proportional to the width and height thereof. In this case, the height of the load resistor corresponds to the thickness of the semiconductor layer.As a consequence, the output voltage Vout is proportional to the length of the semiconductor layer and inversely proportional to only the width, these values being determined by the accuracy of a mask utilized for manufacturing the transistor, and considered to be substantially constant. Thus, with this construction it is possible to maintain the output voltage at a constant value regardless of the thickness variation in the construction of the semiconductor layer.

As shown by dotted lines in Fig. 5, a high resistive P- or N- buffer layer 60 consisting of similar compound semiconductor may be interposed between the semiinsulating substrate 11 and the semiconductor layer 12.

Although in the foregoing embodiments, one gate electrode was interposed between the source and drain electrodes, a plurality of gate electrodes may be provided as shown in Figs. 7, 8 and 9.

Thus, a modified transistor device having an inverter function 70 shown in Fig. 7, comprises a seminsulating substrate 71 made of a compound, an N type semiconductor layer 72 made of a similar compound, source and drain electrodes 74 and 75 and two gate electrodes 76a and 76b disposed between the source and drain electrodes 74 and 75 formed on a main surface of the N type semiconductor layer 72. Similar to those shown in the foregoing embodiments, the gate electrodes are in ohmic contact with P type semiconductor gate regions 77a, 77b, 77c, 80a and 80b extending from the main surface to the substrate 71 in the direction of the thickness of the semiconductor layer 72.

The semiconductor gate regions 77b and 77c connected to a gate electrode 76b are in contact with the peripheries 78a and 78b of the transistor whereas the semiconductor gate region 77a connected to the gate electrode 76a is disposed to define a triangular area with the regions 77b and 77c between the semiconductor gate regions 77b and 77c and the drain electrode. The drain electrode 75 also acts as an output terminals for succeeding stages, and a bias feed connection electrode 79 spaced a definite distance from the drain electrode 75 is disposed in ohmic contact with the main surface of the semiconductor layer 72 so that a load transistor is formed between the drain electrode 75 and the bias feed connection electrode 79.In this case, the drain electrode is in ohmic contact with a pillar or column shaped P type semiconductor regions 80a and 80b formed in the semiconductor layer 72 between the drain electrode 75 and the bias feed connection electrode 79 so as to utilize the load transistor of the driver field effect transistor. As is well known in the art, the load of this type is utilized to solve problems involved in the manufacturing steps and a problem regarding the magnitude of the load impedance and the dimension of the load. In this embodiment the source electrode 74 is grounded.

With this construction, the transistor device as an inverter 70 can perform various logic operations by suitably selecting a channel spacing dAB between semiconductor gate regions 77a and 77b or 77c and the channel spacing dBB between regions 77b and 77c, and by combining inputs A and B applied to the gate electrodes 77a and 76b respectively.

Although in this modification, the semiconductor gate regions 77b and 77c are commonly in ohmic contact with one gate electrode 76b these gate regions may be made to have ohmic contacts with different gate electrodes. Then, the number of combinations of the logic operations can be increased.

Fig. 8 shows a modification of the transistor device shown in Fig. 7. The field effect transistor device 100 shown in Fig. 8 comprises two driver transistors 101 and 102 and a load transistor 103 which are arranged in the form of a letter Y. These elements are formed on an N type semiconductor layer 106 on a semiinsulating substrate 105 of a compound semiconductor. Transistors 101 and 102 have a common drain electrode 107.The driver transistor 101 is constituted by the electrode 107, a source electrode 108 disposed on a semiconductor layer 106 positioned as the outer end of one leg of the Y, pillar shaped semiconductor gate regions 11 0a and 11 Ob extending in the direction of the thickness of the semiconductor layer 106 between the drain and source electrodes 107 and 108, and gate electrodes 11 la, 11 lb and 11 lc in ohmic contact with these regions. In the same manner as in the previous embodiments, the gate semiconductor regions 11 Oa and 11 Ob extend from the main surface of the semiconductor layer 106 to or near the substrate 1 05.

The semiconductor gate regions 11 ova and 11 Ob are adjacent to the peripheries 112a and 11 2b of the transistor just like the previous embodiments.

The driver transistor 102 is constituted by a drain electrode 107, a source electrode 115 mounted on a semiconductor layer 106 at the outer end of the another leg of the Y, pillar shaped semiconductor gate regions 11 0b and 11 0c extending in the direction of thickness of the semiconductor layer 106 between the source and drain electrodes 115 and 107 and gate electrodes 11 ib and 11 lc in ohmic contact with these gate regions. Since in this modification, the semiconductor gate region 11 0b and the gate electrode 111 b in ohmic contact therewith are provided to bridge both driver transistor 101 and 102, the gate region 11 0b and the gate electrode 111 b are used in common for both transistors.Similar to the gate regions 11 Oa and 11 Ob, the gate region 11 or also extends from the main surface of the semiconductor layer 106 to or near the substrate 105. In the same manner as in the foregoing embodiments, the semiconductor gate regions 11 Ob and 110c are in contact with the peripheries 11 6a and 11 6b of the transistor 102.

A bias feed connection electrode 118 is disposed on the main surface of the semiconductor layer 106 in ohmic contact and at a definite distance from the common drain electrode 107. For this reason, a load transistor 103 is formed between the drain electrode 107 and the bias feed connection electrode 118. The drain electrode 107 is also in ohmic contact with pillar shaped P type semiconductor regions 119a and 119b formed in the semiconductor layer 106 between the drain electrode 107 and the bias feed connection electrode 118 to form a load field effect transistor. In this embodiment, the source electrodes 108 and 115 are grounded via resistors 120 and 121.

When the channel spacing dAC between the semiconductor gate regions 11 Oa and 11 Ob and the channel spacing dBC between the gate regions 11 0b and 110c are selected suitably, outputs of various logic operations can be derived out by suitable combinations of inputs A, B and C supplied to the gate electrodes 11 1a-1 1 c.

Fig. 9 illustrates still another modification of the field effect transistor device embodying the invention. A transistor device 130 shown therein is a modification of that shown in Fig.

7 7 and has a different layout of the gate electrode and the semiconductor gate region.

More particularly, P type semiconductor regions 131a-131d are formed between the drain electrode 75 and the source electrode 74, and gate electrodes 1 32a-1 32d are in ohmic contact with respective regions 1 31a-1 31d. Respective semiconductor gate regions 1 31 a and 1 31 b are in contact with the periphery 78a of the transistor device 1 30 whereas the gate regions 1 31 c and 1 31 d are in contact with the periphery 78b.With this construction too, by suitably selecting the channel spacing dAC between the semiconductor regions 131a and 131c and the channel spacing dBD between the semiconductor regions 131b and 131 d, and by suitably combining inputs A-D applied to electrode 132a-132d various logic operations can be performed by the transistor device.

The semiconductor gate regions that characterize the invention may take the forms of a rectangle, triangle, star, diamond or any other desired shape in addition to a circle and ellipse.

Although in the foregoing embodiment a mesa construction was used for the purpose of isolating electrically component elements, any other separating construction may be used. For example, Fig. 10 is a sectional view which clearly shows that semiconductor gate regions 141a and 141 c are positioned at the periphery of the transistor device. Actually, source and drain electrodes are disposed on the region 142 in ohmic contact on the opposite sides of the gate regions 141a-141c and in a plane perpendicular to the sheet of drawing.

The same construction can be obtained by implanting oxygen ions into a region of an N type semiconductor layer on a semiinsulating layer other than the transistor region so as to convert the N type semiconductor layer at that portion into an insulating region. In any case, two semiconductor gate regions of an array should be in contact both with the peripheries of element isolating and with the insulating region.

Although in the foregoing embodiment the semiinsulating layer is made of a compound semiconductor such as GaAs or InP, other compound semiconductors having a specific resistance of more than 106#.cm may be used. If the specific resistance is less than 106Sl.cm, a leakage current flowing within the compound semiconductor exerts an undesirable effect on the characteristic of the field effect transistor formed.

Figs. 11A through 1 1J illustrate another example of method for manufacturing the field effect transistor device according to the invention.

First, there is prepared a semiinsulating substrate 170 which is made of a compound semiconductor such as GaAs and has the resistivity more than 1062, cm and thickness of from 200 to 400 #m. Then, there is formed on the surface of said substrate 170, an N type semiconductor layer 171 which is made of a compound such as GaAs having the thickness of from 0. 1 to 1 ym. The semiconductor layer 171 may be, for instance, epitaxially grown. This state is shown in Fig. 11A.

An insulating protective layer 172 made of SiO2, Si3N4 etc., having the thickness of between 0.05 and 0.5 #m is formed on top of the N type semiconductor layer 171. The protective layer is formed by the conventional method such as CVD (chemical vapor deposition) or sputtering technique. A photoresist layer 173 is subsequently formed on the protective layer 172 in a thickness of between 0.5 and 3 ym. This state is illustrated in Fig.

11 B.

The photoresist layer 173 is then provided, in alignment, with a plurality of windows or holes 173a through 173e by photoetching technique. The holes in this case are shaped rectangular and are spaced at a regular interval with one another. This state is illustrated in Fig. 11 C.

Utilizing the photoresist layer 173 provided with the holes as a mask, ions of impurity such as Be are implanted from above in a direction indicated by the arrow A, under conditions of, for example, 100KeV and a dose of Be ions in an amount of 5 x 10'4Cm-2. Be ions thus implanted via the holes 173a through 173e of the photoresist layer 173 would penetrate the protective layer 172 as well as the semiconductor layer 171 and reach as far as the upper portion of the semiinsulating substrate 170 adjacent thereto, which results in Be ion implanted regions 174a through 174e formed at portions corresponding to said holes 173a and 173e. This state is shown in Fig. 11 D.

The portions of the protective layer 172 which are exposed in the holes 173a through 173e will then be removed by utilizing the photoresist layer 173 as a mask. This is carried out, for example, by employing the conventional sputtering or plasma etching technique. The photoresist layer 173 is then etched off with the use of, for example, resist remover and the like. This state is shown in Fig. 11 E.

It is then subjected to an annealing treatment at a low temperature of, for example, between 500 C and 600 C for 20 to 60 minutes. Since the annealing treatment for the electrical activation of P type impurity is conducted at a low temperature, there will hardly be any effects caused by the high temperature annealing for the N type impurity mentioned above. The ion implanted regions 174a through 174e are thus activated, thereby restoring crystals of the semiconductor from damage caused by the ion implanting and rendering the regions 174a through 174e to be the P type semiconductor gate regions 175a through 175e. As a result, a PN junction is formed between the P type semiconductor gate regions 175a through 175e and the remaining N type semiconductor regions 1 71 a within the semiconductor region 171.

This state is illustrated in Fig. 11 F.

A strip of metallic layer 177 having the thickness of between 0.1 and 1 lim is formed to connect the semiconductor gate regions 175a through 175e which are disposed in alignment, using the holes 172a through 172e of the protective layer 172 as a mask.

The metallic layer 177 is formed either by vapor desposition or sputtering technique, and is in ohmic contact with the semiconductor gate regions 175a through 175e to function as the gate electrode. In this case, the metallic layer 177 is formed, for example, by AuZn alloy. This state is shown in Fig. 11 G.

The protective layers 172 on both sides of the strip of metallic layer 177 are then removed by etching according to a predetermined pattern to form striped grooves 1 72g and 172h that are in parallel with said semiconductor gate regions 175a through 175e.

This state is shown in Fig. 11 H. Fig. 11 H shows the portion indicated by the line H-H of Fig. 11 G in cross section.

Conductive layers 178a and 178b in the form of a stripe are then formed to come in ohmic contact with the semiconductor layer 171 that is exposed in said grooves 172g and 172h. The conductor layers are made of AuGe alloy and function as the source and drain electrodes of the field effect transistor to be constructed. This state is shown in Fig.

111.

The configuration of the field effect transistor thus obtained is illustrated in Fig. 11J.

The field effect transistor thus obtained and shown in Fig. 11J had the saturation current ISD of 86 mA where the voltage applied to the gate electrode was zero, the mutual conductance was 20 mS which is expressed by the changes per 1 volt in ISD of the voltage VSD between the source and drain electrodes, and the pinch-off voltage was - 9V which renders the value of ISD zero.

Fig. 12 shows a modification of the method shown in Fig. 11. The sectional structure of Fig. 12 corresponds to the one shown in Fig.

11 C. As can be understood from the figure, the semiconductor layer 171 is exposed in the holes 173a through 173e formed in an alignment on the photoresist layer 173; this is because the photoresist layer 173 is formed directly on the semiconductor layer 171 without the previous protective layer 173. When ions are implanted in this state, the acceleration voltage at the time of ion implanting can be reduced as compared with the method in Fig. 11. It is further noted that the photoresist layer 173 will function to insulate and isolate spatially the N type semiconductor layers at the time of depositing the gate electrode and then be removed thereafter by etching to obtain a similar structure as shown in Fig. 5.

It is removed because the photoresist will not withstand a high temperature treatment.

Figs. 13A and 13B show still another modifications of the example shown in Fig. 11.

First, the process successive to that of Fig.

11 F is shown in Fig. 13A wherein the portion of P type semiconductor gate regions 175a through 175e near its surface are removed in a thickness of between 0.1 and 2 ym, for example, by etching using the protective layer 172 as a mask. In this case, the P type semiconductor gate regions 175a through 175e are somewhat expanded in the direction of the lower surface of the protective layer 172 extending from the edge of the hole of the protective layer 172 due to ion implanting and annealing processes subsequent to the process in Fig. 11 E. Therefore, the P type semiconductor gate regions will be shaped in the letter U in cross section by the etching treatment described above and the semiconductor layer 171 will not be exposed.The strip of metallic layer will then be disposed on the said semiconductor gate regions by a process similar to that shown in Fig 11 G to form a gate electrode 177 in ohmic contact with said regions and further subjected to the process shown in Fig. 11 H. The protective layers 172 located on opposite sides with the semiconductor gate regions 175a through 175e interposed therebetween are removed.

After the protective layers 172 are removed during the process of Fig. 11 H, the metalic layers 178a and 178b are disposed on the exposed portions of semiconductor 171, to form the source and gate electrodes in ohmic contact with the semiconductor layer 171.

The field effect transistor thus constructed is shown in Fig. 1 3B, which is a sectional view of the one in Fig. 13A along the line B-B. It is therefore possible to expose the portions of the semiconductor gate regions formed by the ion implanting technique where the P type impurity has the highest concentration, thereby enabling a lower ohmic contact of the regions with the gate electrodes 177 which is to be disposed thereon.

The method for manufacturing a field effect transistor illustrated in Fig. 11 can be modified in various other ways. For example, after or during the steps shown in Fig. 11 C, the protective layer can be removed according to the pattern of the windows of the resist, and further subjected to the implanting step of Fig. 11 D. It is also possible to have the concentration near the main surface of the semiconductor layer to be the highest by multiple implantation. In this way it will no longer be necessary to remove the surface of the P type semiconductor regions by etching as shown in Fig. 13.

Claims

1. A field effect transistor device comprising a semiinsulating layer made of a compound semiconductor; a compound semiconductor layer of a first conductivity type and formed on said semiinsulating layer; at least two spaced semiconductor gate regions having a second conductivity type different from said first conductivity type and extending to or near said semiinsulating layer from a main surface of said semiconductor layer; source and drain electrodes disposed on opposite sides of said semiconductor gate regions, said source and drain electrodes being in ohmic contact with said semiconductor layer; and gate electrode means in ohmic contact with said semiconductor gate regions and electrically insulated from regions of said semiconductor layer other than said gate regions, a periphery of a resulting transistor being in contact with at least two of said semiconductor gate regions.

2. The field effect transistor device according to claim 1 wherein a number of said semiconductor gate regions are aligned along a straight line, said source and drain electrodes extend in parallel with said straight line and two of said semiconductor gate regions at both ends of the alignment are in contact with a periphery of a resulting field effect transistor.

3. The field effect transistor device according to claim 1 or 2 wherein said gate electrode means comprises a single electrode commonly connected to said semiconductor gate regions.

4. The field effect transistor device according to claim 1 or 2 wherein said gate elec trode means comprises a plurality of gate electrodes respectively connected to said semiconductor gate regions.

5. The field effect transistor device according to claim 1 or 2 wherein said semiconductor gate regions in contact with the periphery of said field effect transistor are oblong in the direction of alignment of said gate regions.

6. The field effect transistor device according to claim 1 or 2 which further comprises a bias feed connection electrode extending in parallel with the direction of alignment of said semiconductor gate regions and mounted on said compound semiconductor layer on one side of said drain electrode opposite said source electrode, said bias feed connection electrode being spaced a definite distance from said drain electrode, whereby a region of said semiconductor layer between said bias feed connection electrode and said drain electrode is utilized as a load of said field effect transistor.

7. The field effect transistor device accord ing to claim 6 wherein said load is of a field effect transistor type.

8. The field effect transistor device according to claim 1 or 2 wherein said periphery of the transistor has a mesa construction.

9. The field effect transistor according to claim 1 or 2 wherein said periphery of said transistor is bounded by a semiinsulating semiconductor.

10. The field effect transistor device according to claim 1 which further comprises an insulator film mounted on said semiconductor layer, and said semiconductor gate regions are connected to said gate electrode means through openings provided for said insulator layer.

11. The field effect transistor device according to claim 1 or 2 which further comprises a buffer layer interposed between said semiinsulating layer and said semiconductor layer and having high resistivity as said semiconductor layer and a lower impurity concentration than said semiconductor layer.

12. A field effect transistor device comprising a semiinsulating layer made of a compound semiconductor; a compound semiconductor layer of a first conductivity type and formed on said semiinsulating layer; three semiconductor gate regions of a second conductivity type extending from the main surface of the semiconductor layer and substantially reaching said semiinsulating layer and being disposed in a triangle arrangement with a predetermined interval with one another, said semiconductor gate region being different from the semiconductor layer of the first type; source and drain electrodes disposed on opposite sides of said semiconductor gate regions, said source and drain electrodes being in ohmic contact with said semiconductor layer;; a first gate electrode in ohmic contact with said semiconductor gate region which is nearest to the drain electrode, said gate electrode being insulated from the other regions on semiconductor layers; a second gate electrode in ohmic contact with said semiconductor gate regions other than the one in contact with the first gate electrode, said second electrode being insulated from the other regions of semiconductor layers; the boundary region of the transistor thus constructed being in contact with two semiconductor gate regions on which the second gate electrode is mounted.

13. A field effect transistor device comprising a semiinsulating layer made of a compound semiconductor; a compound semiconductor layer of a first conductivity type which is positioned on the semiinsulating layer; three semiconductor gate regions of a second conductivity type extending from the main surface of the semiconductor layer and substantially reaching said semiinsulating layer and being positioned with a predetermined interval with one another, said second conductivity type being different from the first conductivity; a source electrode means and a drain electrode means disposed on opposite sides of the semiconductor gate regions and being in ohmic contact with said semiconductor layer; three independent gate electrodes in ohmic contact with respective semiconductor gate regions and being insulated from the region on the other semiconductor layers; said source electrode means being two source electrodes which are spaced, said drain electrode being one common drain electrode, and two of said semiconductor gate regions being in contact with the periphery regions of either one of the two transistors which are to be constructed while the each of remaining semiconductor regions is in contact with the periphery region of two transistors to be constructed.

14. A field effect transistor device comprising a semiinsulating layer made of a semiconductor; a a compound semiconductor layer of a first conductivity type disposed on said semiinsulating layer; four semiconductor gate regions of a second conductivity type extending from the main surface of the semiconductor layer and substantially reaching said semiinsulating layer and being disposed with a predetermined interval with one another, the second conductivity being different from the first conductivity type; source and drain electrodes disposed on opposite sides of the semiconductor gate regions and being in ohmic contact with said semiconductor layer; and four gate electrodes being so disposed as to be in ohmic contact with each of said semiconductor gate regions and insulated from the region of the other semiconductor layers; the periphery region of the transistor to be constructed being in contact with each of the four semiconductor gate regions.

15. The field effect transistor according to claim 12, 13 or 14 which further comprises a bias feed connection electrode with a predetermined distance spaced from said drain electrode, said bias feed connection electrode being in ohmic contact with the main surface of said semiconductor layer so as to form a load resistor between said drain electrode and said bias feed connection electrode.

16. The field effect transistor according to claim 15 which further comprises semiconductor regions of the opposite conductivity type and formed in said semiconductor layer between said drain electrode and said bias feed connection electrode, said drain electrode being in ohmic contact with said opposite conductivity type semiconductor regions thus rendering said load to constitute a field effect transistor.

17. The field effect transistor according to claim 16 wherein said drain electrode is used to derive out an output, said source electrode is grounded and inputs are applied to said semiconductor gate electrodes.

18. The field effect transistor device according to claim 16 wherein said drain electrode is used to derive out an output, said source electrodes are grounded respectively through resistors.

19. The field effect transistor according to claim 1, 12, 13 or 14 wherein said semiconductor layer is prepared by implanting ions of an impurity into said semiinsulating sustrate.

20. The field effect transistor device according to claim 1, 12, 13 or 14 wherein said semiconductor layer is epitaxially grown on said semiinsulating layer.

21. The field effect transistor device according to claim 1, 12, 13 or 14 wherein said semiinsulating layer consists of a compound semiconductor material having a specific resistivity of more than about 106 ohm-centimeter.

22. A method of manufacturing a field effect transistor comprising the steps of forming a semiinsulating layer, made of a compound semiconductor, and a compound semiconductor layer which is disposed on said semiinsulating layer; implanting ions of an impurity into the main surface of said compound semiconductor layer to form at least two semiconductor gate regions which extend from the main surface to substantially reach said semiinsulating layer and are disposed with a predetermined interval, said impurity being of a second conductivity type different from the first conductivity type; and sintering metallic layers on the semiconductor gate region in ohmic contact and on opposite sides of the semiconductor layers with said semiconductor gate regions being interposed therebetween to form a gate, a source and a drain electrodes; said second step further comprising a step of positioning at least two of said semiconductor gate regions such that said gate regions come in contact with the periphery region of the transistor to be constructed.

23. The method according to Claim 22 wherein the compound semiconductor layer of the first conductivity type is epitaxially grown on the semiinsulating substrate of a semiconductor.

24. The method according to Claim 22 wherein said first step includes the step of implanting ions of an impurity of the first conductivity type on the entire surface of the semiinsulating substrate made of a semiconductor, thereby forming a semiinsulating layer and a semiconductor layer disposed thereon.

25. The method according to Claims 22, 23 or 24, wherein said second step includes the steps of forming an insulating layer on said semiconductor layer; forming on said insulating layer a protective layer made of a material different from that of said insulating layer; forming windows on the protective layer at portions which correspond to the portion where the semiconductor gate regions of the protective layer are to be formed; implanting ions of an impurity of second conductivity type to form a region of the second conductivity type impurity extending from the main surface of the semiconductor layer which corresponds to the windows mentioned above and reaching the semiinsulating layer with the use of said protective layer as a mask; removing said protective layer; and forming said region of the second conductivity type impurity into a semiconductor gate regions by subjecting to a heat treatment.

26. The method according to Claims 22, 23, or 24 wherein the second step includes the steps of forming a protective layer on said semiconductor layer; forming windows at positions on the protective layer which correspond to where the semiconductor gate regions thereof are to be formed; implanting ions of an impurity of second type to form a region of the second conductivity impurity which extends from the main surface of the semiconductor layer corresponding to said windows and reaching the semiinsulating layer, with the use of the protective layer as a mask; forming the region of the second conductivity impurity into a semiconductor gate region; and said third step includes the step of removing the protective layer after each of the electrodes have been formed.

27. The method according to Claims 22, 23 or 24 wherein said second step includes; forming an insulating layer on said semiconductor layer; forming on said insulating layer a protective layer made of a material different from that of said insulating layer; forming windows on the protective layer at portions corresponding to where the semiconductor gate regions are to be formed; implanting ions of an impurity of second conductivity type, with the use of the protective layer as a mask, to form a region which extends from the main surface of the semiconductor layer corresponding to said window and reaching the semiinsulating layer; forming windows on said insulating layer with said protective layer being used as a mask; removing the semiconductor layer which is exposed to a predetermined depth; removing said protective layer; and forming said region of second conductivity into a semiconductor gate region by heat treatment.

28. A field effect transistor device substantially as described herein with reference to Figs. 1 to 3A or to any one of Figs. 5 to 10 of the accompanying drawings.

29. A method of manufacturing a field effect transistor device substantially as described herein with reference to Figs. 4A to 4E, to Figs. 11A to 1 1J, or to Figs. 11A to 11J with any one of Figs. 12, 13A and 13B of the accompanying drawings.