GB2256315A - Mos transistors - Google Patents

Mos transistors Download PDF

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Publication number
GB2256315A
GB2256315A GB9118511A GB9118511A GB2256315A GB 2256315 A GB2256315 A GB 2256315A GB 9118511 A GB9118511 A GB 9118511A GB 9118511 A GB9118511 A GB 9118511A GB 2256315 A GB2256315 A GB 2256315A
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semiconductor
layer
forming
insulating layer
substrate
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GB9118511D0 (en
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Byeong-Hyeok Rho
Chang-Kyu Hwang
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66651—Lateral single gate silicon transistors with a single crystalline channel formed on the silicon substrate after insulating device isolation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

STRUCTURE OF MOS TRANSISTOR AND FABRICATION THEREFOR The present invention relates to a semiconductor transistor, and particularly although not exclusively, to a structure of a MOS (Metal Oxide Semiconductor) transistor with an extended channel width, and a fabrication method therefor.
There have been many attempts to minimize the area occupied by each semiconductor device of a semiconductor integrated circuit as the level of integration of such circuits increases. Particularly, the size of each semiconductor transistor is an important factor in determining the size and other characteristics of a semiconductor chip, as is well known in the art. However, the reduction of size of each semiconductor transistor generally causes a reduction of the current driving capability thereof, thus resulting in a degradation of the operational characteristics of the semiconductor chip.
The reasons for this are illustrated by the following equation (1) indicating the driving current (ID) of a MOS transistor as,
where CO is the electrostatic capacity (dielectric constant) of a gate insulating layer, p is the mobility of carriers, L is the length of a channel, W is the width of the channel, VG is the gate voltage, Vm is the threshold voltage, and VD is the drain voltage.
As is apparent from Eq. (1), if the applied gate voltage and the applied drain voltage are constant, the driving current (ID) is proportional to W. Hence, in order L to increase the driving current (it), the channel width (W) needs to be increased relative to the channel length (L).
However, in a conventionally fabricated transistor, since the transistor device is formed in a region of a substantially planar semiconductor substrate, the area occupied by the transistor must be increased in order to increase the driving current (1D) As a result, there occurs a dilemma that the level of integration of a semiconductor integrated circuit should be low in order to obtain a sufficient transistor driving current, or the current driving capability should be sacrificed in order to achieve high integration of the circuit.
It is an object of the specific embodiments and specific methods of the present invention to provide a transistor of the metal-oxide-semiconductor type, having an increased driving current capability without increasing the area of chip occupied by the transistor, and to provide a fabrication process therefor.
According to a first aspect of the present invention, there is provided a semiconductor transistor comprising a substrate, a source region, a drain region and a channel region, said source and drain regions isolated from each other by the channel region, and said source, drain and channel regions being disposed in a device region of said substrate, said device region having a conductive layer disposed over said channel region and extending along a width of the channel region, said channel region having a plurality of protrusions arranged in parallel across said width.
According to a second aspect of the present invention, there is provided a semiconductor transistor comprising: a semiconductor substrate of a first-conductive type; an insulating layer, formed on a top surface of said substrate, and having a plurality of openings arranged in parallel in a direction of a channel width; a semiconductor layer filling said openings and having a thickness greater than that of said insulating layer; a conductive layer extended toward said direction over said semiconductor layer; and diffusion regions formed in said semiconductor layer in portions other than portions underneath said conductive layer.
Preferably, said semiconductor layer is a silicon epitaxial layer.
Preferably, the semiconductor transistor further comprises a plurality of second openings for contacting metal electrodes over selected portions of said diffusion regions.
Preferably, a channel region is formed in said semiconductor layer.
According to a third aspect of the present invention,there is provided a semiconductor transistor comprising: a semiconductor substrate of a first-conductive type; a plurality of second trenches arranged in parallel said trenches lying across a direction of a channel width in said substrate; an insulating layer formed over said substrate; an elongate conductive layer formed on said insulating layer and extending in said channel width direction; and a plurality of diffusion regions formed in portions of said semiconductor substrate other than in portions underneath said conductive layer.
Preferably, the semiconductor transistor further comprises a plurality of first trenches surrounding a region having said second trenches, said first trenches isolating the semiconductor transistor from other devices.
Preferably, a first depth of said first trench is greater than a second depth of said second trench.
According to a fourth aspect of the present invention, there is provided a method of manufacture of a semiconductor transistor said method comprising the steps of; isolating a device region on a semiconductor substrate; within said device region, forming a plurality of troughs and ridges substantially parallel to each other; forming a first insulating layer over said troughs and ridges; forming a gate extending over said troughs and ridges; and forming a drain region on one side of said gate, forming a source region on another side of said gate, said drain and source regions being separated from each other by a channel region formed under said gate.
According to a fifth aspect of the present invetion, there is provided a method for fabricating a semiconductor transistor, comprising the steps of: etching selected portions of a first insulating layer formed on an upper surface of a semiconductor substrate of a first-conductive type until a selected region of said semiconductor substrate is exposed to form a plurality of substantially parallel first openings arranged in a direction of a channel width; growing a silicon epitaxial layer having a thickness greater than that of said first insulating layer on the exposed surface of said semiconductor substrate; forming a second insulating layer on said silicon epitaxial layer; forming a first patterned conductive layer on said second insulating layer, so as to form a gate extended in said direction and disposed over said first openings; and implanting impurity ions of a second-conductivity type into the upper surface of said silicon epitaxial layer.
Preferably, the method further comprises the steps of: forming a third insulating layer over said substrate; etching selected portions of said third insulating layer over said ion implanted regions in order to form second openings; and forming a second conductive layer contacting with said second openings over said substrate, and thereafter patterning said second conductive layer.
Preferably, said first, second and third insulating layers are oxide layers.
Preferably, said second insulating layer is of an oxide layer provided by oxidizing said silicon epitaxial layer.
Preferably, an effective channel width of said semiconductor transistor is determined by controlling a thickness of said silicon epitaxial layer.
According to a sixth aspect of the present invention, there is provided a method of fabricating a semiconductor transistor comprising the steps of: forming a plurality of first trenches of a first depth surrounding a device region in a semiconductor substrate of a first-conductivity type, and thereafter filling interiors of said first trenches with insulating material; forming a plurality of second trenches of a second depth arranged in parallel across a direction of a channel width in said device region; forming a first insulating layer; forming a gate extending in said direction over said first and second trenches, by patterning a first conductive layer formed on said first insulating layer; and implanting impurity ions of a second-conductivity type into an upper surface of said substrate, to form drain and source regions.
Preferably, the method further comprises the steps of: forming a second insulating layer over said semiconductor substrate; etching selected portions of said second insulating layer so as to form a plurality of openings; and forming a second conductive layer contacting with said semiconductor substrate through said openings, and thereafter patterning said second conductive layer.
Preferably, said first and second insulating layers are oxide layers.
Preferably, said first conductive layer is of polycrystalline silicon.
Preferably, said first depth is substantially greater than said second depth.
The invention includes a semiconductor transistor or method of fabrication of the transistor, wherein a current driving capability of said semiconductor transistor is controlled by adjusting a shape and number of said second trenches.
The invention includes a transistor and a method of fabrication therefor, in which an insulating layer is formed on a semiconductor substrate of first-conductivity type. Then, selected portions of the insulating layer are etched until selected top portion of the substrate below the selected insulating portions are exposed. On the exposed portions of the substrate, silicon epitaxial layers are grown with a given thickness.
The invention also includes a transistor and method of fabrication therefor, in which there are formed first trenches in a substrate of first-conductivity type.
Between the first trenches, a plurality of second trenches are formed, each second trench having a depth less than that of each first trench. A plurality of protrusions and the trenches may be formed in selected portions of the substrate.
For a better understanding of the invention, and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying diagrammatic drawings, in which: Figure 1 shows a layout of the structure of a first MOS transistor according to a first specific embodiment of the present invention; Figure 2 is a cross sectional view taken along a line A-A' of Figure 1; Figure 3 is a cross sectional view taken along a line B-B' of Figure 1; Figure 4 illustrates a process for fabrication of the first transistor of Figure 1 according to a first specific method of the present invention; Figure 5 shows a layout of the structure of a second MOS transistor according to a second specific embodiment of the present invention; Figure 6 is a cross-sectional view taken along a line A-A' of Figure 5;; Figure 7 is a cross-sectional view taken along a line B-B' of Figure 5; Figure 8 illustrates a process for fabrication of the second transistor of Figure 5 according to a second specific method of the present invention; and Figure 9 illustrates a cross-sectional view of a conventional MOS transistor, and of first and second MOS transistors according to respective first and second specific embodiments of the present invention.
The first MOS transistor according to the first specific embodiment of the present invention will now be described with reference to Figures 1 to 3 of the accompanying drawings.
Firstly, the formation of four openings in a limited area of the transistor will be described.
Referring to Figure 1 of the accompanying drawings, there are shown a plurality of openings 4 arranged in parallel in a first direction, (i.e., the channel width direction) of a MOS transistor in a device region 6 of a semiconductor substrate. The device region is surrounded by a device isolating region 2. The openings 4 extend towards a second direction, (i.e., the channel length direction) of the MOS transistor, the second direction being perpendicular to the first direction. A gate 8 extends in the first direction. Metal lines 10 are arranged in parallel with the gate 8. A plurality of contact regions 12 are provided to electrically connect the metal lines 10 with the device region 6. Four of the contact regions 12 adjacent to each other are connected by one of the metal lines 10, so as to form one MOS transistor.
Referring to Figure 2 of the accompanying drawings, illustrating a cross section across the line A - A' in the first direction of the MOS transistor, a silicon epitaxial layer 16 is selectively grown on the semiconductor substrate 14 between oxide layers 15a, 15b. Over the silicon epitaxial layer 16 are successively formed a gate insulating layer 18, the gate 8, and an insulating interlayer 20. The silicon epitaxial layer 16 provides the device region 6 for the transistor. The oxide layer 15a at both ends of the device region 6 is a device isolating oxide layer forming the device isolating region 2, and the oxide layers 15b formed between the oxide layers 15a form a plurality of protrusions in the device region 6.
Referring to Figure 3 of the accompanying drawings, illustrating a cross section along the line B - B' in the second direction of the MOS transistor, there is shown the device isolating oxide layer 15a formed on the semiconductor substrate of the first-conductivity type, and the silicon epitaxial layer 16 formed therein. Source and drain regions 22 are isolated from each other by a channel region formed in the silicon epitaxial layer 16.
The gate 8 is formed over the channel region with the gate insulating layer 18 interposed therebetween. Each of the metal lines 10 contact with the source or drain, as appropriate, but are insulated from other parts of the transistor by the insulating interlayer 20.
A process for fabrication of the MOS transistor shown in Figures 1 to 3 of the accompanying drawings will now be described with reference to Figures 1 to 4 of the accompanying drawings.
Figures 4(A) to 4(D) of the accompanying drawings illustrate cross sectional views of the MOS transistor of Figures 1 to 3 taken in the first direction, i.e., the direction of the channel width, and Figures 4(A') to 4(D') of the accompanying drawings illustrate cross sectional views of the transistor in the second direction, i.e., in the direction of the channel length.
Referring to Figures 4(A) and 4(A'), of the accompanying drawings, there is formed a thick oxide layer 15 on the semiconductor substrate 14 of the first conductivity type. The thick oxide layer is etched so as to form a plurality of openings arranged in the first direction and extending in the second direction. Through the openings are exposed selected portions of the surface of the substrate 14. The oxide layer parts 15a formed on the substrate 14 are used to and are wide enough to isolate devices.
The silicon epitaxial layer 16 is selectively grown on the exposed portions of the surface of the substrate 14 as shown in Figures 4(B) and 4(B') of the accompanying drawings. The thickness of the epitaxial layer 16 should be made greater than the thickness of the oxide layer 15a, 15b and may be adjusted according to a desired value of driving current. The silicon epitaxial layer 16 is used as the device region of the transistor, and later, the source, drain and channel regions of the transistor are formed therein. The surface of the silicon epitaxial layer 16 is oxidized to form the gate insulating layer 18.
Then polycrystalline silicon is deposited over the whole surface of the substrate 14 as shown in Figures 4(C) and 4(C') of the accompanying drawings. The deposited polycrystalline silicon is subjected to photolithography and patterned so as to form the gate 8 extended in the first direction as shown in Figures 1 and 2 of the accompanying drawings. Impurity ions of the secondconductivity type are implanted into the polycrystalline silicon layer 16 so as to form the source and drain therein.
Over the whole surface of the substrate 14 is formed the insulating interlayer 20 of oxide as shown in Figures.
4(D) and 4(D') of the accompanying drawings. At this time, the impurity ions are diffused to form the source and drain 22 as shown in Figure 4(D'). Through openings formed by the etching of selected portions of the insulating interlayer 20 over the source and drain 22, the metal electrodes 10 are contacted with the source and drain 22 as appropriate, and as shown in Figure 3 of the accompanying drawings.
The second MOS transistor according to the second specific embodiment of the present invention will now be described with reference to Figures 5 to 7 of the accompanying drawings.
Referring to Figure 5 of the accompanying drawings, there are formed a plurality of protrusions including four trenches buried within an area for a transistor in a semiconductor substrate 34. Along four edges of a device region of the semiconductor substrate 34, is formed a trenched device isolating region 26. A gate 38, crossing over the device region surrounded by the device isolating region 26, is extended in a first direction, (ie, the direction of the channel width). Metal lines 30 extend in the first direction, over a region bordered by the device isolating region 26 and the gate 38. Contact regions 32 are provided to electrically connect the device region to the metal lines 30.
Referring to Figure 6 of the accompanying drawings, there is illustrated a cross section of the MOS transistor in the first direction, i.e., the direction of the channel width, along the line A - A' of Figure 5. To form the device isolating region 26 first trenches of a first depth are formed, being isolated from each other by a given distance therebetween. A plurality of second trenches 27 of a second depth are formed between the first trenches 26. The second depth is shallower than the first depth.
Over the surface of the substrate 34 having the protrusions including the trenches 27, are successively deposited a gate insulating layer 36, the gate 38, and an insulating interlayer 40. The first trenches 26 are used to isolate individual device regions of corresponding individual transistors from each other, and the second trenches 27 are to increase the surface area of the device region.
Referring to Figure 7 of the accompanying drawings, there is illustrated a cross section in the second direction, i.e., the direction of the channel length of the second MOS transistor, along the line B - B' of Figure 5. The source and drain regions 42 are isolated by a channel region in the semiconductor substrate 34. The gate 38 is formed over the channel region, with the gate insulating layer 36 being interposed therebetween. The metal electrodes 30 contact the source and drain 42 as shown, but are isolated from other parts of the transistor by the insulating interlayer 40.
A second process according to a second specific method of the present invention, for fabrication of the second MOS transistor will now be described with reference to Figure 8 of the accompanying drawings.
Figures 8(A), 8(B), 8(C) and 8(D) of the accompanying drawings show cross sectional views in the first direction, i.e., the direction of the channel width, and Figures 8(A'), 8(B'), 8(C') and 8(D') show cross sectional views in the second direction, i.e., the direction of the channel length.
Referring to Figures 8(A) and 8(A') of the accompanying drawings, the first trenches 26 of the device isolating region are formed with the first depth in the semiconductor substrate 34 of the first-conductivity type, to isolate the device region. First trenches having a larger depth than the depth of the second trenches formed in the device regions are utilized for the insulating between transistor devices.
Referring to Figures 8(B) and 8(B') of the accompanying drawings, the first trenches 26 are filled with insulating material. Then in the device region surrounded by the first trenches 26, a plurality of the second trenches 27 having the second depth, and arranged parallel and extended in the second direction, are formed.
The second depth of each of the second trenches 27 is shallower than the first depth of the first trenches 26.
Over the whole surface of the substrate 34 are sequentially deposited the gate insulating layer 36 of oxide and a polycrystalline silicon layer, as shown in Figures 8(C) and 8(C') of the accompanying drawings. The polycrystalline silicon layer is patterned as shown in Figure 5, and is subjected to photolithography so as to form the gate 38 extending in the first direction.
Impurity ions of the second-conductivity type are implanted into the upper portion of the substrate 34 for forming the source and drain regions 42.
The insulating interlayer 40 is formed over the whole surface of the substrate 34, as shown in Figures 8(D) and 8(D') of the accompanying drawings. During this time, the implanted impurity ions are diffused, thus forming the source and drain 42. Then selected portions of the insulating interlayer 40 over the source and drain regions 42 are etched to form the openings. Thereby, the metal electrode 10 is contacted with the source and drain 42 as shown in Figures 5 to 7 of the accompanying drawings.
Although in the present embodiment each second trench 27 has a trapezoidal shaped cross section, it will be easily appreciated by those skilled in this art that the cross section of the second trenches may have other shapes, provided that the second depth thereof is shallower than the first depth of the first trenches.
In the first specific embodiment illustrated in Figures 1 to 4 of the accompanying drawings, a first MOS transistor is made to have four openings by contacting the contact regions to the metal electrodes. In still another embodiment of the present invention, a number of transistors is determined by dividing the metal electrodes connected to the contact regions into several portions, or connecting a number of contact regions other than four, to each other.
Referring to Figure 9 of the accompanying drawings, the first and second MOS transistors according to the respective first and second specific embodiments of the present invention will now be compared with a conventional MOS transistor.
In Figure 9A of the accompanying drawings there is illustrated a cross section of a conventional MOS transistor in the direction of the channel width of the conventional MOS transistor. There is shown a semiconductor substrate 44 having field oxide layers 46 grown by a known LOCOS (local oxidation of silicon) method. An interval between the field oxide layers 46 is the channel width Wl. Since the surface of the substrate is flat in the direction of the channel width in the conventional MOS transistor, the practically effective channel width corresponds simply to the physical channel width W1 of the layout shown in Figure 9A of the accompanying drawings.
Figure 9(B) of the accompaning drawings illustrates a cross section in the direction of the channel width of the first MOS transistor according to the first specific embodiment of Figures 1 to 4. There is selectively grown the silicon epitaxial layer 16 on the semiconductor substrate 14 of the first-conductivity type. In this case, the undulated surface of the silicon epitaxial layer 16 is used as the channel width. Thus the practically effective channel width W2 of the first MOS transistor is expressed by Eq. (2) as; W2 = 4a + 8c o (2) and where
and where the distances a, b and c and angle 61 are as illustrated in Figure 9B of the accompanying drawings.
On the other hand, the physical channel width W1 of the first specific embodiment is expressed by Eq. (3).
Wl = 4a + 4b (3) The difference aW between the effective channel width W2, and the physical channel width W1 of the first specific embodiment, as expressed in Eqs. (2) and (3) respectively, is expressed by Eq. (4) as;
In Eq. (4), the value
is always greater than zero, and therefore the amount of the driving current may be determined by adjusting the angle ~l.
Figure 9(C) of the accompanying drawings illustrates the cross section in the direction of the channel width of the second MOS transistor according to the second specific embodiment of Figures 5 to 8. A plurality of the trenches 27 are formed in the device region of the semiconductor substrate 34 of the first-conductivity type. The physical channel width of the second specific embodiment between the device isolating layers 15a is expressed as W1, and may be the same as for a conventional MOS transistor.
However, the practically effective channel width W3 of the second embodiment is expressed by Eq. (5) as; W3 = 8d + 8e (5) where distances d, e, f and g, and angle 82 are as described in Figure 9C. On the other hand, the physical channel width W1 of the layout of the second MOS transistor is expressed by Eq. (6) as; W1 = 8d + 8f (6) The difference AW between the effective channel width and the physical channel width of the second specific embodiment given respectively by Eqs. (5) and (6), is expressed by Eq. (7) as;
Hence, the amount of the driving current in the second specific embodiment may be determined by adjusting the angle 62 between the horizontal surface and the slanting surface of the trench.
Alternatively, if the cross section of the trench 27 is made rectangular, W3 = Wl + 8g, and therefore AW = 8g.
As described above, the present invention may provide a MOS transistor having a considerably increased effective channel width compared with a conventional MOS transistor having a same physical channel width, by forming protrusions in the direction of the channel width in the substrate. A desired amount of the driving current may be obtained by controlling the shape and number of the protrusions.
While the invention has been particularly shown and described with reference to the preferred specific embodiments and methods thereof, it will be apparent to those who are skilled in the art that in the foregoing changes in form and detail may be made without departing from the spirit and scope of the present invention.
The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification in connection with this application and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.
All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps anre mutually exclusive.
Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.
The invention is not restricted to the details of the foregoing embodiment(s). The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.

Claims (22)

1. A semiconductor transistor comprising a substrate, a source region, a drain region and a channel region, said source and drain regions isolated from each other by the channel region, and said source, drain and channel regions being disposed in a device region of said substrate, said device region having a conductive layer disposed over said channel region and extending along a width of the channel region, said channel region having a plurality of protrusions arranged in parallel across said width.
2. A semiconductor transistor comprising: a semiconductor substrate of a first-conductive type; an insulating layer, formed on a top surface of said substrate, and having a plurality of openings arranged in parallel in a direction of a channel width; a semiconductor layer filling said openings and having a thickness greater than that of said insulating layer; a conductive layer extended toward said direction over said semiconductor layer; and diffusion regions formed in said semiconductor layer in portions other than portions underneath said conductive layer.
3. A semiconductor transistor as claimed in Claim 2, wherein said semiconductor layer is a silicon epitaxial layer.
4. A semiconductor transistor as claimed in Claim 2 or 3, further comprising a plurality of second openings for contacting metal electrodes over selected portions of said diffusion regions.
5. A semiconductor transistor according to Claim 2, 3 or 4, in which a channel region is formed in said semiconductor layer.
6. A semiconductor transistor comprising: a semiconductor substrate of a first-conductive type; a plurality of second trenches arranged in parallel said trenches lying across a direction of a channel width in said substrate; an insulating layer formed over said substrate; an elongate conductive layer formed on said insulating layer and extending in said channel width direction; and a plurality of diffusion regions formed in portions of said semiconductor substrate other than in portions underneath said conductive layer.
7. A semiconductor transistor as claimed in Claim 6, further comprising a plurality of first trenches surrounding a region having said second trenches, said first trenches isolating the semiconductor transistor from other devices.
8. The semiconductor transistor as claimed in Claim 6 or 7, in which a first depth of said first trench is greater than a second depth of said second trench.
9. A method of fabrication of a semiconductor transistor said method comprising the steps of; isolating a device region on a semiconductor substrate; within said device region, forming a plurality of troughs and ridges substantially parallel to each other; forming a first insulating layer over said troughs and ridges; forming a gate extending over said troughs and ridges; and forming a drain region on one side of said gate, forming a source region on another side of said gate, said drain and source regions being separated from each other by a channel region formed under said gate.
10. A method for fabrication of a semiconductor transistor, comprising the steps of: etching selected portions of a first insulating layer formed on an upper surface of a semiconductor substrate of a first-conductive type until a selected region of said semiconductor substrate is exposed to form a plurality of substantially parallel first openings arranged in a direction of a channel width; growing a silicon epitaxial layer having a thickness greater than that of said first insulating layer on the exposed surface of said semiconductor substrate; forming a second insulating layer on said silicon epitaxial layer; forming a first patterned conductive layer on said second insulating layer, so as to form a gate extended in said direction and disposed over said first openings; and implanting impurity ions of a second-conductivity type into the upper surface of said silicon epitaxial layer.
11. A method as claimed in Claim 10, further comprising the steps of: forming a third insulating layer over said substrate; etching selected portions of said third insulating layer over said ion implanted regions in order to form second openings; and forming a second conductive layer contacting with said second openings over said substrate, and thereafter patterning said second conductive layer.
12. A method as claimed in Claim 10 or 11, wherein said first, second and third insulating layers are oxide layers.
13. A method as claimed in Claim 10, 11 or 12, wherein said second insulating layer is of an oxide layer provided by oxidizing said silicon epitaxial layer.
14. A method as claimed in any one of claims 10 to 13, wherein an effective channel width of said semiconductor transistor is determined by controlling a thickness of said silicon epitaxial layer.
15. A method for fabricating a semiconductor transistor comprising the steps of: forming a plurality of first trenches of a first depth surrounding a device region in a semiconductor substrate of a first-conductivity type, and thereafter filling interiors of said first trenches with insulating material; forming a plurality of second trenches of a second depth arranged in parallel across a direction of a channel width in said device region; forming a first insulating layer; forming a gate extending in said direction over said first and second trenches, by patterning a first conductive layer formed on said first insulating layer; and implanting impurity ions of a second-conductivity type into an upper surface of said substrate, to form drain and source regions.
16. A method as claimed in Claim 15, further comprising the steps of: forming a second insulating layer over said semiconductor substrate; etching selected portions of said second insulating layer so as to form a plurality of openings; and forming a second conductive layer contacting with said semiconductor substrate through said openings, and thereafter patterning said second conductive layer.
17. A method as claimed in Claim 15 or 16, wherein said first and second insulating layers are oxide layers.
18. A method as claimed in Claim 15, 16 or 17 wherein said first conductive layer is of polycrystalline silicon.
19. A method as claimed in any one of Claims 15 to 18, wherein said first depth is substantially greater than said second depth.
20. A method as claimed in any one of claims 15 to 19, wherein a current driving capability of said semiconductor transistor is controlled by adjusting a shape and number of said second trenches.
21. An MOS transistor or method of manufacture, substantially as hereinbefore described with reference to Figures 1 to 4 and Figure 9B of the accompanying drawings.
22. An MOS transistor or method of manufacture substantially as hereinbefore described with reference to Figures 5 to 8 and Figure 9C of the accompanying drawings.
GB9118511A 1991-05-31 1991-08-29 Mos transistors Withdrawn GB2256315A (en)

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KR1019910009066A KR920022546A (en) 1991-05-31 1991-05-31 Structure of MOS transistor and its manufacturing method

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CN104952785A (en) * 2014-03-31 2015-09-30 中芯国际集成电路制造(上海)有限公司 Semiconductor device and manufacturing method thereof

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DE4127795A1 (en) 1992-12-03
ITRM910646A1 (en) 1993-03-01
KR920022546A (en) 1992-12-19
ITRM910646A0 (en) 1991-08-29
JPH04368180A (en) 1992-12-21
GB9118511D0 (en) 1991-10-16
IT1250089B (en) 1995-03-30

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