JPS586179A - Manufacture of field effect transistor - Google Patents
Manufacture of field effect transistorInfo
- Publication number
- JPS586179A JPS586179A JP10396081A JP10396081A JPS586179A JP S586179 A JPS586179 A JP S586179A JP 10396081 A JP10396081 A JP 10396081A JP 10396081 A JP10396081 A JP 10396081A JP S586179 A JPS586179 A JP S586179A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- opening
- gate
- field effect
- effect transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 238000005530 etching Methods 0.000 claims abstract description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 18
- 239000002184 metal Substances 0.000 claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000005468 ion implantation Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims 1
- 229910000077 silane Inorganic materials 0.000 claims 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 5
- 230000004888 barrier function Effects 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910018885 Pt—Au Inorganic materials 0.000 abstract 1
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 51
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- KOWWOODYPWDWOJ-LVBPXUMQSA-N elatine Chemical compound C([C@]12CN(C3[C@@]45OCO[C@]44[C@H]6[C@@H](OC)[C@@H]([C@H](C4)OC)C[C@H]6[C@@]3([C@@H]1[C@@H]5OC)[C@@H](OC)CC2)CC)OC(=O)C1=CC=CC=C1N1C(=O)CC(C)C1=O KOWWOODYPWDWOJ-LVBPXUMQSA-N 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 235000003642 hunger Nutrition 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 210000000554 iris Anatomy 0.000 description 1
- 210000003127 knee Anatomy 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000037351 starvation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はシーツトキーパリアゲート瀝電界効果トランジ
スタの製造方法に関し、１ＩＩＩＲ−ゲート電極とソー
スおよびドレイン電極間の距離を制御性がよく、セルフ
ァライン方式て形成する電界効果トランジスタの製造方
法に関する０
８愚に比べＳ〜６倍と大きな電子移動度を有するＧａＡ
ｓ牛導体は、その高速性に大きな特徴があり最近、超高
速集積回路（ＩＣ）に応用する研究−尭が活発に行われ
ている。このＧａｐｍ ＩＣの能動素子としては、基
本的に１１１Ｋ［Ｈｔよび第２図に示すようなシ■ット
キーバリャゲート瀧電界効果トランジスタ（Ｍｌｇ Ｆ
ｌ”ｒ ’）が提案されている０ξれは、プレーナ構造
と呼ばれ、半絶縁性ＧａＡｓ基１［１上にエピタキシャ
ル成長やイオン注入によ轢厚喜約０２μ簡の１形動作層
２を形成した後、ホトレジスト膜によるリフトオフ法な
どによりシーットキーゲート電極３を形成し、マスクの
位置合せを行ないＰＩＵＩＩ）にリフトオフ法などによ
りソース詔よびドレインのオーミック電極４．５を形成
した比較的簡単な構造のものである・
しかしこの様なプレーナ構造では、オーミック電極を形
成するために目合せが必Ｊｊｌて、１台せ精度は最喪の
機器に愈いても±ａ、Ｓ声鵬ぐらいてあり、ゲートの電
極間隔を１０層１ｍ以下にすることは実際上は難かしい
。また、この様なプレーナ構造では、ＧａＡｓ動作層の
表頁で結晶性の乱れや気体の１着などにより第２図に示
すように表面に空乏層６が生じ実効的な動作層が狭くな
る。その結果、ゲートとソース間の動作層の抵抗弁（ソ
ース直列抵抗）が増大し、相互コンダクタンスｆｒｍが
著しく低下する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a sheet keeper gate field effect transistor, and relates to a method for manufacturing a sheet keeper gate field effect transistor, in which the distance between the gate electrode and the source and drain electrodes can be easily controlled, and the field effect transistor is formed using a self-line method. GaA has an electron mobility that is ~6 times larger than that of 08G.
BACKGROUND ART Semiconductor conductors are characterized by their high speed, and recently, research has been actively conducted to apply them to ultra-high-speed integrated circuits (ICs). The active elements of this Gapm IC are basically 111K [Ht] and a Schottky barrier gate field effect transistor (MlgF) as shown in Fig.
The proposed structure is called a planar structure, in which a type 1 active layer 2 with a thickness of about 02 μm is formed on a semi-insulating GaAs base 1 by epitaxial growth or ion implantation. After that, a sheet key gate electrode 3 is formed by a lift-off method using a photoresist film, the mask is aligned, and the source and drain ohmic electrodes 4.5 are formed by a lift-off method (PIUII) to form a relatively simple structure. However, in such a planar structure, alignment is required to form an ohmic electrode, and the accuracy of a single device is about ±a, S, even if it is the worst equipment. In practice, it is difficult to reduce the gate electrode spacing to 1 m or less in 10 layers.In addition, in such a planar structure, the surface of the GaAs active layer may have problems such as crystallinity disturbance and gas adhesion, as shown in Figure 2. As shown, a depletion layer 6 is formed on the surface, and the effective active layer becomes narrow.As a result, the resistance valve (source series resistance) of the active layer between the gate and the source increases, and the mutual conductance frm decreases significantly.
ζこて、目合せの問題を避けてソース直列抵抗を小さく
するために、第Ｓ閣に示すようにオーミック電極下にイ
オン注入やエピタキシャル成長によりキャリア＃Ｉｆを
高（したｔ層重を形成して接触抵抗を下げようとするｔ
層構造が提案されているが、この構造でも表面空乏層の
影譬を減らすこと繻【１１副−一南一烏鳴論ｔ４ｃ向上
で釦−■そζで表面空乏層によるソース直列抵抗を小さ
くでき、しかも目合せＳ度ｆＩＩ春はど必要としない第
４図のようなリセス構造が提案専れている０これは、ゲ
ート電極の近傍だけを纏込んて所定の厚さの動作層（リ
セス部＄）にして、伽の部分は厚くすることにより、電
極間抵抗を小さくしたものである０
このリセス構造により電気約特性が大きく改善され、高
性能なＭｌｇ Ｆｌ’ｌ’を得ることができるようにな
ったｏしかし、このリセス構造において、リセス量の１
ＩＩＩＦな調整が難しく、ウーーノ１面内でのばらつ会
も大会い０
また、Ｉ合せによらずセルファライン方式により電極を
形成しようという試みも従来から提案されている。これ
は第Ｈａのようにゲート電極９を１字−または合のｃＩ
ｌにして、この傘を利用してソース・ドレインのオーミ
ック電＠４、Ｓを形成しようというものであるｏＴ″＃
皺のゲート電極を員遼する方法には、ＡＩと他の金属を
積層しムＩをサイドエツチングするものや、めっきによ
り電極を盛上げるものなどがあるが、ムＩの号イドエツ
チングは制御性や再現性に問題があり、めっきによる盛
上げも肩の横幅を再現性棗く制御することは困難である
。ζ In order to avoid alignment problems and reduce the source series resistance, a T layer with a high carrier #If is formed under the ohmic electrode by ion implantation or epitaxial growth, as shown in the S section. Trying to lower contact resistance
A layered structure has been proposed, but even with this structure, it is important to reduce the influence of the surface depletion layer. The recessed structure shown in Fig. 4, which does not require any alignment S degree fII spring, has been proposed. The recessed structure greatly improves the electrical characteristics, making it possible to obtain high-performance MlgFl'l'. However, in this recess structure, the recess amount is 1
IIIF adjustment is difficult, and variations within one Uno surface are also common.In addition, attempts to form electrodes using the self-line method without relying on I alignment have been proposed in the past. This is the case where the gate electrode 9 is set to 1- or cI as in No. Ha.
l, and use this umbrella to form a source/drain ohmic conductor @4,
There are methods to make wrinkled gate electrodes, such as layering AI and other metals and side-etching the layer, and raising the electrode by plating. There are also problems with reproducibility, and it is difficult to control the width of the shoulder with good reproducibility even with plating.
本発明の目的は、これらの聞題点を堆り除いた新しい電
界効果トランジスタの製造方法を提供することにある０
本発明によれば、半導体基板表面上に、菖１層、９２層
および第３層を鋏順序に積層し、次いでゲート形成部分
が開口したホトレジスト膜を被着し、エツチングにより
前記第１層に前記ホトレジスト膜の開口幅と同じ開口を
設けた後、前記ｌｓ３層に前記第１Ｍの開口よ吟＾い−
ｐを設け、前記ホトレジスト膜を除去した後、金１ｉｆ
：ゲート金属を被着して断面が〒・字型のゲート電＠管
形成し、前記篇１層−第２層および第３層を除去した後
、前記ゲート電極を傘にしてソース禽よびドレインのオ
ーｔ ｖり電極を形成することを特徴とする電界効果ト
ランジスタの製造方法が得られる。An object of the present invention is to provide a new method for manufacturing a field effect transistor that eliminates these problems. The three layers are laminated in a scissors order, and then a photoresist film with an opening in the gate formation portion is deposited, and an opening having the same width as the opening width of the photoresist film is provided in the first layer by etching. Check out the 1M opening.
After removing the photoresist film, gold 1if
: A gate metal is deposited to form a gate tube with a square cross section, and after removing the first layer, second layer and third layer, the source and drain are formed using the gate electrode as an umbrella. There is obtained a method for manufacturing a field effect transistor characterized by forming an automatic electrode.
以下、実施例をｌｉ！ｉＷＪを用いて説明する。Examples are shown below. This will be explained using iWJ.
縞藝図は、本発明の詳細な説明するための図である。The striped map is a diagram for explaining the present invention in detail.
嬉６図Ｃｍｌのように牛縁性ＧａＡ畠基板上に不純物Ｉ
１１度約ＩＱ ａｍ、厚さ約０．２μｍのｎ形動作層
をエビメキシャル成長法あるいはイオン注入法盛ζより
形成したＧｌム−ウ龜−ハ１０の上に、スパッター蒸着
機’？、１１１層１１としｒＡｊを約０．３５ｍ５ １
１１２層Ｕとして８ｉｓＮｎを約ＣＬ’ｉｆｉｍ％ｆｌ
Ｅ３層１３として８１０雪を＃０．３μｍ該順序に被着
する。 さらにゲート形成部分１５が約０．７声１ｍ開
口したホトレジスト膜１４を被着形成する◎
次に、ｊｌｓｉｇｌ（ｂ）のように異方性エツチング例
えば平行平ａｍのスパッタエツチング装置を用いてｅｒ
ａガスＥより、ＪＩ１層８ｊＯｇ１３、第２層８ｉｓＮ
４４をエツチングし、ガスをＣＣ１ａＫ、切換えて第１
層ム１１１をエツチングする０このとき、横方向にはほ
とんどエツチングされないため、ホトレジスト層１４の
パターンとほとんど同一のパターンが第１層１１に形成
される口
次に第６ｍ１ｌ（ｃ）のように等方性エツチングである
例えば円筒部プラズマエツチング装置を用いて、ＣＦ４
ガスで第３層８ｉ０ｘ１３ｔｉｉよび菖２層８ｉｓＮｎ
認をサイドエツチングして一口を広げる。ここてム４は
ＣＦ４’ガスではほとんどエツチングされず、８ｉｉ４
は８１０意よりも約１０倍の速さでエツチングされ、第
２層８ｉｓＮ４がｊも広＜ １１０８ ｔＬ ２５ ｏ
１１１７１１ ｉｃ ｍｅＷ化あけるＢｉＯ２のサイ
ドエツチング量とエーング時閲との関係を示す０この図
より、サイドエツチング量のばらつきは小さく、再現性
がよいＣきが分かる０こζては、第３層８１Ｑ、口を約
０．１７１ｍサイドエツチングする〇
次に第６図（ｄ）のようにホトレジスト膜１４を除去す
ると、第１層１１より第３層ｎが広く第２層ルがより広
いような開口群が形成専れている０次に、第６Ｅ−）の
ように全面１（ＴＩ−Ｐｔ−ムＵなどのゲート金属を約
ａ５μｔａｇ着すれば、８轟０ｓ１３の開口部を通して
Ｔ字部、のゲート電ｌ１ｌＩが形成される・次に、第６
図（０のようにゲート開口部および近傍をホトレジスト
膜１７で覆怠い、第＠＠−のようにスパッタエツチング
により余分なゲート金属、嬉３層１３および第２層１２
を除去し、餓１層１１の人ｊを露出させる。そしてホト
レジスト膜１７を除去し６０℃のリン酸中で第１層のＡ
ｊを除去すると、−口したホトレジスト膜を被着形成し
、ＡａＧｅを約（１１μｍ１着すれば、Ｔ字型のゲート
電極が傘になり、ソースおよびドレイン電極がゲート電
Ｉｉ９に対して自己整合的に形成され、ホトレジスト膜
誌をリフトオフすれば、電界効果、トランジスタの基本
構造第６図（ｊ）が出来上る。As shown in Figure 6, Cml, impurity I is deposited on the fertile GaA Hatake substrate.
An n-type active layer of about 11 degrees IQ am and about 0.2 μm thick was formed using a sputter deposition machine on top of the Gl layer 10, which had been formed by the epimexical growth method or the ion implantation method. , 111 layers 11 and rAj is approximately 0.35 m5 1
8isNn as 112 layer U about CL'ifim%fl
As the E3 layer 13, #0.3 μm of 810 snow is deposited in this order. Furthermore, a photoresist film 14 having an opening of approximately 0.7 mm and a gate forming portion 15 is deposited.Next, as shown in JLSIGL(b), anisotropic etching is performed, for example, using a parallel plane am sputter etching device.
From a gas E, JI1 layer 8jOg13, second layer 8isN
44, switch the gas to CC1aK, and
Etching the layer 111 At this time, since there is almost no etching in the lateral direction, a pattern almost identical to the pattern of the photoresist layer 14 is formed on the first layer 11. Using a directional etching, for example, a cylindrical plasma etching device, CF4
3rd layer 8i0x13tii and irises 2nd layer 8isNn with gas
Side-etch the recognition to widen the bite. Here, element 4 is hardly etched by CF4' gas, and 8ii4
is etched about 10 times faster than 810, and the second layer 8isN4 is also wider than 1108tL 25o.
111711 ic This figure shows the relationship between the side etching amount of BiO2 and the etching time after conversion to meW. From this figure, it can be seen that the variation in the side etching amount is small and C etching has good reproducibility. , the opening is side-etched by about 0.171m. Next, as shown in FIG. 6(d), the photoresist film 14 is removed, and an opening is formed in which the third layer n is wider than the first layer 11 and the second layer n is wider. If the gate metal such as TI-Pt-muU is deposited on the entire surface 1 (approximately a5μtag) as in No. 6E-) where the group is exclusively formed, then the T-shaped part, through the opening of 0s13 Gate voltage l1lI is formed.Next, the sixth
(As shown in Figure 0, the gate opening and its vicinity are not covered with a photoresist film 17, and as shown in Figure 2, sputter etching is performed to remove excess gate metal, the third layer 13, and the second layer 12.
Remove and expose person j of starvation 1 layer 11. Then, the photoresist film 17 is removed and the first layer A is heated in phosphoric acid at 60°C.
After removing j, a diagonal photoresist film is deposited and AaGe is deposited with a thickness of approximately (11 μm), and the T-shaped gate electrode becomes an umbrella, and the source and drain electrodes are self-aligned with respect to the gate electrode Ii9. By lifting off the photoresist film, the basic structure of a field effect transistor shown in FIG. 6(j) is completed.
ここで、Ｍｔ層はゲート金属とＧａＡｓを侵さずに選択
的に除去できることが必要であるｏＡノはリン酸で容易
にエツチングで合一しかもＧａＡｓあるいはＴ Ｉ／Ｐ
ｔ／ Ａｓ＋８らには通常用いられているゲート金属
、例えば、Ｍｏ５ＷＳＴ１等はリン酸でほとんど侵され
ないので１１１層として適しているＯ
第２層および第３層の物質は、エツチング速度が第２層
のほうが速いものてあればよい。８ｉ０ｘと８ｉ１Ｎ４
は、物質としても安定であり他にも多（利用専れて素子
に悪影響を与えないのて適している〇
また等方性エツチングは、筐体によるウーνトエッチン
グても可能であるが、エツチング反応が結合強度の弱い
結晶界面を通して進むため、端面ががさついて制御性も
悪い。それ鰐反し、畳方性ドライエツチングでは、端面
は平たんで制御性のよいエツチングを得ることがてきる
。Ｉ１１図化示したようにサイドエツチング量のばらつ
会は約（１１ｊ１１１１であり、目合せ精度の±ａ、ｓ
ｓｍＥ較べれば非常に精度がよいξとが分かる。つまり
、この第３層のサイドエツチング量よりＴ字部ゲート電
極の肩幅が一義的に決まり、また、この肩幅によりソー
ス＄よびドレインの電極間隔が一義的に決まるため８ｃ
形状精度のよい電極を得ることがて會ることが分かる。Here, it is necessary that the Mt layer can be selectively removed without damaging the gate metal and GaAs.
Gate metals commonly used for t/As+8 et al., such as Mo5WST1, are hardly attacked by phosphoric acid, so they are suitable for the 111 layer. It would be better if there was something faster. 8i0x and 8i1N4
is stable as a material and is suitable for many other uses as it does not adversely affect the device if used exclusively.In addition, isotropic etching is also possible by weight etching using the casing. Because the etching reaction proceeds through crystal interfaces with weak bonding strength, the edge surfaces are rough and the controllability is poor.On the other hand, with fold-oriented dry etching, the edge surfaces are flat and etching can be obtained with good controllability. As shown in Figure I11, the variation in side etching amount is approximately (11j1111), and the alignment accuracy ±a, s
If we compare smE, we can see that ξ is very accurate. In other words, the shoulder width of the T-shaped gate electrode is uniquely determined by the amount of side etching of the third layer, and since this shoulder width uniquely determines the spacing between the source and drain electrodes, 8c
It can be seen that this is achieved by obtaining electrodes with good shape accuracy.
・
ゲート金属を蒸着する方向は第＠Ｒ（ｅ）に示したよう
に垂直でもよいが、第８図−）に示すように蒸着する方
向を傾むけて斜め蒸着をして、！字置ゲ−）ｔｌｉを非
対称形にし、後のニーは岡しように余分な層を除去して
オーミマり電極を形成すれば第＄図如に示すよう化オフ
セットゲートにすることがで会る◎これによりドレイン
耐圧の向上およびソース抵抗の低減を國ることかで台、
高性能な）ａｌｌ ＦＩＴを得ることかで會る０前記実
施例においてソースおよびドレインのオー１ツタ電極の
形成にはムｕＧａを蒸着するものを示したが、イオン注
入により一層を形成しその上にオーミ！り電極を形成す
ればソース抵抗をさらに効果的に減らすことができる。- The direction in which the gate metal is deposited may be vertical as shown in Section @R(e), but it can be deposited obliquely by tilting the direction in which it is deposited, as shown in Figure 8-). If you make tli asymmetrical and form an ohm-margin electrode by removing the extra layer on the later knee, you can make an offset gate as shown in Figure ◎ This improves drain breakdown voltage and reduces source resistance.
In the above embodiments, muGa was deposited to form the source and drain electrodes, but a single layer was formed by ion implantation and then Ohmi! The source resistance can be further effectively reduced by forming a secondary electrode.
第９図はこの例を示したものであり、イオン注入秦件と
しては、例えば注入イオン８ｅ＋、 ドース量５ｘｉ
ｏ”ｍａｒ”１．ｉｇ速電ＪＥ１０６１ｃｅＶ ｔｌ
ｌ適轟テあるＯ
以上詳しく説明したごと（本発明化よればプレーナー構
造て電極間隔を訣くしｓ表面空乏層の影響を小さくして
、リセス構造に近い高性能のＭＩＳＦＩＴを得ることが
可能となり、しかも従来のりセス構造において必要とさ
れた制御性、再現性に欠ける掘込み部分の鳳形動作層厚
専の調整ニーが不要となり、４１性の揃った素子を再現
性よ（生寓することが可能となった０FIG. 9 shows this example, and the ion implantation conditions include, for example, implanted ions of 8e+ and a dose of 5xi.
o”mar”1. ig speed train JE1061ceV tl
As explained in detail above (according to the present invention, it is possible to obtain a high-performance MISFIT similar to a recessed structure by narrowing the electrode spacing and reducing the influence of the surface depletion layer). In addition, there is no need to adjust the thickness of the tung-shaped movement layer in the excavated portion, which lacks the controllability and reproducibility required in the conventional glue structure, and allows elements with uniform properties to be reproducibly obtained. 0 became possible
第ｉｌｌは、従来の最も基本的なプレーナ構造のシ１ッ
トキーゲートー電昇効果トランジスタ（ＭｉｓＦＮ’！
’ ）の断面図であり、第３園は、このプレーナ構造Ｍ
１８ ＦＩＴのＧａＡｓ輪作層の１＆ＮＥ表両空乏層
が発生している状態を示しである・第５Ｉｉｌは一層が
あるプレーナー構造ΦＭｍｌｌ ＦＩＴ の図、第４
１１はリセス構造のＭＩＳＦＩＴの図である。
そして、第１ＩＩはテ字臘ゲート電極でセルファライン
方式によるプレーナ構造の■８ＦＭテ である。
第４Ｉｔ（−〜０）は、本発−の製造方法を説明するた
めのｇ″１？あるＯ
ｓｙｍは、円筒型プラズマエシチング装置で高周波出力
３０Ｗにおけるホトレジストマスク下のｓｔｏｗ層の工
！チング時間とサイドエツチング量の関係を示す０第８
図Ｃａ）、（６）は斜め蒸着によるオフセフトゲ−）
ＩＩ ＭＢＩ！Ｉ ＦＩＴの製造方法を説明する閣であ
る０
籐會図は本発明の製造方法により形成専れたテ字部ゲー
ト電極をマスクに０層を廖虞したプレーナ構造Ｍ１８
ＦＩＴｔＴ である０＠Ｅおいて
ｌは半絶縁＠ＧａλＳ基板、 ２はＧａＡｍ動作層、３
はゲー１１、４はソース電極、 ５はトイイン電極、
６は表面空乏層、 フは一層、８はリセス部、 ９はＴ
字部ゲート電極、１ＧはＧａムＳ基板、 １１は＃ｉ４
１層（ムｊ）、 ｔｔはＳ雪層（８ｉｓＮ４）、 １３
は第３層（１１１０ｍ）、１４はホトレジスト膜、 謁
はゲート開口、１６は第１層のゲート開口、１７、比は
ホトレジスト膜を示す０第 １ 図
稟 ３１！Ｉ第６図
（ｂ） （＃）（Ｃ）
（ｈン（ε） （ｊ
）第 ７ 図
エラチン１時間Ｃ分】
第８５！１
（ｂ）
鳥９１￥１The illumination is the conventional most basic planar structure Sheetkey gate-voltage effect transistor (MisFN'!
), and the third garden is a cross-sectional view of this planar structure M
18 The 1&NE surface of the GaAs rotation layer of FIT shows the state in which both depletion layers are generated. 5th Iil is a planar structure with one layer ΦMmll FIT, 4th
11 is a diagram of a MISFIT having a recessed structure. The 1st II is an 8FM TE with a planar structure using a self-line method with a T-shaped gate electrode. 4th It(-~0) is g"1?Osym for explaining the manufacturing method of the present invention. The stow layer under the photoresist mask is etched at a high frequency output of 30 W using a cylindrical plasma etching device. No. 8 showing the relationship between time and side etching amount.
Figures Ca) and (6) are off-theft games by oblique deposition)
IIMBI! The figure below shows the planar structure M18 in which the zero layer is removed using the T-shaped gate electrode as a mask, which is formed by the manufacturing method of the present invention.
In 0@E which is FITtT, l is semi-insulating @GaλS substrate, 2 is GaAm active layer, 3
is the gate 11, 4 is the source electrode, 5 is the toy-in electrode,
6 is a surface depletion layer, F is a single layer, 8 is a recessed portion, 9 is a T
Gate electrode, 1G is GaM S substrate, 11 is #i4
1 layer (muj), tt is S snow layer (8isN4), 13
is the third layer (1110 m), 14 is the photoresist film, audience is the gate opening, 16 is the gate opening of the first layer, 17, ratio is the photoresist film, 0.
Rin 31! IFigure 6 (b) (#) (C)
(hn(ε) (j
) Figure 7 Elatin 1 hour C minute] No. 85!1 (b) Bird 91 yen 1
Claims (1)
層を該１序に積層し、次いてゲート形成部分が開口した
ホトレジスト膜を被着し、工１チングにより前記館１層
に前記ホトレジスト膜の一ロ―と同じ開口を設けた後、
前記第３層に前記第１層の開口より広い開口を設けると
ともに前１！ＩＩＩ冨層に前記第３層よりも広い開口を
１ム前記ホトレジスト膜を除去した後、全ＩＩｋゲート
金属を被着して断両がテ字瀝のゲージ電極を廖虞しｔ前
記のｉｌ１層、ｔｌｔｚ層および第３層を除膏した後、
前記ゲート電極を傘にしてソースおよびドレインのオー
ｔ ｖり電極を形成することを特徴とする電界効果ト
ランジスタの製造方法＠ １ ゲート形成部分が開口したホトレジスト膜を被着し
た後、異方性ドライエツチング法により前記半導体基板
表両が露出する重て前記第１層、菖２層自よび第３層に
開口を設け、勢方性ドライエツチング＄により前ＩＩＩ
！層自よ０第３層をサイドエツチングして開口をムげる
特許請求の範−嬉１項記噴の電界効果シランジスタの１
１′Ｒ１方法。 龜 ゲート嚢属を斜め１着によ＃）＊威する特許請求の
範囲第１項記載の電界効果トランジスタの製造方法０ ４、Ｔ字型ゲート電極を形成した後、オーミνり金属と
してＡ ｗ Ｇ ｅを被着することｋよりソースおよび
ドレインのオーミマク電極を形成する特許請求の範囲第
１項記載の電界効果トランジスタの製造方法・ 賑 テネ腫ゲート電極を形成した後、前記ゲート電極を
傘にして、イオン注入によりノーを形威しオーミック電
極を形成する特許請求の範■第１項記載の電界効果トラ
ンジスタの製造方法◎[Claims] 1. Semiconductor substrate 1
After stacking the layers in the first order, then depositing a photoresist film with an opening in the gate forming part, and forming an opening in the first layer in the same manner as the first row of the photoresist film by etching,
The third layer is provided with an opening wider than the opening in the first layer, and the front 1! After removing the photoresist film and forming an opening wider than the third layer in the III layer, the entire IIk gate metal is deposited and a gauge electrode with a T-shape cut is formed in the IL1 layer. , after removing the tltz layer and the third layer,
A method for manufacturing a field effect transistor, characterized in that overlapping source and drain electrodes are formed using the gate electrode as an umbrella. Openings are formed in the first layer, the second layer, and the third layer so that both surfaces of the semiconductor substrate are exposed by an etching method.
! A field effect silane resistor according to claim 1, in which the third layer is side-etched to eliminate the opening.
1'R1 method. 4. After forming the T-shaped gate electrode, A w is formed as an ohmic metal. A method for manufacturing a field effect transistor according to claim 1, which forms source and drain ohmic electrodes by depositing Ge. The method for manufacturing a field effect transistor according to claim 1, wherein an ohmic electrode is formed by forming an ohmic electrode by ion implantation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10396081A JPS586179A (en) | 1981-07-03 | 1981-07-03 | Manufacture of field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10396081A JPS586179A (en) | 1981-07-03 | 1981-07-03 | Manufacture of field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS586179A true JPS586179A (en) | 1983-01-13 |
Family
ID=14367952
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10396081A Pending JPS586179A (en) | 1981-07-03 | 1981-07-03 | Manufacture of field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS586179A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60167381A (en) * | 1984-02-09 | 1985-08-30 | Matsushita Electronics Corp | Manufacture of semiconductor device |
| JPH03185739A (en) * | 1989-12-01 | 1991-08-13 | Hughes Aircraft Co | Self-aligning t gate hemt |
| US5252843A (en) * | 1989-09-01 | 1993-10-12 | Fujitsu Limited | Semiconductor device having overlapping conductor layers |
-
1981
- 1981-07-03 JP JP10396081A patent/JPS586179A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60167381A (en) * | 1984-02-09 | 1985-08-30 | Matsushita Electronics Corp | Manufacture of semiconductor device |
| US5252843A (en) * | 1989-09-01 | 1993-10-12 | Fujitsu Limited | Semiconductor device having overlapping conductor layers |
| JPH03185739A (en) * | 1989-12-01 | 1991-08-13 | Hughes Aircraft Co | Self-aligning t gate hemt |
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