JPH05283619A - Formation of resistor element - Google Patents

Abstract

PURPOSE:To reduce fluctuation in the resistance value by forming a polycrystalline silicon layer of a linear pattern while oxidizing a side part of the polycrystalline silicon layer. CONSTITUTION:The polycrystalline silicon layers 4a, 4b having a slightly wider pattern that a prescribed linear pattern are formed. The side parts 13, 14 of the polycrystalline silicon layers 4a, 4b are selectively oxidized from the horizontal direction so as to be changed into an insulating material for generating the polycrystalline silicon layers 15, 16 having a prescribed linear pattern of a resistance element. The final width of the polycrystalline silicon layers 15, 16, which are resistor elements, is controlled basing on the parameter having the extremely good controllability such as oxidation from the horizontal direction of the side part so as to be very correct. Accordingly, fluctuation of the resistance value can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a resistance element which is a component of a semiconductor integrated circuit, for example.

[0002]

2. Description of the Related Art There are various types of resistance elements. As a resistance element which is a constituent element of a semiconductor integrated circuit such as SRAM, a resistance element which is composed of a polycrystalline silicon layer having a linear pattern is used. ing. This resistance element is conventionally formed as follows.

First, as shown in FIG. 7, a silicon substrate 5
A polycrystalline silicon film 53 is deposited on the thick silicon oxide film (field oxide film) 52 formed on the surface of No. 1 by a CVD method, and then impurities such as phosphorus are introduced by an ion implantation method for resistance adjustment. (Dope) Following the formation of the impurity-doped polycrystalline silicon film 52, as shown in FIG. 8, a photoresist mask 54 for patterning is used.
Is formed on the polycrystalline silicon film, and the unmasked portion of the polycrystalline silicon film is removed by dry etching to form a linear pattern polycrystalline silicon layer 53a doped with impurities. Next, as shown in FIG. 9, after removing the photoresist mask 54, an interlayer insulating oxide film 55 is deposited by the CVD method.

Then, a photoresist mask (not shown) for forming a contact hole is formed on the interlayer insulating oxide film 55, and the interlayer insulating oxide film is formed by dry etching as shown in FIG. A part of 55 is removed to open contact holes 61 and 62, and this hole 6
Ion implantation with a high dose amount is performed to obtain ohmic contact from Nos. 1 and 62. Then, after performing an annealing treatment for activating the implanted ions, an aluminum film is deposited by a sputtering method, a photoresist mask (not shown) is formed, and then a dry etching method is performed as shown in FIG. Then, the unmasked portion of the aluminum film is removed, and aluminum wirings 58 and 59 which contact the polycrystalline silicon layer 53a which is the resistance element are formed.

However, the above-described method of forming a resistance element has a problem that the resistance value varies greatly. In particular, the variation is large when the dose amount at the time of ion implantation for resistance value adjustment is small and the set resistance value is high. The resistivity of the polycrystalline silicon layer largely changes depending on the size of the crystal grain boundary, and this change appears as a variation in the resistance value when the dose amount at the time of ion implantation is small.

[0006]

In view of the above circumstances, the present invention aims to reduce variations in resistance value in a method of providing a resistive element composed of a polycrystalline silicon layer having a linear pattern on a substrate. To do.

[0007]

In order to solve the above problems, in the method of forming a resistance element according to the present invention, when a resistance element made of a polycrystalline silicon layer having a linear pattern is provided on a substrate, impurities are doped. A polycrystalline silicon layer whose surface is covered with a nitride film mask is formed in a pattern wider than the linear pattern on the substrate, and the side surface portion of the polycrystalline silicon layer is oxidized. The polycrystalline silicon layer having the linear pattern is formed.

The resistance element formed by the method of the present invention includes, for example, a resistance element which is a component of a semiconductor integrated circuit such as SRAM, but it goes without saying that the resistance element is not limited to this. Further, the substrate on which the resistance element is provided includes, for example, a silicon substrate, but is not limited to this, and may be, for example, a ceramic insulating substrate.

In the case of the present invention, the polycrystalline silicon layer
The surface of the is covered with a nitride mask, but it is usually polycrystalline.
A nitride film is also provided on the back side of the silicon layer, and polycrystalline silicon
A thin silicon oxide layer should be placed between the surface of the layer and the nitride mask.
To be provided. Further, in the case of this invention, the polycrystalline silicon
The impurity dose of the con layer is high (normally 10¹⁴cm ^-2
Above).

[0010]

In the case of the present invention, even if the resistance value is high, the impurity dose in the polycrystalline silicon layer on the substrate is set to be high and the variation in the resistivity due to the size of the crystal grain boundary is caused. Can be eliminated. This is because when the impurities are implanted with a high dose amount, the impurities basically dominate the resistivity, and the influence of the size of the crystal grain boundary on the resistivity can be ignored. However, if the dose amount is increased, the resistivity decreases, and the width of the linear pattern must be made extremely narrow to form a resistance element with a high resistance value. Machining cannot perform machining with sufficient accuracy, and variations in resistance value occur due to insufficient machining accuracy. However, in the case of the present invention, the polycrystalline silicon layer on the substrate is formed with a pattern wider than a predetermined linear pattern with a margin and with high accuracy, and then the side surface of the polycrystalline silicon layer from the lateral direction is formed. Since the portion is oxidized to narrow it into a predetermined linear pattern, the linear pattern with a high resistance and a narrow width can be formed with high accuracy without any problems. The line width of the linear pattern can be easily controlled by adjusting the oxidation time of the side surface. Since the linear pattern with a narrow width can be formed with high accuracy, the length of the resistance element itself can be suppressed. Therefore, it is possible to cope with the miniaturization of the element and eventually the miniaturization of the LSI. Become.

[0011]

Embodiments of the present invention will be described below. Needless to say, the present invention is not limited to the following embodiments. First, as shown in FIG. 1, on the thick silicon oxide film (field oxide film) 2 formed on the surface of the silicon substrate 1,
CV the silicon nitride film 3 with a thickness of 500 to 1000Å
After the deposition by the D method, the polycrystalline silicon film 4 is deposited by the CVD method, and then impurities such as phosphorus are introduced (doped) by the ion implantation method for adjusting the resistance. The dose of impurities at this time is usually 10 ¹⁴ cm ^-2 or more so as to obtain a stable resistivity.

After doping the polycrystalline silicon film 4 with impurities, as shown in FIG. 2, after forming a thermal oxide film 5 of about 500 Å, a silicon nitride film 6 of about 500 to 1000 Å is then formed by the CVD method. accumulate. Then, as shown in FIG. 3, a photoresist mask 7a for patterning,
7b is formed on the polycrystalline silicon film, and the silicon nitride film 6, the thermal oxide film 5,
The unmasked portion of the polycrystalline silicon film 4 is removed, and the polycrystalline silicon layers 4a and 4b having a pattern slightly wider than the predetermined linear pattern are formed.

Linear pattern polycrystalline silicon layers 4a, 4
In each of b, the surface is covered with the silicon nitride film masks 6a and 6b through the thermal oxide films 5a and 5b while being doped with impurities, and the back surface is also in contact with the silicon nitride film 3. .. Then, after removing the photoresist masks 7a and 7b, the polycrystalline silicon layers 4a and 4b are removed.
The side surface portion of b is selectively oxidized from the lateral direction. The oxidation conditions are
The line width before oxidation is measured by a SEM for length measurement, and the line is oxidized by Tox calculated by the following formula (1). In this selective oxidation, as shown in FIG. 4, the polycrystalline silicon layers 4a,
The side portions 13 and 14 of 4b are oxidized to be an insulator,
Polycrystalline silicon layers 15 and 16 having a predetermined linear pattern, which are resistance elements, are formed.

Tox = (XL −X) / 2 (1) where To
x: oxidation width dimension on one side, XL: line width before oxidation, X: final line width selective oxidation in a predetermined linear pattern after oxidation, and then the silicon nitride film 3 is etched by an etching method using a hot phosphoric acid solution. After removing the exposed portion (a portion other than the back surface portion such as the silicon nitride film 3a) and the silicon nitride films 6a and 6b, a silicon oxide film 18 is deposited by an CVD method as an interlayer insulating oxide film as shown in FIG. This silicon oxide film 1
A photoresist mask (not shown) for forming a contact hole is formed on the contact hole 8, and a part of the silicon oxide film 18 is removed by a dry etching method to open contact holes 21 and 22. Ions are implanted from 21 and 22 with a high dose to obtain ohmic contact. Then, after performing an annealing treatment for activating the implanted ions, an aluminum film is deposited by a sputtering method, and a photoresist mask (not shown)
Then, as shown in FIG. 6, the unmasked portion of the aluminum film is removed by dry etching to complete the aluminum wirings 19 and 20 contacting the polycrystalline silicon layers 15 and 16 which are resistance elements.

In the above case, the final width X of the polycrystalline silicon layers 15 and 16 which are resistance elements is controlled on the basis of a very controllable parameter of lateral oxidation of the side surface portion, and therefore is extremely high. Be accurate. It is also possible to control the final width X of the polycrystalline silicon layers 15 and 16 on the order of half micron.

[0016]

According to the method of forming a resistance element of the present invention, even when the resistance value is high, the dose amount of impurities in the polycrystalline silicon layer on the substrate is set high and the size of the crystal grain boundary is increased. It is possible to eliminate the variation in the resistivity caused by the resistance, and it is possible to easily form a narrow linear pattern for high resistance values with high accuracy. It is very useful because it can handle

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a process of forming a polycrystalline silicon film doped with impurities in an example.

FIG. 2 is a cross-sectional view showing a step of forming a silicon nitride film for a nitride film mask in an example.

FIG. 3 is a cross-sectional view showing a patterning process of a polycrystalline silicon film in an example.

FIG. 4 is a cross-sectional view showing an oxidation step of a side surface portion of a polycrystalline silicon layer in an example.

FIG. 5 is a cross-sectional view showing a step of forming a contact hole in a silicon oxide film in an example.

FIG. 6 is a cross-sectional view showing an aluminum wiring forming step in an example.

FIG. 7 is a cross-sectional view showing a step of forming a polycrystalline silicon film doped with impurities by a conventional method.

FIG. 8 is a cross-sectional view showing a patterning process of a polycrystalline silicon film by a conventional method.

FIG. 9 is a cross-sectional view showing a step of forming an interlayer insulating oxide film by a conventional method.

FIG. 10 is a cross-sectional view showing a step of forming a contact hole in a silicon oxide film by a conventional method.

FIG. 11 is a cross-sectional view showing a step of forming an aluminum wiring by a conventional method.

[Explanation of Codes] 1 silicon substrate 4a wide pattern polycrystalline silicon layer 4b wide pattern polycrystalline silicon layer 6a silicon nitride film mask 6b silicon nitride film mask 15 linear pattern polycrystalline silicon layer 16 linear pattern Polycrystalline silicon layer

Claims (1)

[Claims] 1. A method for providing a resistive element composed of a polycrystalline silicon layer having a linear pattern on a substrate, wherein a polycrystalline silicon layer doped with impurities and having a surface covered with a nitride film mask is provided on the substrate. A method of forming a resistance element, in which a polycrystalline silicon layer having a linear pattern is formed, and a side surface portion of the polycrystalline silicon layer is oxidized to form the polycrystalline silicon layer having the linear pattern. ..