JPS6336140B2 - - Google Patents
Info
- Publication number
- JPS6336140B2 JPS6336140B2 JP12409879A JP12409879A JPS6336140B2 JP S6336140 B2 JPS6336140 B2 JP S6336140B2 JP 12409879 A JP12409879 A JP 12409879A JP 12409879 A JP12409879 A JP 12409879A JP S6336140 B2 JPS6336140 B2 JP S6336140B2
- Authority
- JP
- Japan
- Prior art keywords
- polysilicon
- layer
- metal layer
- wiring
- resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 30
- 229920005591 polysilicon Polymers 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 21
- 239000012535 impurity Substances 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 9
- 238000010438 heat treatment Methods 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 4
- 238000002844 melting Methods 0.000 claims 2
- 238000000151 deposition Methods 0.000 claims 1
- 230000008018 melting Effects 0.000 claims 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 15
- 229910052750 molybdenum Inorganic materials 0.000 description 15
- 239000011733 molybdenum Substances 0.000 description 15
- 239000000758 substrate Substances 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
本発明は、半導体装置の製法に関し、特にシリ
コンゲートプロセスに適合するポリシリコン配線
形成法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming polysilicon wiring that is compatible with a silicon gate process.
従来、いわゆるMOS型ICの製作にあたつては、
シリコンゲートプロセスが広く採用されている
が、この場合、配線となるべきポリシリコン層の
一部を高抵抗部となし、これをMOS型FETの負
荷抵抗などに用いている。 Conventionally, when manufacturing so-called MOS type ICs,
The silicon gate process is widely used, and in this case, a part of the polysilicon layer that is supposed to be the wiring is made into a high-resistance part, which is used as a load resistor in a MOS FET.
ところで、これまでに提案されているこの種の
ポリシリコン配線形成法としては、比較的高比抵
抗のポリシリコン層を形成した後、その高抵抗部
となすべき部分以外の部分に選択的にリン等の不
純物を拡散して低抵抗化を図り、しかる後、高抵
抗部となすべき部分を通るような配線パターンに
したがつてポリシリコン層をパターニングする方
法がある。しかるに、この方法によると、(1)不純
物の選択拡散の際に不純物の横方向拡散により高
抵抗部となすべき部分にも不純物がドープされる
ために高抵抗部の長さ方向の寸法制御精度が低
く、従つて抵抗値精度が低いこと、(2)パターニン
グの際のエツチング処理において高抵抗部（不純
物非拡散部）と低抵抗部（不純物拡散部）とが両
者間のエツチ速度差のために異なる幅でパターニ
ングされ、幅方向の寸法制御精度も低いことなど
の問題点があつた。 By the way, this type of polysilicon wiring formation method that has been proposed so far involves forming a relatively high resistivity polysilicon layer and then selectively rinsing it in areas other than the high resistance parts. There is a method in which impurities such as the like are diffused to lower the resistance, and then the polysilicon layer is patterned according to a wiring pattern that passes through the portion that is to be a high resistance portion. However, according to this method, (1) during selective diffusion of impurities, impurities are doped into the portions that should be high resistance portions due to lateral diffusion of impurities, resulting in poor longitudinal dimensional control accuracy of high resistance portions; (2) Due to the difference in etching speed between the high resistance part (impurity non-diffused part) and the low resistance part (impurity diffused part) in the etching process during patterning. There were problems such as patterning with different widths and poor dimensional control accuracy in the width direction.
本発明の目的は、これらの問題点を解決した新
規な半導体装置の製法を提供することにある。 An object of the present invention is to provide a novel method for manufacturing a semiconductor device that solves these problems.
本発明の方法は、ポリシリコン層上に選択的に
高融点金属層を形成してからパターニングを行う
ことを特徴とするもので、以下添付図面に示す実
施例について詳述する。 The method of the present invention is characterized in that a refractory metal layer is selectively formed on a polysilicon layer and then patterned, and embodiments shown in the accompanying drawings will be described in detail below.
第１ａ図及び第１ｂ図は、本発明の一実施例に
よるMOS型ICの製造工程を示すもので、１０は
Ｐ型シリコンからなる半導体基板、１１は基板表
面に公知の選択酸化法で形成されたフイールド酸
化膜、１２はフイールド酸化膜１２のアクテイブ
領域配置用開孔部内に熱酸化法により形成された
ゲート酸化膜である。 1a and 1b show the manufacturing process of a MOS type IC according to an embodiment of the present invention, in which 10 is a semiconductor substrate made of P-type silicon, and 11 is a semiconductor substrate formed on the surface of the substrate by a known selective oxidation method. The field oxide film 12 is a gate oxide film formed by thermal oxidation within the opening for arranging the active region of the field oxide film 12.
まず、第１ａ図の工程では、ゲート酸化膜１２
にドレインコンタクト用の開孔をホトエツチング
により形成した後、ゲート層１３及び配線層１４
となるべきポリシリコン層を公知のCVD法によ
り形成し、つづいて第２図に示すようにポリシリ
コン層の高抵抗部Ｒとなすべき部分をおおうよう
なパターンＰのホトレジストマスクを形成してか
ら蒸着法によりゲート層１５及び配線層１６，１
７となるべきモリブデン層を被着する。ここで、
ポリシリコン層は所望の高抵抗部Ｒを得るに適し
た値に比抵抗が定められるもので、通常、導電型
決定不純物は全くドープされていないか、ドープ
されていてもわずかである。また、モリプデン層
は、後続の熱処理に耐えうる金属層として形成さ
れるもので、モリブデンシリサイド、タングステ
ン、タングステンシリサイドなどの層であつても
よい。次に、パターンＰのホトレジストマスクと
共にその上のモリブデン層部分を除去（リフトオ
フ）すると、モリブデン層は第２図で実線ハツチ
ングを施した領域Ｍに示すような形で残存する。
なお、第２図のパターンＰに示す部分を選択的に
露呈させるには、上述したリフトオフ法の代り
に、モリブデンの全面蒸着後でパターンＰに示す
部分をホトエツチングで選択的に除去する方法を
用いてもよい。 First, in the step of FIG. 1a, the gate oxide film 12
After forming an opening for a drain contact by photoetching, the gate layer 13 and wiring layer 14 are formed.
A polysilicon layer to be formed is formed by a known CVD method, and then, as shown in FIG. 2, a photoresist mask with a pattern P is formed to cover the portion of the polysilicon layer that is to be the high resistance part R. A gate layer 15 and wiring layers 16 and 1 are formed by vapor deposition.
7. Deposit a molybdenum layer. here,
The specific resistance of the polysilicon layer is determined to be a value suitable for obtaining a desired high resistance portion R, and normally it is not doped with conductivity type determining impurities at all, or even if it is doped, it is only slightly doped. Further, the molybdenum layer is formed as a metal layer that can withstand subsequent heat treatment, and may be a layer of molybdenum silicide, tungsten, tungsten silicide, or the like. Next, when the photoresist mask having the pattern P and the molybdenum layer portion thereon are removed (lifted off), the molybdenum layer remains in the form shown in the area M hatched with solid lines in FIG.
In order to selectively expose the portion shown in pattern P in Fig. 2, instead of the above-mentioned lift-off method, a method is used in which the portion shown in pattern P is selectively removed by photoetching after molybdenum is deposited on the entire surface. It's okay.
この後、所定のゲートパターン及び配線パター
ンにしたがつて、モリブデン層及びポリシリコン
層をホトエツチングにより順次にパターニング
し、ゲート層１３，１５及び配線層１４，１６，
１７を形成する。この場合、配線層のパターニン
グは第２図で破線ハツチングを付して示すように
高抵抗部Ｒを通るような帯状パターンで行われ、
この結果、高抵抗部Ｒの長さ方向の寸法は前述の
モリブデン層の選択的除去の際のパターンＰの長
辺寸法に対応して精度良く定められることにな
る。また、高抵抗部Ｒの両側においては、ポリシ
リコン配線層１４上にモリブデン配線層１６，１
７がそれぞれ積層された形の低抵抗配線部が高抵
抗部Ｒとほぼ同一の幅で精度よく形成される。こ
れは、ホトレジストをマスクとしてモリブデン層
を選択エツチした後、残存するモリブデン層及び
ホトレジスト層をマスクとして不純物濃度が均一
なポリシリコン層を選択エツチするため、高抵抗
部Ｒとその両側の低抵抗部とで実質的にエツチ速
度に差が生じないことによるものである。 Thereafter, the molybdenum layer and the polysilicon layer are sequentially patterned by photoetching according to a predetermined gate pattern and wiring pattern, and gate layers 13, 15, wiring layers 14, 16,
form 17. In this case, the wiring layer is patterned in a strip pattern that passes through the high-resistance region R, as shown by the dashed hatch in FIG.
As a result, the lengthwise dimension of the high-resistance portion R can be determined with high accuracy in correspondence with the long side dimension of the pattern P during the selective removal of the molybdenum layer described above. Further, on both sides of the high resistance part R, molybdenum wiring layers 16 and 1 are formed on the polysilicon wiring layer 14.
A low-resistance wiring portion in the form of laminated wires 7 is formed with almost the same width as the high-resistance portion R with high accuracy. This is because the molybdenum layer is selectively etched using the photoresist as a mask, and then the polysilicon layer with uniform impurity concentration is selectively etched using the remaining molybdenum layer and the photoresist layer as masks. This is because there is virtually no difference in etching speed.
次に、第１ｂ図の工程では、高抵抗部Ｒをおお
うようにホトレジストあるいはCVD法による
SiO2膜などからなるマスク層１８を形成した後、
リンあるいはヒ素などのＮ型決定不純物をマスク
層１８におおわれない部分に選択的に打込み不純
物を活性化するに非要な熱処理を行う。このよう
な処理によりゲート層１３，１５の両側にはそれ
に自己整合した形でN+型ソース領域１９及びN+
型ドレイン領域２０が形成されると共に、モリブ
デン層１５の下のポリシリコン層１３と、ポリシ
リコン層１４のモリブデン層１６及び１７の下方
部分とは上記イオン打込みにより導入された不純
物により低抵抗化される。そして、ドレイン領域
２０に隣接する基板表面部分には、モリブデン層
１６の下のポリシリコン層部分に上記イオン打込
みで導入された不純物が前述の熱処理により拡散
されるため、N+型ドレインコンタクト領域２１
が形成される。 Next, in the step shown in Figure 1b, a photoresist or CVD method is applied to cover the high resistance part R.
After forming the mask layer 18 made of SiO 2 film or the like,
An N-type determining impurity such as phosphorus or arsenic is selectively implanted into a portion not covered by the mask layer 18, and unnecessary heat treatment is performed to activate the impurity. Through such processing, N + type source regions 19 and N + type source regions are formed on both sides of the gate layers 13 and 15 in a self-aligned manner.
While the mold drain region 20 is formed, the polysilicon layer 13 under the molybdenum layer 15 and the lower portions of the molybdenum layers 16 and 17 of the polysilicon layer 14 are lowered in resistance by the impurities introduced by the ion implantation. Ru. The impurities introduced into the polysilicon layer below the molybdenum layer 16 by the above-mentioned heat treatment are diffused into the substrate surface area adjacent to the drain region 20, so that the N + type drain contact region 20
is formed.
以上のように、本発明の方法は、シリコンゲー
トプロセスと両立しうるものであつて、高抵抗部
を有するポリシリコン配線を寸法精度よく形成す
ることができ、特に高抵抗部を抵抗値精度よく形
成できるなど優れた作用効果を奏するものであ
る。 As described above, the method of the present invention is compatible with the silicon gate process, can form polysilicon wiring having high resistance parts with high dimensional accuracy, and in particular, can form high resistance parts with high resistance value accuracy. It has excellent functions and effects, such as being able to be formed easily.
第１ａ図及び第１ｂ図は、本発明の一実施例に
よるMOS型ICの製造工程を示す基板断面図、第
２図は、第１ａ図の工程における高抵抗部形成処
理を説明するための平面図である。
１０……半導体基板、１１……フイールド酸化
膜、１２……ゲート酸化膜、１３……ポリシリコ
ンゲート層、１４……ポリシリコン配線層、１５
……モリブデンゲート層、１６，１７……モリブ
デン配線層、１９……ソース領域、２０……ドレ
イン領域、Ｒ……高抵抗部。
1a and 1b are cross-sectional views of a substrate showing the manufacturing process of a MOS type IC according to an embodiment of the present invention, and FIG. 2 is a plan view for explaining the high resistance part forming process in the process of FIG. 1a. It is a diagram. 10... Semiconductor substrate, 11... Field oxide film, 12... Gate oxide film, 13... Polysilicon gate layer, 14... Polysilicon wiring layer, 15
... Molybdenum gate layer, 16, 17 ... Molybdenum wiring layer, 19 ... Source region, 20 ... Drain region, R ... High resistance part.
Claims (1)
であつて、所要の高抵抗部を得るに適した値に比
抵抗が定められたポリシリコン層の上に後続の熱
処理に耐えうる高融点金属層を被着した後、前記
高抵抗部となすべきポリシリコン部分を露呈させ
るように前記金属層を選択的に除去し、しかる後
前記金属層及び前記ポリシリコン層を、前記露呈
されたポリシリコン部分を通るような配線パター
ンにしたがつて順次パターニングすることを特徴
とする半導体装置の製法。 ２ ポリシリコン配線を有する半導体装置の製法
であつて、所要の高抵抗部を得るに適した値に比
抵抗が定められたポリシリコン層の上に後続の熱
処理に耐えうる高融点金属層を被着した後、前記
高抵抗部となすべきポリシリコン部分を露呈させ
るように前記金属層を選択的に除去し、しかる後
前記金属層及び前記ポリシリコン層を、前記露呈
されたポリシリコン層を通るような配線パターン
にしたがつてパターニングし、この結果として得
られるポリシリコン及び金属の２層配線層の所定
部分に導電型決定不純物をドープして当該部分の
ポリシリコンを低抵抗化することを特徴とする半
導体装置の製法。[Scope of Claims] 1. A method for manufacturing a semiconductor device having polysilicon wiring, which provides a polysilicon layer having a specific resistance set to a value suitable for obtaining a required high resistance portion, which can withstand subsequent heat treatment. After depositing the high melting point metal layer, the metal layer is selectively removed to expose the polysilicon portion that is to become the high resistance portion, and then the metal layer and the polysilicon layer are removed from the exposed portion. 1. A method for manufacturing a semiconductor device, characterized in that patterning is performed sequentially according to a wiring pattern that passes through a polysilicon portion. 2 A method for manufacturing a semiconductor device having polysilicon wiring, in which a high-melting point metal layer that can withstand subsequent heat treatment is coated on a polysilicon layer whose specific resistance is set to a value suitable for obtaining a required high-resistance part. After the metal layer is deposited, the metal layer is selectively removed to expose the polysilicon portion that is to become the high resistance part, and then the metal layer and the polysilicon layer are passed through the exposed polysilicon layer. It is characterized by patterning according to the wiring pattern, and doping a conductivity type determining impurity into a predetermined part of the resulting two-layer wiring layer of polysilicon and metal to lower the resistance of the polysilicon in the relevant part. A method for manufacturing semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12409879A JPS5648165A (en) | 1979-09-28 | 1979-09-28 | Preparation of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12409879A JPS5648165A (en) | 1979-09-28 | 1979-09-28 | Preparation of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5648165A JPS5648165A (en) | 1981-05-01 |
| JPS6336140B2 true JPS6336140B2 (en) | 1988-07-19 |
Family
ID=14876865
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12409879A Granted JPS5648165A (en) | 1979-09-28 | 1979-09-28 | Preparation of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5648165A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59225565A (en) * | 1983-06-06 | 1984-12-18 | Mitsubishi Electric Corp | Manufacture of metal ballast resistor in semiconductor device |
| JPS60116272A (en) * | 1983-11-28 | 1985-06-22 | Fujitsu Ltd | Transmission control system of facsimile |
| JPS61230363A (en) * | 1985-04-04 | 1986-10-14 | Fujitsu Ten Ltd | Semiconductor integrated device |
| IT1186485B (en) * | 1985-12-20 | 1987-11-26 | Sgs Microelettronica Spa | MONOLITHIC INTEGRATED CIRCUIT, IN PARTICULAR OF THE MOS OR CMOS TYPE AND PROCESS FOR THE REALIZATION OF SUCH CIRCUIT |
| JPH01302748A (en) * | 1988-05-30 | 1989-12-06 | Sharp Corp | Manufacture of semiconductor device |
-
1979
- 1979-09-28 JP JP12409879A patent/JPS5648165A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5648165A (en) | 1981-05-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5187109A (en) | Lateral bipolar transistor and method of making the same | |
| US4475964A (en) | Method of manufacturing a semiconductor device | |
| US5185285A (en) | Method of producing polycrystalline silicon resistor | |
| US3933528A (en) | Process for fabricating integrated circuits utilizing ion implantation | |
| US5420058A (en) | Method of making field effect transistor with a sealed diffusion junction | |
| JPH04348077A (en) | Thin-film transistor | |
| JPS6336140B2 (en) | ||
| JP2544937B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPS61182267A (en) | Manufacture of semiconductor device | |
| EP0042040B1 (en) | Method of manufacturing an insulated gate field-effect transistor in a silicon wafer | |
| JPH0230573B2 (en) | ||
| JPS6052591B2 (en) | Method for manufacturing semiconductor integrated circuit device | |
| JP3013385B2 (en) | Method for manufacturing semiconductor device | |
| JPS6220711B2 (en) | ||
| JP3651901B2 (en) | Method for manufacturing lateral bipolar transistor | |
| JP3036034B2 (en) | Method for manufacturing semiconductor device | |
| JPS59105366A (en) | Manufacture of metal oxide semiconductor type transistor | |
| JPS6145392B2 (en) | ||
| JPH0482220A (en) | Manufacture of semiconductor device | |
| JPH03283419A (en) | Semiconductor and manufacture thereof | |
| JPH0786195A (en) | Fabrication of semiconductor device | |
| JPS60251670A (en) | Manufacture of semiconductor device | |
| JPH0410620A (en) | Manufacture of semiconductor device | |
| JPH02275639A (en) | Manufacture of semiconductor device | |
| JPH0445523A (en) | Manufacture of semiconductor device |