JPS61230363A - Semiconductor integrated device - Google Patents

Semiconductor integrated device

Info

Publication number
JPS61230363A
JPS61230363A JP60071827A JP7182785A JPS61230363A JP S61230363 A JPS61230363 A JP S61230363A JP 60071827 A JP60071827 A JP 60071827A JP 7182785 A JP7182785 A JP 7182785A JP S61230363 A JPS61230363 A JP S61230363A
Authority
JP
Japan
Prior art keywords
resistor
section
output
external terminal
external
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60071827A
Other languages
Japanese (ja)
Inventor
Masahiko Fujimoto
正彦 藤本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Ten Ltd
Original Assignee
Denso Ten Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Ten Ltd filed Critical Denso Ten Ltd
Priority to JP60071827A priority Critical patent/JPS61230363A/en
Publication of JPS61230363A publication Critical patent/JPS61230363A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/647Resistive arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To form the titled device in a small mounting area without requiring the external attaching of a resistor isolating a circuit input section or output section for a semiconductor chip, in which a predetermined circuit is integrated, and an external terminal in a high-frequency manner by connecting the resistor in series between both the circuit input section or output section and the external terminal. CONSTITUTION:One parts of a lead frame 11 for an input (output) section required are cut, and resistors R are inserted to the cut sections. Consequently, suitability to an electromagnetic environment can be improved on the IC side, thus increasing the degree of freedom in the design, then eliminating the need for a countermeasure to the electromagnetic environment in a system into which an IC is incorporated. A mounting area is not made wider than the countermeasure of improvement by external attaching parts, high-density mounting is enabled, and these effects are effective for not only the case when an analog IC malfunctions by an electromagnetic field from the outside but also the case when an IC into which a clock source is incorporated leaks out a clock component to the outside as seen in a microprocessor, a successive comparison A/D converter, etc. and other apparatus are malfunctioned.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、電磁環境適合性を向上させた半導体集積装置
に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated device with improved electromagnetic environment compatibility.

〔従来の技術〕[Conventional technology]

電子機器の多様化、普遍化に伴ない該機器が使用される
環境も多様化している。このうち電磁環境の悪い条件下
で使用される機器の例として車載用機器を挙げることが
できる。これには2通りのケースがある。1つは自動車
のイグニッションノイズ、或いは搭載される無線通信装
置の発する電磁波等の影響を車載用の電子機器が受ける
ケースである。この場合、該機器がエンジン制御のよう
に自動車の走行に関する制御用であると、その誤動作は
人命にかかわるので危険である。他のケースは、車載用
の電子機器が電磁波源となり、それが発生するノイズ成
分(クロック周波数の電磁波等)が同じ車室内に搭載さ
れている他の車載用機器(例えばラジオ受信機)に悪影
響を及ぼす場合である。
As electronic devices become more diverse and universal, the environments in which they are used are also becoming more diverse. Among these, in-vehicle equipment can be cited as an example of equipment used under poor electromagnetic environment conditions. There are two cases for this. One is a case in which in-vehicle electronic equipment is affected by the ignition noise of the car or electromagnetic waves emitted by an on-board wireless communication device. In this case, if the device is used to control the running of a car, such as engine control, it is dangerous because its malfunction could endanger human life. In other cases, in-vehicle electronic equipment becomes a source of electromagnetic waves, and the noise components it generates (clock frequency electromagnetic waves, etc.) have an adverse effect on other in-vehicle equipment (for example, radio receivers) installed in the same vehicle interior. This is a case where

従来はこのような電磁環境下で使用される電子機器の電
磁環境適合性を増すために、第4図に示すように挿入抵
抗Rを用いることがある。この抵抗Rはコンパレータ1
やA/Dコンバータ2のようなアナログICの入力イン
ピダンス(回路入力部は一般にpnp )ランジスタの
ベース)に比して十分に小さく、回路動作上無視できる
値(例えばIKΩ以下)に選定される。この抵抗Rの機
能は理論的には十分解明されていないが、経験的には高
周波帯域(例えば100MHz以上)でローパスフィル
タに類似した高周波阻止機能が確認されており、この他
に演算増幅器やマイクロブロセッサの入(出)力端子部
でも使用されることがある。
Conventionally, in order to increase the electromagnetic compatibility of electronic equipment used in such an electromagnetic environment, an insertion resistor R is sometimes used as shown in FIG. 4. This resistance R is comparator 1
The impedance is selected to be sufficiently small compared to the input impedance of an analog IC such as the A/D converter 2 (the circuit input part is generally the base of a PNP transistor) and can be ignored in terms of circuit operation (for example, IKΩ or less). The function of this resistor R has not been fully elucidated theoretically, but it has been empirically confirmed that it has a high-frequency blocking function similar to a low-pass filter in high frequency bands (for example, 100 MHz or higher). It may also be used in input (output) terminals of processors.

コンパレータやA/Dコンバータの入力部では外部から
の影響を阻止するために使用するが、マイクロプロセッ
サの出力部ではクロック成分が外部へ漏出するのを防ぐ
ために使用する。
It is used at the input of a comparator or A/D converter to block external influences, and at the output of a microprocessor to prevent clock components from leaking to the outside.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、上述した抵抗RをIC外部に外付けする
と、■抵抗Rによって実装面積が拡大し、また■抵抗R
とIC1,2との間の配線3が長くなると効果がなくな
る欠点がある。本発明はこの点を改善しようとするもの
である。
However, if the above-mentioned resistor R is externally attached to the outside of the IC, the mounting area will be expanded by the resistor R, and
There is a drawback that if the wiring 3 between the IC 1 and the IC 2 becomes long, the effect will be lost. The present invention attempts to improve this point.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、所定の回路を集積化した半導体チップの回路
入力部または出力部と外部端子との間に、両者を高周波
的に分離する抵抗を直列に接続してなることを特徴とす
るものである。
The present invention is characterized in that a resistor is connected in series between a circuit input section or an output section of a semiconductor chip in which a predetermined circuit is integrated and an external terminal to isolate the two in terms of high frequency. be.

〔作用〕[Effect]

所定の回路を集積化した半導体チップの回路入力部また
は出力部と外部端子の間に、両者を高周波的に分離する
抵抗Rを挿入するIC構成とじておけば、該抵抗Rを外
付けする必要がないので実装面積は少な(て済み、また
第4図で示した抵抗−rc間配線3も全く問題でな(な
る。以下、図示の実施例を参照しながらこれを詳細に説
明する。
If the IC configuration is such that a resistor R is inserted between the circuit input section or output section of a semiconductor chip that integrates a predetermined circuit and an external terminal to isolate the two in terms of high frequency, it is not necessary to connect the resistor R externally. Since there is no wiring, the mounting area is small, and the wiring 3 between the resistor and rc shown in FIG. 4 is not a problem at all.This will be explained in detail below with reference to the illustrated embodiment.

〔実施例〕〔Example〕

第1図は本発明の一実施例で、10はICチップ、11
はリードフレーム(外部端子)、12はその間を接続す
るボンディングワイヤである。ここまでは一般的なIC
の構成であるが、本例では所要とする入(出)刃部のリ
ードフレーム11を一部切断してそこに前述した抵抗R
を挿入する。
FIG. 1 shows an embodiment of the present invention, where 10 is an IC chip, 11 is an IC chip, and 11 is an IC chip.
1 is a lead frame (external terminal), and 12 is a bonding wire connecting therebetween. Up to this point, it is a general IC.
However, in this example, a part of the lead frame 11 of the required input (output) blade part is cut and the above-mentioned resistor R is installed there.
Insert.

本例の抵抗Rはチップ型で、半田付けによりリードフレ
ーム11の切断部に接続される。
The resistor R in this example is of a chip type and is connected to the cut portion of the lead frame 11 by soldering.

第2図は本発明の他の実施例である。本例は通常のボン
ディングワイヤ12の代りに、NiCr。
FIG. 2 shows another embodiment of the invention. In this example, NiCr is used instead of the normal bonding wire 12.

T1Ni等の高抵抗ボンディングワイヤを用いて抵抗R
を実現したものである。この高抵抗ボンディングワイヤ
Rも通常のボンディングワイヤ12と同様にリードフレ
ーム11からICチップ10の入(出)カパッドにかけ
て設けられる。
Resistor R using high resistance bonding wire such as T1Ni
This has been realized. This high resistance bonding wire R is also provided from the lead frame 11 to the input (output) pad of the IC chip 10 in the same way as the normal bonding wire 12.

第3図はICチップ10上に抵抗Rを形成する実施例で
ある。同図において、13は表面の5102層、14は
図示せぬリードフレームとの間がボンディングワイヤで
接続されるパッド、15は該パッドからICチップ内の
回路人(出)刃部へつながるA1配線層である。本例で
はこのAI配線層15を一部切断して、そこに薄膜抵抗
Rを形成する。このi1m抵抗抵抗、NiCr、’ra
l  5n02等を蒸着、スバフタ等で付着することに
より形成される。
FIG. 3 shows an embodiment in which a resistor R is formed on the IC chip 10. In FIG. In the figure, 13 is the 5102nd layer on the front surface, 14 is a pad connected to a lead frame (not shown) with a bonding wire, and 15 is an A1 wire that connects the pad to the circuit board inside the IC chip. It is a layer. In this example, this AI wiring layer 15 is partially cut and a thin film resistor R is formed there. This i1m resistance resistance, NiCr, 'ra
It is formed by depositing 15n02 or the like by vapor deposition, sputtering, or the like.

〔発明の効果〕〔Effect of the invention〕

以上述べたように本発明によれば、電磁環境適合性をr
c側で改善できるので設計の自由度が増し、また該IC
を組入れたシステムでの電磁環境対策が不要になる利点
がある。さらに、外付は部品による改善対策(−例とし
て第4図)に比べ実装面積の拡大がなく、高密度実装が
可能となる。
As described above, according to the present invention, electromagnetic environment compatibility is
Since improvements can be made on the c side, the degree of freedom in design increases, and the
This has the advantage of eliminating the need for electromagnetic environment countermeasures in systems that incorporate Furthermore, external mounting does not increase the mounting area compared to improvement measures using parts (as shown in FIG. 4 as an example), and high-density mounting is possible.

これらの効果は、アナログICが外部からの電磁界で誤
動作する場合のみならず、マイクロプロセッサ、逐次比
較A/D変換器等のようにクロック源を内蔵するICが
外部ヘクロック成分(その高、低調波を含む)を漏出し
て他機器を誤動作させる場合にも有効である。
These effects occur not only when analog ICs malfunction due to external electromagnetic fields, but also when ICs with built-in clock sources such as microprocessors, successive approximation A/D converters, etc. It is also effective in cases where other equipment malfunctions due to leakage (including waves).

【図面の簡単な説明】[Brief explanation of the drawing]

第1図〜第3図は本発明の異なる実施例を示す構成図、
第4図は従来の電磁環境対策の一例を示す回路図である
。 図中、10はICチップ、11は外部端子、12はボン
ディングワイヤ、14はパッド、15は配線層、Rは高
周波阻止抵抗である。 出 願 人  富士通テン株式会社 代理人弁理士  青  柳   稔 2トじ内ト日口の*1tイテ11 第1図 奉養60の大施登り2 第2図 n 1lflの*柁イ列3 13図 稗入塾1九e1設6Hり 第4図
1 to 3 are configuration diagrams showing different embodiments of the present invention,
FIG. 4 is a circuit diagram showing an example of conventional electromagnetic environment countermeasures. In the figure, 10 is an IC chip, 11 is an external terminal, 12 is a bonding wire, 14 is a pad, 15 is a wiring layer, and R is a high frequency blocking resistor. Applicant Fujitsu Ten Ltd. Representative Patent Attorney Minoru Aoyagi 2 Tojinai Tohiguchi's *1t item 11 Figure 1 Hoyo 60 Oshiborori 2 Figure 2 n 1lfl *柁' column 3 13 Figure 1 Enrollment 19 e1 Establishment 6H Ri Figure 4

Claims (1)

【特許請求の範囲】[Claims] 所定の回路を集積化した半導体チップの回路入力部また
は出力部と外部端子との間に、両者を高周波的に分離す
る抵抗を直列に接続してなることを特徴とする半導体集
積装置。
1. A semiconductor integrated device comprising a resistor connected in series between a circuit input section or an output section of a semiconductor chip on which a predetermined circuit is integrated and an external terminal to isolate the two in terms of high frequency.
JP60071827A 1985-04-04 1985-04-04 Semiconductor integrated device Pending JPS61230363A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60071827A JPS61230363A (en) 1985-04-04 1985-04-04 Semiconductor integrated device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60071827A JPS61230363A (en) 1985-04-04 1985-04-04 Semiconductor integrated device

Publications (1)

Publication Number Publication Date
JPS61230363A true JPS61230363A (en) 1986-10-14

Family

ID=13471769

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60071827A Pending JPS61230363A (en) 1985-04-04 1985-04-04 Semiconductor integrated device

Country Status (1)

Country Link
JP (1) JPS61230363A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63127149U (en) * 1987-02-10 1988-08-19
EP0580855A4 (en) * 1992-02-18 1994-03-16 Intel Corporation

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5372481A (en) * 1976-12-08 1978-06-27 Mitsubishi Electric Corp Wiring constitution of lsi
JPS5596646A (en) * 1979-01-17 1980-07-23 Nec Corp Semiconductor device
JPS5648165A (en) * 1979-09-28 1981-05-01 Hitachi Ltd Preparation of semiconductor device
JPS5889832A (en) * 1981-11-24 1983-05-28 Nec Corp Semiconductor integrated circuit device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5372481A (en) * 1976-12-08 1978-06-27 Mitsubishi Electric Corp Wiring constitution of lsi
JPS5596646A (en) * 1979-01-17 1980-07-23 Nec Corp Semiconductor device
JPS5648165A (en) * 1979-09-28 1981-05-01 Hitachi Ltd Preparation of semiconductor device
JPS5889832A (en) * 1981-11-24 1983-05-28 Nec Corp Semiconductor integrated circuit device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63127149U (en) * 1987-02-10 1988-08-19
EP0580855A4 (en) * 1992-02-18 1994-03-16 Intel Corporation
EP0603158A3 (en) * 1992-02-18 1994-07-13 Sumitomo Electric Industries Advanced multilayer molded plastic package using mesic technology.

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