JPH0445523A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a gate oxide film which is highly reliable over a long period by forming a direct contact to the gate oxide film without applying any photoresist directly. CONSTITUTION:After a field oxide film 2, gate oxide film 3, polycrystalline silicon layer 4, CVD oxide film 5 are formed on a P-type silicon substrate 1, a direct contact hole 7 is formed. After the hole 7 is formed, the hole 7 is filled up with a silicide 8 by selective growth. Then an N<+> diffusion layer 9 is formed on the substrate at the direct contact part by performing phosphor diffusion after the film 5 is removed. After removing the film 3, a thin oxide film 10 is formed and an N<+> diffusion layer 11 is formed by ion implantation. Thereafter, aluminum wiring 14 is formed and patterning is performed for aluminum wiring. Therefore, the direct contact can be formed to the film 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming a contact between a gate electrode wiring and a diffusion layer (hereinafter referred to as a direct contact).

[Prior Art] A method of forming a direct contact in a conventional semiconductor device is shown in FIGS. 3(a) to 3(c). As shown in FIG. 3(a), after device isolation is performed on a P-type silicon substrate 1 by a field oxide film 2 and a gate oxide film 3 is formed thereon, a direct contact hole is formed by photolithography. The photoresist 6 is left in place other than the photoresist 6. Next, as shown in FIG. 3(b), after removing the oxide film 3 at the direct contact portion, a polycrystalline silicon layer 4 is formed, and phosphorus is diffused into the polycrystalline silicon layer 4. During this phosphorus diffusion, since there is no oxide film 3 in the direct contact area, phosphorus is diffused into the substrate 1 only in this area, and an N+ diffusion layer 9 can be formed. Next, as shown in FIG. 3(c), after patterning the gate electrode using photolithography,
Ion implantation for forming a D shadow is performed to form an N1 diffusion layer 11. Through the above steps, it becomes possible to obtain a direct electrical connection between the gate electrode wiring 9 and the diffusion layer 11.

10 is an oxide film.

[Problems to be Solved by the Invention] In the conventional direct contact forming method described above, in order to coat the photoresist 6 directly on the gate oxide film 3, cleaning is performed before growing the polycrystalline silicon layer for the gate electrode. Even if this is done, impurities tend to remain between the gate oxide film and the gate electrode, and as the gate oxide film becomes thinner to 200 Å or less as LSI speeds increase and integration increases, the relationship between the gate oxide film and the gate electrode increases. A problem arises in that the gate breakdown voltage deteriorates due to the influence of impurities between the gates and the long-term reliability of the gate oxide film deteriorates.

An object of the present invention is to provide a method for manufacturing a semiconductor device that solves the conventional problems by forming a direct contact without directly applying photoresist to a gate oxide film.

[Means for Solving the Problem] In order to achieve the above object, the method for manufacturing a semiconductor device according to the present invention includes an oxide film formation step, an oxide film removal step, a growth step, a phosphorus diffusion step, and a patterning step. A method for manufacturing a semiconductor device that includes a step of forming a diffusion layer and a step of forming a diffusion layer to form a direct contact structure between the gate electrode wiring of the semiconductor device and the diffusion layer, the oxide film forming step being a step of forming an element isolation layer on a substrate. After performing oxidation, a gate oxide film is formed on the substrate, and a polycrystalline silicon layer is formed on the gate oxide film, and then a CVD oxide film is formed on the polycrystalline silicon layer. The film removal step is to remove, by photolithography, the CVD oxide film, the polycrystalline silicon layer, and the gate oxide film in the portions that form a direct contact structure between the gate electrode wiring and the diffusion layer; A high-melting point metal or silicide is selectively grown in a hole opened in a part where a direct contact structure between the gate electrode wiring and the diffusion layer is formed, and the phosphorus diffusion process is performed by removing the CVD oxide film. Phosphorus diffusion is then carried out, the patterning process is to pattern the gate electrode, and the diffusion layer forming process is to form a diffusion layer in the self-alignment line on the gate electrode by ion implantation.

Further, the present invention includes a step of forming a high melting point metal silicide after the phosphorus diffusion to form the gate electrode into a two-layer wiring structure of the high melting point metal silicide and the polycrystalline silicon layer.

[Operation] According to the present invention, a direct contact is formed without applying photoresist directly to the gate oxide film. Therefore, in devices requiring high speed or high integration using a thin gate oxide film of 200 Å or less, a gate oxide film with high gate breakdown voltage and high long-term reliability can be obtained.

Further, by forming a high melting point metal or its silicide in the direct contact portion, stable and low contact resistance can be obtained.

[Example] Next, embodiments of the present invention will be described with reference to the drawings.

(Example 1) FIGS. 1A to 1B are cross-sectional views showing Example 1 of the present invention in the order of steps.

As shown in FIG. 1(a), first, a P-type silicon substrate l
After a field oxide film 2 is formed to perform element isolation, a gate oxide film 3 is formed, a polycrystalline silicon layer 4 is further formed, and a CVD oxide film 5 is formed thereon. Thereafter, patterning is performed by photolithography so that the photo resist 6 is left in areas other than the direct contact areas.

Next, as shown in FIG. 1(b), using the photoresist 6 as a mask, the CVD oxide film 5. Polycrystalline silicon layer 4. The gate oxide film 3 is etched to form a direct contact hole 7.

Next, as shown in FIG. 1(c), a high melting point metal or its silicide 8 such as W, WSi, Mo, MoSi,
Direct growth by selectively growing Ti and TiSi
Fill the contact hole 7. Since the portion other than the direct contact hole 7 is covered with the CVD oxide film 5, high melting point metal or its silicide does not grow.

Next, as shown in FIG. 1(d), after removing the CVD oxide film 5, phosphorus diffusion is performed to lower the layer resistance of the polycrystalline silicon layer 4 and to form an N" diffusion layer 9 on the substrate in the direct contact area. form.

Next, the gate electrode is patterned as shown in FIG. 1(e).

Next, as shown in FIG. 1 (0), after removing the gate oxide film 3 exposed on the substrate surface, a thin oxide film 10 is formed by thermal oxidation, and an N+ diffusion layer 1 is formed by ion implantation.
form 1.

Next, as shown in FIG. 1(2), an interlayer insulating film 12 is formed, a contact hole 13 is formed, an aluminum wiring 14 is formed, and the aluminum wiring is patterned.

Through the above steps, a direct contact can be formed without directly applying photoresist to the gate oxide film 3.

(Example 2) FIG. 2 is a sectional view showing a second embodiment of the present invention.

In this embodiment, ``high melting point metal silicide 15'' is used as the gate electrode. A two-layer structure electrode of polycrystalline silicon layer 4 is used.

[Effects of the Invention] As explained above, the present invention allows direct contact to be formed without applying photoresist directly to the gate oxide film, so it is possible to achieve high speed or high integration using a gate oxide film as thin as 200 Å or less. In devices that require the following, it is possible to obtain a gate oxide film with high gate breakdown voltage and high long-term reliability. Also, direct
Since a high melting point metal or its silicide is formed in the contact portion, there is an effect that a stable and low contact resistance can be obtained.

[Brief explanation of drawings]

Figures 1 (a) to (2) are cross-sectional views showing the first embodiment of the present invention in the order of steps, Figure 2 is a cross-sectional view showing the second embodiment of the present invention, and Figures 3 (a) to (c) are FIG. 3 is a cross-sectional view showing a conventional example in the order of steps. 1... P-type silicon substrate 2... Field oxide film 3... Gate oxide film 4... Polycrystalline silicon layer 5... CVD oxide film 6... Photoresist 7... Direct contact hole

Claims (2)

[Claims] (1) Includes an oxide film formation process, an oxide film removal process, a growth process, a phosphorus diffusion process, a patterning process, and a diffusion layer formation process, and provides direct contact between the gate electrode wiring of the semiconductor device and the diffusion layer. A method of manufacturing a semiconductor device in which a structure is formed, the oxide film forming step includes forming a gate oxide film on the substrate after element isolation on the substrate, and forming a polycrystalline silicon layer on the gate oxide film. After forming the polycrystalline silicon layer, a CVD oxide film is formed on the polycrystalline silicon layer, and in the oxide film removal step, the CVD oxide film is removed by photolithography in the portion where a direct contact structure between the gate electrode wiring and the diffusion layer is to be formed. The film, polycrystalline silicon layer, and gate oxide film are removed, and the growth process involves injecting high-melting point metal or silicide into the hole opened in the part where the direct contact structure between the gate electrode wiring and the diffusion layer is formed. The phosphorus diffusion step is to perform phosphorus diffusion after removing the CVD oxide film, the patterning step is to pattern the gate electrode, and the diffusion layer formation step is to selectively grow the oxide film. A method of manufacturing a semiconductor device, characterized in that a diffusion layer is formed in a self-aligned manner on a gate electrode by ion implantation. (2) Forming a high melting point metal silicide after the phosphorus diffusion to form the gate electrode into a two-layer wiring structure of a high melting point metal silicide and a polycrystalline silicon layer. ) The method for manufacturing a semiconductor device according to item 2.