JPS647509B2 - - Google Patents
Info
- Publication number
- JPS647509B2 JPS647509B2 JP4145781A JP4145781A JPS647509B2 JP S647509 B2 JPS647509 B2 JP S647509B2 JP 4145781 A JP4145781 A JP 4145781A JP 4145781 A JP4145781 A JP 4145781A JP S647509 B2 JPS647509 B2 JP S647509B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- forming
- oxidation
- base layer
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 16
- 230000003647 oxidation Effects 0.000 claims description 15
- 238000007254 oxidation reaction Methods 0.000 claims description 15
- 150000004767 nitrides Chemical class 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 229910021332 silicide Inorganic materials 0.000 claims description 10
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 5
- 238000002161 passivation Methods 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims 4
- 238000000576 coating method Methods 0.000 claims 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 25
- 229920005591 polysilicon Polymers 0.000 description 25
- 238000005530 etching Methods 0.000 description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
Description
【発明の詳細な説明】
この発明は半導体装置の製造方法に関し、より
詳しくは高周波トランジスタを含む半導体装置の
製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device including a high frequency transistor.
第１図は従来の製造方法になる半導体装置の素
子断面を示し、n+形基板１にn-形エピタキシヤ
ル成長層２を形成し、ｐ形活性ベース層３につな
がるP+形外部ベース層４から、およびn+形エミ
ツタ層５からそれぞれパツシベーシヨン膜１１に
開口されたコンタクトを通してベース電極２２お
よびエミツタ電極２１に配線されている。高周波
トランジスタの最大発振周波数naxはベース抵抗
に依存し、ベース抵抗が小さいほど大きくなる。
ベース抵抗を下げるにはベース電極端からエミツ
タ接合までの距離（図中ｄで示す）が小さいほど
よいが、これは設計ルールによつて決まり例えば
4μmのマージンをとる設計ルールでは約6μm程度
である。従つて、上記ベース抵抗をあまり下げる
ことができず、最大発振可能周波数naxの高いト
ランジスタが得られなかつた。 FIG. 1 shows a cross section of a semiconductor device according to a conventional manufacturing method, in which an n - type epitaxial growth layer 2 is formed on an n + type substrate 1, and a P + type external base layer connected to a p type active base layer 3 is formed. 4 and from the n + type emitter layer 5 to the base electrode 22 and the emitter electrode 21 through contacts opened in the passivation film 11, respectively. The maximum oscillation frequency nax of a high-frequency transistor depends on the base resistance, and increases as the base resistance decreases.
In order to lower the base resistance, the smaller the distance from the base electrode end to the emitter junction (indicated by d in the figure), the better, but this depends on the design rules and, for example,
According to the design rule that takes a margin of 4 μm, the margin is about 6 μm. Therefore, the base resistance could not be lowered much, and a transistor with a high maximum oscillation frequency nax could not be obtained.
この発明は以上のような点に鑑みてなされたも
ので、ベースコンタクトをエミツタ接合に近接し
て形成できる構成とし、更にベースコンタクトの
下面の半導体基体内にエミツタ接合方向に延びる
金属シリサイド層を設けるようにすることによつ
て、同じ設計ルールのもとでも距離ｄを小さくし
てベース抵抗の小さいトランジスタの製造方法を
提供することを目的としている。 This invention has been made in view of the above points, and has a structure in which the base contact can be formed close to the emitter junction, and further includes a metal silicide layer extending in the emitter junction direction within the semiconductor substrate on the lower surface of the base contact. By doing so, it is an object of the present invention to provide a method of manufacturing a transistor with a small base resistance by reducing the distance d even under the same design rule.
第２図Ａ〜Ｄはこの発明の一実施例の主要工程
段階におけるる状態を示す断面図で、活性ベース
層３を形成するまでは従来と同じようにn+形基
板１にn-形エピタキシヤル成長層２を形成した
後、ｐ形活性ベース層３を形成しシリコン基体と
し、さらにその上に酸化膜１２を形成し、その上
に耐酸化性被膜として、窒化膜３１をデポジシヨ
ンし、その表面を若干酸化して酸化膜１３を形成
した後、エミツタとなる領域上の膜１２，３１お
よび１３を公知の写真製版技術およびエツチング
技術で選択的に除去開口し、その上にn+形ポリ
シリコン膜４１を形成し、さらにその上に窒化膜
３２を形成する（第２図Ａ）。ここで基板近くの
窒化膜３１の表面を若干酸化膜１３に変えるのは
次工程でのポリシリコン膜のCF4ガス・ドライエ
ツチング時にストツパーとして使用するためで、
窒化膜は耐酸化膜として使用されることから理解
されるように薄い（50Å程度）酸化膜変換が制御
性よく形成される。さらにこのように薄くするの
は後工程でのポリシリコン膜側面を選択的に酸化
する時、ポリシリコン−窒化膜界面での酸化膜の
くいこみを小さくしてポリシリコン膜のカタの部
分のもり上がりを防止するためである。なお、ポ
リシリコン膜のパターニングに、リアクテイブ・
イオン・エツチングなどを使用する場合には、ポ
リシリコン膜と窒化膜とのエツチング速度差を大
きくすることにより酸化膜によるストツパーは不
要となる。n+形ポリシリコン膜４１の形成には、
初めからドープド・ポリシリコン膜を形成しても
よいし、ノンドープド・ポリシリコン膜を形成後
n+拡散をおこなつてもよい。さらにポリシリコ
ン膜４１の代わりにエピタキシヤル成長させ一部
結晶化したシリコン膜を使つてもよい。 FIGS. 2A to 2D are cross-sectional views showing the main process steps of an embodiment of the present invention. Until the active base layer 3 is formed, an n - type epitaxy is applied to an n + type substrate 1 in the same manner as in the prior art. After forming the layer growth layer 2, a p-type active base layer 3 is formed as a silicon substrate, an oxide film 12 is formed thereon, and a nitride film 31 is deposited thereon as an oxidation-resistant film. After slightly oxidizing the surface to form an oxide film 13, the films 12, 31, and 13 on the areas that will become emitters are selectively removed using known photolithography and etching techniques, and an n A silicon film 41 is formed, and a nitride film 32 is further formed thereon (FIG. 2A). The reason why the surface of the nitride film 31 near the substrate is slightly changed to the oxide film 13 is to use it as a stopper during the CF 4 gas dry etching of the polysilicon film in the next step.
As is understood from the fact that the nitride film is used as an oxidation-resistant film, a thin (about 50 Å) oxide film can be formed with good controllability. Furthermore, the purpose of thinning the polysilicon film in this way is that when the side surfaces of the polysilicon film are selectively oxidized in the later process, the oxidized film at the interface between the polysilicon and the nitride film is made smaller and the edges of the polysilicon film swell up. This is to prevent In addition, reactive method is used for patterning the polysilicon film.
When ion etching or the like is used, a stopper using an oxide film is not required by increasing the difference in etching speed between the polysilicon film and the nitride film. To form the n + type polysilicon film 41,
A doped polysilicon film may be formed from the beginning, or a non-doped polysilicon film may be formed.
n + diffusion may also be performed. Further, instead of the polysilicon film 41, a silicon film that is epitaxially grown and partially crystallized may be used.
次に、第２図Ｂに示すように周知の写真製版お
よびドライ・エツチング技術を用いて所要パター
ンのホトレジスト膜５１をマスクとして窒化膜３
２とポリシリコン膜４１を選択的に除去してパタ
ーニングし、さらにレジスト膜５１をマスクにし
てイオン注入によつてp+形領域４を形成する。 Next, as shown in FIG. 2B, using the well-known photolithography and dry etching techniques, the nitride film 3 is etched using the photoresist film 51 in the desired pattern as a mask.
2 and polysilicon film 41 are selectively removed and patterned, and p + -type region 4 is formed by ion implantation using resist film 51 as a mask.
つづいて、第２図Ｃに示すように、レジスト膜
５１を除去した後、酸化を施して第２図Ｂの段階
でパターニングしたポリシリコン膜４２の側面の
みに酸化膜１４を形成し、次に窒化膜３２の全部
と酸化膜１３、窒化膜３１及び酸化膜１２からな
る多層膜の一部とを除去した後に、ポリシリコン
膜４２と上記多層膜の除去によつて露出したp+
形領域４の上表面部にそれぞれ低抵抗金属シリサ
イド〔白金（Pt）、パラジウム（Pd）、モリブデ
ン（Mo）などのシリサイド〕層６１および６２
を形成する。このポリシリコン膜４２の上表面部
に形成された金属シリサイド層６１はエミツタ配
線として使用するポリシリコン膜４２の抵抗を下
げ、これによつて、ポリシリコン膜４２にドープ
ないしは拡散する不純物濃度を後述のエミツタ拡
散層形成のためのみに自由に決定でき、かつポリ
シリコン膜４２を薄くして段差を小さくし得る利
点がある。さらに、p+形領域４の表面部に形成
された金属シリサイド層６２は後述する低抵抗金
属によるベース電極につながり実効的にベース電
極端をエミツタ接合に近づける役割を果す。上記
ポリシリコン膜４２の側面の選択酸化の熱処理時
にポリシリコン膜４２を拡散源として、エミツタ
拡散層５が形成される。 Subsequently, as shown in FIG. 2C, after removing the resist film 51, oxidation is performed to form an oxide film 14 only on the side surfaces of the polysilicon film 42 patterned in the step of FIG. 2B. After removing the entire nitride film 32 and a part of the multilayer film consisting of the oxide film 13, the nitride film 31, and the oxide film 12, the polysilicon film 42 and the p + exposed by the removal of the multilayer film are removed.
Low-resistance metal silicide [silicide such as platinum (Pt), palladium (Pd), molybdenum (Mo)] layers 61 and 62 are formed on the upper surface of the shaped region 4, respectively.
form. The metal silicide layer 61 formed on the upper surface of the polysilicon film 42 lowers the resistance of the polysilicon film 42 used as the emitter wiring, thereby reducing the concentration of impurities doped or diffused into the polysilicon film 42, which will be described later. It has the advantage that it can be freely determined only for forming the emitter diffusion layer, and that the polysilicon film 42 can be made thinner and the step difference can be reduced. Further, the metal silicide layer 62 formed on the surface of the p + -type region 4 is connected to a base electrode made of a low resistance metal, which will be described later, and serves to effectively bring the end of the base electrode closer to the emitter junction. During heat treatment for selective oxidation of the side surface of the polysilicon film 42, the emitter diffusion layer 5 is formed using the polysilicon film 42 as a diffusion source.
次に第２図Ｄに示すように、パツシベーシヨン
膜としてリンガラス膜１１を形成しベースコンタ
クト用孔を明けた後にアルミ電極２２を形成す
る。ここで、ベース・コンタクト・エツヂをポリ
シリコン膜４２から少し離して形成する。これは
ベースコンタクトがずれたり、リンガラス膜１１
のサイドエツチング等により、もしポリシリコン
膜４２にコンタクトが接触するとベース・エミツ
タ間でシヨートするからである。ここで、ポリシ
リコン膜４２の側面に酸化膜１４があれば、リン
ガラス膜１１のサイドエツチで側面の酸化膜１４
までエツチングが進んだとしても酸化膜１４はリ
ンガラス膜１１に比べ非常にエツチング速度が遅
いのでポリシリコン膜４２に達するまで酸化膜１
４がエツチングされる必要がなく、写真製版のず
れのみを考えて、従来の約4μmから約2μmのマー
ジンで十分である。これによつて、ベース電極２
２の端からエミツタ接合までの距離d1はポリシリ
コン膜４２のパターニングエツジと開口部とのマ
ージンを1μmとしてもd1＝3μmとなり、更に、ベ
ース電極２２は低抵抗金属シリサイド層６２につ
ながつており、この金属シリサイド層６２とエミ
ツタ接合までの距離d2は上記ポリシリコン膜４２
の開口部とのマージンである1μm程度となり、実
効的なベース電極２２端からエミツタ接合までの
距離deffは1μm強で、従来例の約1/5になる。 Next, as shown in FIG. 2D, a phosphor glass film 11 is formed as a passivation film, a hole for a base contact is made, and then an aluminum electrode 22 is formed. Here, the base contact edge is formed a little apart from the polysilicon film 42. This may occur if the base contact shifts or if the phosphor glass film 11
This is because if the contact comes into contact with the polysilicon film 42 due to side etching or the like, it will shoot between the base and emitter. Here, if there is an oxide film 14 on the side surface of the polysilicon film 42, the oxide film 14 on the side surface can be etched by side etching of the phosphor glass film 11.
Even if the etching progresses to this point, the etching rate of the oxide film 14 is much slower than that of the phosphor glass film 11, so the oxide film 1 is etched until it reaches the polysilicon film 42.
4 does not need to be etched, and a margin of approximately 2 μm from the conventional approximately 4 μm is sufficient considering only the deviation in photolithography. With this, the base electrode 2
The distance d 1 from the end of the base electrode 2 to the emitter junction becomes 3 μm even if the margin between the patterning edge of the polysilicon film 42 and the opening is 1 μm, and the base electrode 22 is connected to the low resistance metal silicide layer 62. The distance d 2 between this metal silicide layer 62 and the emitter junction is the same as the distance d 2 between the metal silicide layer 62 and the emitter junction.
The margin with respect to the opening is about 1 μm, and the effective distance d eff from the end of the base electrode 22 to the emitter junction is a little over 1 μm, which is about 1/5 of the conventional example.
なお、以上はnpn形トランジスタについて説明
したが、pnp形トランジスタについてもこの発明
を適用できるのは勿論である。 Note that although the above description has been made regarding npn type transistors, it goes without saying that the present invention can also be applied to pnp type transistors.
以上説明したように、この発明ではエミツタ層
にコンタクトするシリコン膜の側面に熱酸化膜を
形成するようにしたのでベースコンタクトとシリ
コン膜とのマージンを小さくすることができ、更
に、低抵抗金属シリサイド層を設けることによつ
て実効的ベース電極端をエミツタ接合にさらに接
近させることができ、ベース抵抗を決定する部分
の幅を従来の約1/5にすることができる。 As explained above, in this invention, since a thermal oxide film is formed on the side surface of the silicon film that contacts the emitter layer, the margin between the base contact and the silicon film can be reduced. By providing the layer, the effective base electrode end can be brought closer to the emitter junction, and the width of the portion that determines the base resistance can be reduced to about 1/5 of the conventional width.
第１図は従来の製造方法になる半導体装置の素
子断面図、第２図Ａ〜Ｄはこの発明の一実施例の
主要工程段階における状態を示す断面図である。
図において、１は半導体基板、２はn-形エピ
タキシヤル成長層（第１導電形層）、３はｐ形ベ
ース層（第２導電形のベース層）、４はp+形外部
ベース層（低抵抗ベース層）、５はn+形エミツタ
層、１２は第２の酸化膜（第１の耐酸化性被膜の
一部）、１３は第３の酸化膜（第１の耐酸化性被
膜の一部）、１４は第１の酸化膜、２２はベース
電極、３１は窒化膜（第１の耐酸化性被膜の一
部）、３２は窒化膜（第２の耐酸化性被膜）、４
１，４２は（ポリ）シリコン膜、６１，６２は金
属シリサイド層である。なお、図中同一符号は同
一または相当部分を示す。
FIG. 1 is a sectional view of an element of a semiconductor device according to a conventional manufacturing method, and FIGS. 2A to 2D are sectional views showing states at main process steps of an embodiment of the present invention. In the figure, 1 is a semiconductor substrate, 2 is an n - type epitaxial growth layer (first conductivity type layer), 3 is a p type base layer (second conductivity type base layer), and 4 is a p + type external base layer ( 5 is an n + type emitter layer, 12 is a second oxide film (a part of the first oxidation-resistant film), and 13 is a third oxide film (a part of the first oxidation-resistant film). 14 is the first oxide film, 22 is the base electrode, 31 is the nitride film (part of the first oxidation-resistant film), 32 is the nitride film (the second oxidation-resistant film), 4
1 and 42 are (poly)silicon films, and 61 and 62 are metal silicide layers. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
するシリコン基体の上記ベース層上に第１の耐酸
化性被膜を形成する工程、上記第１の耐酸化性被
膜の一部を除去して上記第１の耐酸化性被膜に第
１の開口を形成する工程、上記第１の開口に露出
した上記ベース層上と上記第１の耐酸化性被膜上
とにわたつて第１導電形決定不純物を含むシリコ
ン膜を形成し更にこのシリコン膜上に第２の耐酸
化性被膜を形成する工程、上記シリコン膜および
上記第２の耐酸化性被膜を少なくとも上記第１の
開口上の部分が残るようにパターニングする工
程、上記パターニングされたシリコン膜の側面に
第１の酸化膜を形成する工程、この第１の酸化膜
の形成工程と同時または別工程によつて上記シリ
コン膜に含まれた上記第１導電形決定不純物を上
記ベース層内の一部に拡散させてエミツタ層を形
成する工程、上記第１および第２の耐酸化性被膜
の露出部を除去しそれによつて露出した上記シリ
コン膜および上記シリコン基体の表面部に金属シ
リサイド層を形成する工程、上記各工程を経た上
記シリコン基体上全面にパツシベーシヨン膜を形
成する工程、上記パツシベーシヨン膜に第２の開
口を形成しこの第２の開口を経て上記ベース層に
つながるベース電極を形成する工程を備えたこと
を特徴とする半導体装置の製造方法。 ２ 第１の耐酸化性被膜としてシリコン基体を酸
化して形成した第２の酸化膜と、その上に形成し
た窒化膜と、この窒化膜の表面を酸化して得られ
る第３の酸化膜とからなる多層膜を用いることを
特徴とする特許請求の範囲第１項記載の半導体装
置の製造方法。 ３ シリコン膜および第２の耐酸化性被膜のパタ
ーニングに使用したマスクを用いて第２導電形決
定不純物をベース層の不純物濃度より高濃度にな
るように導入して低抵抗ベース層を形成すること
を特徴とする特許請求の範囲第１項または第２項
記載の半導体装置の製造方法。[Scope of Claims] 1. A step of forming a first oxidation-resistant coating on the base layer of a silicon substrate having a base layer of a second conductivity type on the first conductivity type layer; forming a first opening in the first oxidation-resistant coating by removing a portion of the coating, on the base layer exposed in the first opening and on the first oxidation-resistant coating; forming a silicon film containing a first conductivity type determining impurity and further forming a second oxidation-resistant film on the silicon film; a step of patterning so that a portion above the opening remains; a step of forming a first oxide film on the side surface of the patterned silicon film; a step of diffusing the first conductivity type determining impurity contained in the silicon film into a part of the base layer to form an emitter layer; removing exposed portions of the first and second oxidation-resistant films; forming a metal silicide layer on the exposed surface of the silicon film and the silicon substrate; forming a passivation film over the entire surface of the silicon substrate that has undergone the above steps; and forming a second opening in the passivation film. A method for manufacturing a semiconductor device, comprising the step of forming a base electrode connected to the base layer through the second opening. 2. A second oxide film formed by oxidizing a silicon substrate as the first oxidation-resistant film, a nitride film formed thereon, and a third oxide film obtained by oxidizing the surface of this nitride film. A method of manufacturing a semiconductor device according to claim 1, characterized in that a multilayer film consisting of: 3 Using the mask used for patterning the silicon film and the second oxidation-resistant film, introduce a second conductivity type determining impurity to a higher concentration than the impurity concentration of the base layer to form a low resistance base layer. A method for manufacturing a semiconductor device according to claim 1 or 2, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4145781A JPS57155772A (en) | 1981-03-20 | 1981-03-20 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4145781A JPS57155772A (en) | 1981-03-20 | 1981-03-20 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57155772A JPS57155772A (en) | 1982-09-25 |
| JPS647509B2 true JPS647509B2 (en) | 1989-02-09 |
Family
ID=12608897
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4145781A Granted JPS57155772A (en) | 1981-03-20 | 1981-03-20 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57155772A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03295612A (en) * | 1990-04-12 | 1991-12-26 | Moriyama Kogyo Kk | Manufacture of concrete hollow product and mold frame apparatus and inner mold frame used therefor |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59132663A (en) * | 1983-01-19 | 1984-07-30 | Mitsubishi Electric Corp | Transistor |
| JPS60103669A (en) * | 1983-11-10 | 1985-06-07 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
| US4936928A (en) * | 1985-11-27 | 1990-06-26 | Raytheon Company | Semiconductor device |
-
1981
- 1981-03-20 JP JP4145781A patent/JPS57155772A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03295612A (en) * | 1990-04-12 | 1991-12-26 | Moriyama Kogyo Kk | Manufacture of concrete hollow product and mold frame apparatus and inner mold frame used therefor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57155772A (en) | 1982-09-25 |
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