JP2780711B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device, particularly a semiconductor device having a bipolar transistor, for example, a semiconductor device suitable for being applied to a semiconductor integrated circuit having a bipolar transistor for improving operation speed. And a method for producing the same. [Summary of the Invention] The present invention relates to a method of manufacturing a semiconductor device having a bipolar transistor separated between elements by LOCOS,
A step of forming an oxidation-resistant film such as a nitride film on an element formation region on the semiconductor substrate;
Forming an oxidation region, removing the oxidation-resistant film, flattening at least a portion of the first, and oxidizing at least the oxidation-resistant film-removed portion to the first oxidation region. Forming a second oxide region that is relatively thin;
Selectively removing the second oxidized region while leaving only a predetermined region of the second oxidized region in contact with the first oxidized region; and partially removing the second oxidized region removing portion. Forming a conductive layer extending over the first oxidized region, and forming a base electrode extraction region, that is, a graft base by diffusing impurities from the conductive layer. By forming an emitter region in the second oxidized region removing portion other than the conductive layer forming portion as an electrode for the region, the contact area between the external electrode taking out of the conductive layer and the active region can be reduced, whereby the floating It is an object of the present invention to provide a semiconductor device in which the operation speed of a transistor is improved by reducing the capacitance. [Related Art] In recent years, as the degree of integration has been improved, many transistors having a structure in which the parasitic capacitance has been reduced have been proposed. The structure of a conventional transistor will be described with reference to FIG. The transistor is surrounded by LOCOS2 on the N-type Si substrate 1. Since the separation between the emitter and the base is performed by the sidewall of the SiO ₂ film 6, the width can be made narrower than that of the conventional device. The base is taken out by the polycrystalline Si layer 5 doped with the acceptor. [Problems to be Solved by the Invention] In the transistor structure shown in FIG. 2, a submicron emitter 9 is formed by self-alignment of a polycrystalline Si base and the emitter and the base, and a propagation delay time Tpd
High speed of <100ps is realized. However, the polycrystalline Si layer 5
W 'between the edge of the LOCOS SiO ₂ layer 2 and the edge on the emitter side of
Is determined by the recession of the LOCOS bird's beak and the tolerance of mask alignment, so it is susceptible to process fluctuations, and it is difficult to reduce the size. Absent. For this reason, in a conventional transistor,
This parasitic component has hindered speeding up and miniaturization. Therefore, as a means of reducing the area of the base contact portion and increasing the speed by reducing the parasitic capacitance, for example, NTT's SST-1A process or Sony's Japanese Patent Application No. 60-111249.
A sub-micron base contact formation technology using self-alignment, such as the process of No. 2, has been proposed. However, these processes have the disadvantage that the manufacturing process is complicated and the number of process steps is large. Accordingly, the present invention provides a manufacturing method that can easily realize a submicron base contact with a small number of process steps. [Means for Solving the Problems] In a method for manufacturing a semiconductor device according to the present invention, a step of forming an oxidation-resistant film on an element formation region on a semiconductor substrate,
Selectively oxidizing the surface of the semiconductor substrate using the oxidation-resistant film as a mask to form a first oxidation region; removing the oxidation-resistant film; and etching at least the transistor by etching the first oxidation region. Exposing the formed portion to the outside and flattening the bird's beak; and oxidizing the exposed portion to form a second portion thinner than the first oxidized region.
Forming an oxidized region, and selectively removing the second oxidized region while leaving a portion of the second oxidized region in contact with the first oxidized region to form a first opening. Forming a polycrystalline semiconductor conductive layer forming at least a base electrode over the opening, and forming a second opening inside the polycrystalline semiconductor conductive layer with respect to the polycrystalline semiconductor conductive layer. A selective etching step, a step of forming an intrinsic base region by ion implantation through the second opening, and a step of diffusing impurities from the polycrystalline semiconductor conductive layer constituting the base electrode around the periphery thereof to form a graft base region. Forming a sidewall for emitter / base separation in the second opening, and forming an emitter region in a part of the intrinsic base region. To form a transistor. [Operation] In the case of the conventional structure shown in FIG.
Mask alignment is performed on the top of the beak to form an emitter-base intrinsic region. As a result, the amount of retreat of the bird's beak during LOCOS flattening varies, and the necessity of installing a transformer for mask alignment makes it impossible to reduce the base contact area. In the present invention, as will become more apparent from the description of the embodiment described later, since the intrinsic region of the emitter and the base is determined by opening the window shown in FIG. 1D, there is no problem in the prior art. Embodiment An embodiment of the present invention will be described with reference to an example of a method of manufacturing an NPN transistor shown in FIGS. 1A to 1G. A: A transistor formation region is covered with a Si ₃ N ₄ film 12, that is, an oxidation-resistant film, and thermal oxidation is performed to grow an SiO ₂ layer 2,
Form a recessed LOCOS. After etching the B Si ₃ N ₄ film 12, the SiO ₂ film is CVD
It is grown by a method, and a resist is applied to the entire surface. Then, etch back for planarization and etch the SiO ₂ to planarize the LOCOS bird's beak. The bird's beak is retracted by the last solution etching. C. A thin film 3 of SiO ₂ or the like is formed in the unoxidized region, a photoresist film 4 is applied thereon, and a window is opened inside the bird's beak by mask alignment. Overlay accuracy is ±
About 0.1μ is feasible. D Using the photoresist mask 4 formed in the process C
Etch the SiO ₂ film 3 and continue with polycrystalline S by CVD.
The i-layer 5, that is, the conductive layer is grown to a thickness of several thousand Å, and the SiO ₂ layer 6 is grown to a thickness of several thousand Å. Thereafter, an intrinsic region of the emitter and the base (hereinafter referred to as E / B) is determined by mask alignment. SiO ₂ and photoresist 7 formed in the E step D in the mask
Anisotropic etching of the layer 6 is performed, and an E / B portion is opened by selective etching of the polycrystalline Si layer 5. Intrinsic base is formed by ion implantation of F 2 acceptor and subsequent annealing. The graft base region P ⁺ is formed by diffusion from the acceptor-doped polycrystalline Si layer 5. Thereafter, a sidewall 8 for E / B separation is formed. After the emitter region is formed by ion implantation, the emitter electrode 10 and the base extraction electrode are formed by a normal metal process.
Form 11. [Effect] By comparing FIGS. 1 and 2, it can be seen that in the present invention, the area of the base contact portion is not influenced by the retreat amount of the bird's beak and is greatly reduced. The width W of the graft base of the transistor of FIG.
Is less than 1/3 of the width W 'of the graft base of the conventional transistor of FIG.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1G show a method for manufacturing a transistor of the present invention. FIG. 2 shows the structure of a conventional transistor. 1 ...... substrate, 2, 3, 6 ...... SiO ₂ layer 4,7 ...... photoresist film 5 ...... polycrystalline Si layer 8 ...... sidewall 9 ...... emitter 10 ...... emitter electrode, 11 ...... base electrode 12 …… Si ₃ N ₄ film

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Hiroyuki Miwa               6-7-35 Kita Shinagawa, Shinagawa-ku, Tokyo So               Knee Co., Ltd.                (56) References JP-A-60-216580 (JP, A)                 JP-A-60-81862 (JP, A)                 JP-A-57-10935 (JP, A)                 JP-A-52-49771 (JP, A)                 JP-A-58-172 (JP, A)

Claims (1)

(57) [Claims] Forming an oxidation-resistant film on an element formation region on a semiconductor substrate; selectively oxidizing a surface of the semiconductor substrate using the oxidation-resistant film as a mask to form a first oxidation region; Removing the film, exposing at least the transistor formation portion to the outside by etching the first oxidized region, and flattening the bird's beak; Forming a thin second oxidized region; and selectively removing the second oxidized region while leaving only a predetermined portion of the second oxidized region in contact with the first oxidized region. Forming a first opening, forming a polycrystalline semiconductor conductive layer covering at least the first opening and forming at least a base electrode, inside the first opening with respect to the polycrystalline semiconductor conductive layer And the second A selective etching step for forming an opening; a step for forming an intrinsic base region by ion implantation through the second opening; and impurities from the polycrystalline semiconductor conductive layer forming the base electrode around the intrinsic base region. Forming a graft base region by diffusing the same, forming a sidewall for emitter-base separation in the second opening, and forming an emitter region in a part of the intrinsic base region. A method for manufacturing a semiconductor device, comprising forming a transistor.