JPS60130155A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS60130155A
JPS60130155A JP58238659A JP23865983A JPS60130155A JP S60130155 A JPS60130155 A JP S60130155A JP 58238659 A JP58238659 A JP 58238659A JP 23865983 A JP23865983 A JP 23865983A JP S60130155 A JPS60130155 A JP S60130155A
Authority
JP
Japan
Prior art keywords
layer
resistance
semiconductor
polycrystalline
polycrystalline layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58238659A
Other languages
Japanese (ja)
Inventor
Satoyuki Ando
安藤　智行
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP58238659A priority Critical patent/JPS60130155A/en
Publication of JPS60130155A publication Critical patent/JPS60130155A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3215—Doping the layers
    • H01L21/32155—Doping polycristalline - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

PURPOSE:To enable elements to be made fine by preventing the decrease in resistance to the second layer when the first layer is decreased in resistance by impurity ion implantation by a method wherein, in constructing a wiring or a resistance layer used for a semiconductor memory element by means of a double- layer structure of polycrystalline Si, the second layer is electrically connected to the second layer with a high melting point metal layer. CONSTITUTION:On the surface of a semiconductor substrate 21 with circuit elements, an SiO2 film 22 of required form is produced by heat treatment in a high- temperature oxidizing atmosphere, and a polycrystalline Si layer 23 of the first layer connected to the circuit elements at one end is deposited thereon. Next, the layer 23 is decreased in resistance to be suitable for wiring purpose by impurity diffusion, and is then covered with an Si3N4 film 24. An aperture is bored by corresponding to the connection point, and the part of the exposed layer 23 is filled with a high melting point metal 25 such as W or Mo that is not permeable to impurities. Thereafter, a polycrystalline Si layer 26 of the second layer is deposited over the entire surface including it and patterned; then, the entire surface is covered with an insulation protection film 27. In such a manner, the Si layer 26 of the second layer is not decreased in resistance.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、例えば半々）本紀１意素子に使用され、配
線才たは抵抗等となる半導体多結晶層（Ｐｏ１ｙ　Ｓｉ
　：ポリシリコン）の２層構造を有する半導体装置ζこ
関する。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor polycrystalline layer (PolySi
The present invention relates to a semiconductor device ζ having a two-layer structure of polysilicon.

〔発明の技術的背景〕[Technical background of the invention]

一般に、２つの安定状、す、いからなるスタテイク型の
半導体記憶装置（ＳＲＡＭ　：　５ｔａｔｉｃ　Ｒａｎ
ｄｏｍＡｃｃｅｓｓ　ｒｅａｄ　ｗｒｉｔｅ　Ｍｅｍｏ
ｒｙ　）等は、例えば第１図Ｏこ示すように、２層構造
の半導体多結晶層１１および１２を有している。この２
層構造の半導体多結晶層１１および１２は、それぞれ、
第２図に示すようなスタテイク型記憶素子回路の、破線
ａで示すようなトランジスタ間配線と、この配線に接続
される負荷抵抗Ｒとζこ使用されるもので、このような
２層構造は次のようにして形成される。すなわち、トラ
ンジスタ等の回路素子が形成される半導体基板１３の表
面には、まず、シリコン酸化膜（Ｓｉ０２）Ｊ４を弁じ
て第１の低抵抗半導体多結晶層１１を形成し、次に、こ
の第１の半導体多結晶層１１の表面上Ｏこ、シリコン窒
化膜（Ｓ　１３Ｎ４）　１５を弁して第２の高抵抗半導
体多結晶層１２を形成している。In general, a static type semiconductor memory device (SRAM: 5tatic ran) consists of two stable states.
domAccess read write Memo
For example, as shown in FIG. This 2
The semiconductor polycrystalline layers 11 and 12 each have a layered structure,
In a static type memory element circuit as shown in Fig. 2, the wiring between transistors as shown by the broken line a and the load resistor R connected to this wiring are used, and such a two-layer structure is It is formed as follows. That is, on the surface of the semiconductor substrate 13 on which circuit elements such as transistors are formed, first, a first low-resistance semiconductor polycrystalline layer 11 is formed using a silicon oxide film (Si02) J4, and then this first A second high-resistance semiconductor polycrystalline layer 12 is formed by depositing a silicon nitride film (S13N4) 15 on the surface of the first semiconductor polycrystalline layer 11.

この場合、上記トランジスタ間配線となる第１の半導体
多結晶層１１は、例えば、リン（Ｉ））の拡散により低
抵抗化されるもので、この第１の低抵抗半導体多結晶層
１１には、上記、負荷抵抗Ｒとなる第２の高抵抗半導体
多結晶ＩＣ１１２が、直接接続を得る形で構成される。In this case, the first semiconductor polycrystalline layer 11, which becomes the wiring between the transistors, has a low resistance, for example, by diffusion of phosphorus (I). , the second high-resistance semiconductor polycrystalline IC 112 serving as the load resistance R is configured in such a way that a direct connection is obtained.

τ背景技術の問題点〕 しかしこのように第１および第２の半導体多結晶層１１
および１２を、直接接続して２層構造を形成すると、１
層目の半導体多結晶層１１をこ拡散したリンが、その接
続部を弁して２層目の半４体多結晶層１２に拡散する状
態となる。[Problems with τ background technology] However, in this way, the first and second semiconductor polycrystalline layers 11
and 12 are directly connected to form a two-layer structure, 1
The phosphorus that has diffused through the semiconductor polycrystalline layer 11 of the first layer becomes a state in which it valves the connection portion and diffuses into the second half-quadramid polycrystalline layer 12.

すなわち、負荷抵抗Ｒとして使用される２膚目の半導体
多結晶層１２は、範囲Ａで示すような接続軸域に対応し
て低抵抗化されるようになり、この２層目の半導体多結
晶層１２で所定の負荷抵抗値を得るには、予め上記低抵
抗化される接続領域Ａを考慮し、その領域分だけ矢印Ｂ
で示す方向に長く形成しなければならない。この為、回
路素子のより以上の微細化が困難をこなり、高集積度化
の妨げとなる。That is, the second semiconductor polycrystalline layer 12 used as the load resistance R has a lower resistance corresponding to the connection axis region as shown in range A, and the second semiconductor polycrystalline layer 12 In order to obtain a predetermined load resistance value in the layer 12, the connection area A to be made low in resistance is considered in advance, and the arrow B is adjusted for that area.
It must be formed long in the direction shown. For this reason, further miniaturization of circuit elements becomes difficult, which hinders higher integration.

〔発明の目的〕[Purpose of the invention]

この発明は上記のような問題点に鑑みなされたもので、
例えば１層目の半導体多結晶層をリン拡散により低抵抗
化する場合でも、２層目の半導体多結晶層まで低抵抗化
されることなく、素子の微細化が可能ζこなる半導体装
置を提供することを目的とする。This invention was made in view of the problems mentioned above.
For example, even when the resistance of the first semiconductor polycrystalline layer is lowered by phosphorus diffusion, the resistance of the second semiconductor polycrystalline layer is not lowered, and the device can be miniaturized. The purpose is to

〔発明の概要〕[Summary of the invention]

すなわちこの発明に係る半導体装置は、１１＠目の半導
体多結晶層と２層目の半導体多結晶層とを低抵抗化のた
めの不純物イオンを通すことのない高隔点金属により接
続するようにしたものである。That is, in the semiconductor device according to the present invention, the 11th semiconductor polycrystalline layer and the second semiconductor polycrystalline layer are connected by a high point metal that does not allow impurity ions to pass through to reduce resistance. This is what I did.

〔発明の実施例〕[Embodiments of the invention]

以下図面によりこの発明の一実施例を説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第３図はこの半導体装置を製造工程１１１こ示すもので
、まず、同図（Ａ）に示すように、回路素子の形成され
る半導体基板２ノの表面には、高温酸化雰囲気中にてシ
リコン酸化膜２２を形成し、このシリコン酸化膜２２の
表面ζこは、上記回路素子にその一端が接続される１層
目の半導体多結晶層２３を形成する。ここで、１層目の
半導体多結晶層２３には、リン（Ｐ）等ζこよる不純物
拡散を施し、配線として低抵抗化する。次に、第３図（
Ｂ）に示すように、リンを拡散した１層目の半導体多結
晶層２３の表面には、化学気相成長法（ＣＶＤ　：　Ｃ
ｈｅｍｉｃａｌ　Ｖａｐｕｒ　Ｄｅｐｏｓｉｔｉｏｎ　
）等によりシリコン窒化膜２４を形成し、このシリコン
鴛化膜２４には、上記１層目の半導体多結晶層２３との
接続部に対応して、写真蝕刻法（ＰＥＰ　：　Ｐｈｏｔ
ｏ　Ｅｔｃｈｉｎｇ　Ｐｖｏｃｅｓｓ）　４こよりコン
タクトホールを形成する。そして、このコンタクトホー
ルに対応する接？ｆｊｃ部には、上記リン等の不純物を
通すことのない高融点金属ノ脅２５を形成する。FIG. 3 shows the manufacturing process 111 of this semiconductor device. First, as shown in FIG. An oxide film 22 is formed, and a first semiconductor polycrystalline layer 23 whose one end is connected to the circuit element is formed on the surface ζ of this silicon oxide film 22. Here, the first semiconductor polycrystalline layer 23 is diffused with an impurity such as phosphorus (P) to lower the resistance as a wiring. Next, see Figure 3 (
As shown in B), the surface of the first semiconductor polycrystalline layer 23 in which phosphorus is diffused is coated with chemical vapor deposition (CVD).
chemical vapor deposition
), etc., and this silicon nitride film 24 is etched by photo-etching (PEP) corresponding to the connection portion with the first semiconductor polycrystalline layer 23.
o Etching Pvocess) Form a contact hole from 4 holes. And the contact corresponding to this contact hole? A high melting point metal barrier 25 that does not allow impurities such as phosphorus to pass through is formed in the fjc portion.

この高融点金属、噛２５には、例えばタングステン（４
）、モリブデン（Ｍｏ）ｔたは白金（Ｐｔ）等の材料を
使用し、この製造工程の全搬（・こ杖る高温熱処理によ
っても、融解しないようにする。This high melting point metal, tungsten (4
), molybdenum (Mo)t, or platinum (Pt) to prevent melting even during high-temperature heat treatment throughout the manufacturing process.

この後、第３１凶（ｑ　ｉこ示すよ・う０こ、上記１１
石融点金属１ｆｉ、？４を含むシリコン窒化膜２４０表
向には、２層目の半導体多結晶１熱２６を形成してパタ
ーニングし、そして半導体基板２１上に全面的に絶縁保
護膜２７を形成して構成する。ここで、上記２層目の半
導体多結晶層２６は、例えば高抵抗素子として使用され
るもので、配線となる１層目の半導体多結晶層２３とは
、高融点金属層２５を介在する形で電気的に接続された
状態となる。After this, the 31st evil
Stone melting point metal 1fi,? A second layer of semiconductor polycrystalline silicon 240 is formed and patterned on the surface of the silicon nitride film 240 including silicon nitride film 240, and an insulating protective film 27 is formed over the entire surface of the semiconductor substrate 21. Here, the second semiconductor polycrystalline layer 26 is used, for example, as a high-resistance element, and is different from the first semiconductor polycrystalline layer 23 that serves as wiring with a high melting point metal layer 25 interposed therebetween. It becomes electrically connected.

すなわちこのような半導体装置においては、１層目のリ
ンを拡散して低抵抗化した半導体多結晶層２３と、２層
目の高抵抗素子とし゛Ｃ使用される半導体多結晶層２６
とを、不純物を通すことのない高融点金属２５を弁して
電気的に接続するようにしたので、１層目２３ζこ拡散
したリンが２層目２６まで到達することはない。これに
より、２層目の半導体多結晶層２６は、１層目の半導体
多結晶層２３に拡散したリンζこ影響されずに、所定の
抵抗値を保てるようになる。In other words, in such a semiconductor device, the first layer is a semiconductor polycrystalline layer 23 in which phosphorus is diffused to reduce the resistance, and the second layer is a semiconductor polycrystalline layer 26 used as a high resistance element.
Since these are electrically connected to each other by using the high melting point metal 25 that does not allow impurities to pass through, the phosphorus diffused through the first layer 23ζ will not reach the second layer 26. As a result, the second semiconductor polycrystalline layer 26 can maintain a predetermined resistance value without being affected by the phosphorus ζ diffused into the first semiconductor polycrystalline layer 23.

したがって、２層目の半導体多結晶層２６を、リンによ
る低抵抗化の影響を考慮して、予め長く形成する必要が
ないので、特に、この２１−目の半導体多結晶層２６の
微細化が可能となる。Therefore, it is not necessary to form the second semiconductor polycrystalline layer 26 long in advance in consideration of the effect of lowering the resistance due to phosphorus, so that the miniaturization of the 21st semiconductor polycrystalline layer 26 is particularly effective. It becomes possible.

同、上記実施例では、高融点金属層２５を形成した後に
、２層目の半導体多結晶層２６を形成するようにしたが
、例えば、第４図（Ａ）および（Ｂ）に示すように、シ
リコン窒化膜２４の表面に２）ｔＩＩ目の半導体多結晶
層２６を積層パターニングした後、選択的にコンタクト
ホールを形成し高融点金属ハψ２５を形成するようにし
てもよい。Similarly, in the above embodiment, the second semiconductor polycrystalline layer 26 was formed after forming the high melting point metal layer 25, but for example, as shown in FIGS. 4(A) and 4(B), After patterning the 2) tII-th semiconductor polycrystalline layer 26 on the surface of the silicon nitride film 24, contact holes may be selectively formed to form the high melting point metal layer ψ25.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によれば、例えば１層目の半導体
多結晶層をリン拡散により低抵抗化する場合でも、２層
目の半導体多結晶層まで低抵抗化されることがないので
、２層目の抵抗領域を実質的に短縮することができ、素
子の微細化が可能Ｃとなる。これにより、この半導体装
置の集積度はさらに向上するようになる。As described above, according to the present invention, even when the resistance of the first semiconductor polycrystalline layer is lowered by phosphorus diffusion, the resistance is not lowered to the second semiconductor polycrystalline layer. The resistance region of each layer can be substantially shortened, making it possible to miniaturize the device. As a result, the degree of integration of this semiconductor device can be further improved.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来の半導体装置を示す断面構成図、第２図は
スタテイク型半導体記憶装置を示す回路−成図、第３　
ＰＩ　（Ａｔ乃至（ＣＩはそれぞれこの発明の一実施例
に係る半導体装：仇を製造工程順に示す断面構成図、第
４図囚および（Ｂ）はそれぞれこの・発明の他の実施側
を示す断面構成図である。 ２１・・・半導体基板、２２・・・シリコン酸化膜、２
３・・・１層目の低抵抗半導体多結晶層、２４・・・シ
リコン窒化膜、２５・・・高融点金属層、２６・・・２
層目の高抵抗半導体多結晶庖、２７・・絶縁保護膜。 出順人代理人　弁理士　鈴　江　武　彦第１図 ＤＬ　Ｌ）Ｌ 第　３　図 （Ａ） （Ｃ）FIG. 1 is a cross-sectional configuration diagram showing a conventional semiconductor device, FIG. 2 is a circuit diagram showing a static type semiconductor memory device, and FIG.
PI (At to (CI) are respectively cross-sectional configuration diagrams showing a semiconductor device according to an embodiment of the present invention in the order of manufacturing steps, and Figures 4 and (B) are cross-sectional diagrams showing other implementation sides of this invention It is a configuration diagram. 21... Semiconductor substrate, 22... Silicon oxide film, 2
3... First low resistance semiconductor polycrystalline layer, 24... Silicon nitride film, 25... High melting point metal layer, 26... 2
Layered high-resistance semiconductor polycrystalline layer, 27... Insulating protective film. Junjin's agent Patent attorney Takehiko Suzue Figure 1DL L)L Figure 3 (A) (C)

Claims (1)

【特許請求の範囲】[Claims] それぞれ高抵抗と低抵抗の２層の半導体多結晶層を有す
る半導体装置において、１ＪｆＪ目の半導体多結晶層と
２層目の半導体多結晶層とを高融点金頴層を弁して電気
的に接続したことを特徴とする半導体装｝′武。In a semiconductor device having two semiconductor polycrystalline layers, each having high resistance and low resistance, the 1JfJth semiconductor polycrystalline layer and the second semiconductor polycrystalline layer are electrically connected to each other through a high melting point gold layer. A semiconductor device characterized by being connected.
JP58238659A 1983-12-17 1983-12-17 Semiconductor device Pending JPS60130155A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58238659A JPS60130155A (en) 1983-12-17 1983-12-17 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58238659A JPS60130155A (en) 1983-12-17 1983-12-17 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS60130155A true JPS60130155A (en) 1985-07-11

Family

ID=17033414

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58238659A Pending JPS60130155A (en) 1983-12-17 1983-12-17 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS60130155A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62283643A (en) * 1986-05-02 1987-12-09 アドバンスト・マイクロ・デイバイシズ・インコ−ポレ−テツド Metallic contact system
JPH02113566A (en) * 1988-10-21 1990-04-25 Nec Corp Semiconductor integrated circuit
JPH03166728A (en) * 1989-11-27 1991-07-18 Matsushita Electron Corp Semiconductor device
US5453400A (en) * 1990-06-28 1995-09-26 International Business Machines Corporation Method and structure for interconnecting different polysilicon zones on semiconductor substrates for integrated circuits
JPH0818011A (en) * 1994-04-25 1996-01-19 Seiko Instr Inc Semiconductor device and its production

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62283643A (en) * 1986-05-02 1987-12-09 アドバンスト・マイクロ・デイバイシズ・インコ−ポレ−テツド Metallic contact system
JPH02113566A (en) * 1988-10-21 1990-04-25 Nec Corp Semiconductor integrated circuit
JPH03166728A (en) * 1989-11-27 1991-07-18 Matsushita Electron Corp Semiconductor device
US5453400A (en) * 1990-06-28 1995-09-26 International Business Machines Corporation Method and structure for interconnecting different polysilicon zones on semiconductor substrates for integrated circuits
US5672901A (en) * 1990-06-28 1997-09-30 International Business Machines Corporation Structure for interconnecting different polysilicon zones on semiconductor substrates for integrated circuits
JPH0818011A (en) * 1994-04-25 1996-01-19 Seiko Instr Inc Semiconductor device and its production

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