JPS61216356A - Semiconductor resistor - Google Patents
Semiconductor resistorInfo
- Publication number
- JPS61216356A JPS61216356A JP60057308A JP5730885A JPS61216356A JP S61216356 A JPS61216356 A JP S61216356A JP 60057308 A JP60057308 A JP 60057308A JP 5730885 A JP5730885 A JP 5730885A JP S61216356 A JPS61216356 A JP S61216356A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- polycrystalline silicon
- mask
- silicon
- resistive element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Non-Adjustable Resistors (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、不純物を含ませた単結晶シリコンまたは多結
晶シリコンを抵抗体とする半導体抵抗に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor resistor whose resistor is single crystal silicon or polycrystalline silicon containing impurities.
第3図に多結晶シリコンを抵抗体とする従来の半導体抵
抗を示す。第3図において、1は半導体基体、2は厚い
フィールド絶縁膜、3は多結晶シリコンによる抵抗体、
3a、3bは前記抵抗体30両端に設けられた低抵抗領
域、5は低抵抗領域3g、3bを形成するためのマスク
層で、例えばシリコン窒化物からなる。FIG. 3 shows a conventional semiconductor resistor using polycrystalline silicon as a resistor. In FIG. 3, 1 is a semiconductor substrate, 2 is a thick field insulating film, 3 is a resistor made of polycrystalline silicon,
3a and 3b are low resistance regions provided at both ends of the resistor 30, and 5 is a mask layer for forming the low resistance regions 3g and 3b, which is made of silicon nitride, for example.
一般に、抵抗体3には比較的低濃度のリン又はヒ素等の
不純物がイオン注入されてその抵抗値が決定され、引き
出し電極用として使用される低抵抗領域aa、abは、
マスク層5を利用して高濃度のリン又はヒ素が熱拡散又
はイオン注入によシ導入されて形成されるが、多結晶シ
リコン中の前記不純物の拡散は非常に速い為に、第3図
7に示すように、低抵抗領域の不純物が抵抗体3の内部
に向って数ミクロンに亘り拡散し、抵抗体3の長さ8を
短くシ、かつ再現性を悪化させていた。又、この為、抵
抗自体の寸法も、横方向の高濃度不純物の拡散70分の
マージンを取る必要から大きくなっていた。Generally, a relatively low concentration of impurity such as phosphorus or arsenic is ion-implanted into the resistor 3 to determine its resistance value, and the low resistance regions aa and ab used as extraction electrodes are
A high concentration of phosphorus or arsenic is introduced by thermal diffusion or ion implantation using the mask layer 5, but since the impurity diffuses very quickly into the polycrystalline silicon, as shown in FIG. As shown in FIG. 2, impurities in the low resistance region diffused into the resistor 3 over several microns, shortening the length 8 of the resistor 3 and deteriorating reproducibility. Moreover, for this reason, the dimensions of the resistor itself have also increased because it is necessary to provide a margin of 70 minutes for the diffusion of high concentration impurities in the lateral direction.
(問題点を解決するための手段〕
上記問題点に対し、本発明では単結晶半導体または多結
晶シリコンの抵抗体の電極引出し用領域の構造を、前記
抵抗体と、金属とシリコンとの反応生成物であるシリサ
イドとの2層構造にしている。(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a structure in which the electrode lead-out region of a single-crystal semiconductor or polycrystalline silicon resistor is formed by a reaction between the resistor, metal, and silicon. It has a two-layer structure with silicide.
つぎに本発明を実施例により説明する。 Next, the present invention will be explained by examples.
第1図は本発明の一実施例の断面図である。図において
、lは半導体基体、2は厚いフィールド絶縁膜、3は多
結晶シリコンからなる抵抗体であって、抵抗体3の表面
のマスク5で分けられた両端部に1シリサイド4a、4
bがそれぞれ形成されている0シリサイド4a、4bは
、電極引出し用の低抵抗領域をなすもので、例えば窒化
シリコンのマスク層5をマスクとして、抵抗体3の表面
に、タングステン、白金、チタンなどの金属被膜を成長
させた後、熱処理を行って、これら金属と多結晶シリコ
ンとの反応生成物を成長させるととKより形成され、一
般に多結晶シリコンよシー桁または数桁低い層抵抗を示
す。FIG. 1 is a sectional view of an embodiment of the present invention. In the figure, l is a semiconductor substrate, 2 is a thick field insulating film, and 3 is a resistor made of polycrystalline silicon.
The 0 silicides 4a and 4b in which b are formed respectively form low resistance regions for leading out electrodes. For example, using the silicon nitride mask layer 5 as a mask, tungsten, platinum, titanium, etc. are applied to the surface of the resistor 3. After growing a metal film, a heat treatment is performed to grow a reaction product between these metals and polycrystalline silicon, which is formed by K and generally exhibits a layer resistance that is orders of magnitude or several orders of magnitude lower than that of polycrystalline silicon. .
クリサイド4a 、4bは、また、スパッタなどの方法
で直接多結晶シリコン3の表面に形成することもできる
。Crystalides 4a and 4b can also be formed directly on the surface of polycrystalline silicon 3 by a method such as sputtering.
第2図は本発明の他の実施例の断面図である。FIG. 2 is a sectional view of another embodiment of the invention.
図において、lは半導体基体、12は厚いフィールド絶
縁膜、13は半導体基体lとPN接合を有する単結晶シ
リコンの抵抗体層、抵抗体層13の表面のマスク5で分
けられた両側の表面には、引出し電極を形成するために
シリサイド層6aと6bが設けられている。In the figure, l is a semiconductor substrate, 12 is a thick field insulating film, 13 is a single-crystal silicon resistor layer having a PN junction with the semiconductor substrate l, and the surfaces on both sides of the resistor layer 13 separated by a mask 5 are , silicide layers 6a and 6b are provided to form extraction electrodes.
本発明の半導体抵抗においては、電極引出しのための低
抵抗領域のシリサイドが、マスクの下部に滲み込まない
ために1マスクの寸法により、正確に抵抗値を決めるこ
とができ、よって正しい抵抗値の半導体抵抗が再現性よ
く実現できる。また、抵抗全体の寸法が、不要のマージ
ンを見込む必要がないために、小形に形成でき、高集積
化にも1刺である。In the semiconductor resistor of the present invention, since the silicide in the low resistance region for leading out the electrodes does not seep into the lower part of the mask, the resistance value can be determined accurately based on the dimensions of one mask, and therefore the correct resistance value can be determined. Semiconductor resistance can be realized with good reproducibility. In addition, since there is no need to allow for unnecessary margins in the overall size of the resistor, it can be formed compactly, and only one resistor can be used for high integration.
第1図は本発明の一実施例の断面図、第2図は本発明の
他の実施例の断面図、第3図は従来の半導体抵抗の断面
図である。
1.11・・・・・・半導体基体、2,12・・・・・
・厚いフィールド絶縁膜、3・・・・・・多結晶シリコ
ン抵抗体、4a、4b、6m、6b・・・・・・シリサ
イド、5・・・・・・マスク、7・・・・・・横方向拡
散領域、8・・・・・・抵抗体寸法。
第 3図FIG. 1 is a sectional view of one embodiment of the present invention, FIG. 2 is a sectional view of another embodiment of the invention, and FIG. 3 is a sectional view of a conventional semiconductor resistor. 1.11... Semiconductor substrate, 2,12...
・Thick field insulating film, 3... Polycrystalline silicon resistor, 4a, 4b, 6m, 6b... Silicide, 5... Mask, 7... Lateral diffusion area, 8... Resistor dimensions. Figure 3
Claims (1)
体抵抗において、前記抵抗体の両端に設けられた接続用
領域の表面には、金属とシリコンとの反応生成物である
シリサイドを有することを特徴とする半導体抵抗。A semiconductor resistor using a single crystal semiconductor or polycrystalline silicon as a resistor, characterized in that the surface of the connection region provided at both ends of the resistor has silicide, which is a reaction product of metal and silicon. A semiconductor resistor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60057308A JPS61216356A (en) | 1985-03-20 | 1985-03-20 | Semiconductor resistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60057308A JPS61216356A (en) | 1985-03-20 | 1985-03-20 | Semiconductor resistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61216356A true JPS61216356A (en) | 1986-09-26 |
Family
ID=13051933
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60057308A Pending JPS61216356A (en) | 1985-03-20 | 1985-03-20 | Semiconductor resistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61216356A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01283851A (en) * | 1988-05-10 | 1989-11-15 | Seiko Epson Corp | Semiconductor device |
JPH0319273A (en) * | 1989-06-15 | 1991-01-28 | Nec Corp | Semiconductor device |
JPH04229647A (en) * | 1990-04-27 | 1992-08-19 | Digital Equip Corp <Dec> | Precision resistor by self-aligned silicon compound mos process |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54107279A (en) * | 1978-02-10 | 1979-08-22 | Nec Corp | Semiconductor device |
-
1985
- 1985-03-20 JP JP60057308A patent/JPS61216356A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54107279A (en) * | 1978-02-10 | 1979-08-22 | Nec Corp | Semiconductor device |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01283851A (en) * | 1988-05-10 | 1989-11-15 | Seiko Epson Corp | Semiconductor device |
JPH0319273A (en) * | 1989-06-15 | 1991-01-28 | Nec Corp | Semiconductor device |
JPH04229647A (en) * | 1990-04-27 | 1992-08-19 | Digital Equip Corp <Dec> | Precision resistor by self-aligned silicon compound mos process |
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