JP2919218B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

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Publication number
JP2919218B2
JP2919218B2 JP4344193A JP4344193A JP2919218B2 JP 2919218 B2 JP2919218 B2 JP 2919218B2 JP 4344193 A JP4344193 A JP 4344193A JP 4344193 A JP4344193 A JP 4344193A JP 2919218 B2 JP2919218 B2 JP 2919218B2
Authority
JP
Japan
Prior art keywords
element region
resistance element
semiconductor device
resistance
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP4344193A
Other languages
Japanese (ja)
Other versions
JPH06260597A (en
Inventor
功 板垣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Yamagata Ltd
Original Assignee
NEC Yamagata Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Yamagata Ltd filed Critical NEC Yamagata Ltd
Priority to JP4344193A priority Critical patent/JP2919218B2/en
Publication of JPH06260597A publication Critical patent/JPH06260597A/en
Application granted granted Critical
Publication of JP2919218B2 publication Critical patent/JP2919218B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特に半導体基板に不純物を導入して形成する抵抗
素子を有する半導体装置の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a resistance element formed by introducing impurities into a semiconductor substrate.

【0002】[0002]

【従来の技術】半導体装置の製造方法において、異なっ
たシート抵抗を有する2種類の抵抗素子を形成する従来
技術の一例を図2を用いて説明する。
2. Description of the Related Art An example of a conventional technique for forming two types of resistance elements having different sheet resistances in a method of manufacturing a semiconductor device will be described with reference to FIG.

【0003】先ず、図2(a)に示すように熱酸化によ
りN型半導体基板1表面に数十nmの厚さのシリコン酸
化膜2aを形成し、その後周知のフォトリソグラフィ技
術により、第3抵抗素子形成予定領域を開口するよう
に、シリコン酸化膜2a上にフォトレジスト3aを形成
し、続いてP型不純物であるホウ素をイオン注入する事
により第3抵抗素子領域4cを形成する。
First, as shown in FIG. 2A, a silicon oxide film 2a having a thickness of several tens nm is formed on the surface of an N-type semiconductor substrate 1 by thermal oxidation, and thereafter, a third resistor is formed by a known photolithography technique. A photoresist 3a is formed on the silicon oxide film 2a so as to open a region where an element is to be formed, and then a third resistance element region 4c is formed by ion-implanting boron which is a P-type impurity.

【0004】次に、図2(b)に示す様に、前述の第3
抵抗素子領域4cの形成と同様な工程を行う事により、
第4抵抗素子領域4dを形成する。このとき、第3抵抗
素子領域4cと第4抵抗素子領域4dにイオン注入する
ホウ素の打ち込み量は、それぞれ所望のシート抵抗にな
る様に自由に選択する。
[0004] Next, as shown in FIG.
By performing the same process as the formation of the resistance element region 4c,
The fourth resistance element region 4d is formed. At this time, the implantation amount of boron for ion implantation into the third resistance element region 4c and the fourth resistance element region 4d is freely selected so as to obtain a desired sheet resistance.

【0005】次に図2(c)に示す様に熱処理を行い、
不純物を活性化させる事によりそれぞれ異なるシート抵
抗を有する2種類の抵抗素子を形成していた。
Next, heat treatment is performed as shown in FIG.
By activating the impurities, two types of resistance elements having different sheet resistances are formed.

【0006】[0006]

【発明が解決しようとする課題】上述した従来の技術に
おいては、同様のフォトリソグラフィ工程とイオン注入
工程を2回づつくり返す事により、それぞれ異なるシー
ト抵抗を有する2種類の抵抗素子を形成している為、工
程数が増加し、製造コストが高くなり、製造工期も長く
なるという問題があった。
In the above-mentioned prior art, the same photolithography step and ion implantation step are repeated twice to form two types of resistance elements having different sheet resistances. Therefore, there is a problem that the number of steps increases, the manufacturing cost increases, and the manufacturing period becomes longer.

【0007】本発明の目的は、2種類以上の異なるシー
ト抵抗を有する抵抗素子を形成するにあたり、別々の拡
散工程を設けずに同時に違ったシート抵抗を有する拡散
抵抗素子を形成できる半導体装置の製造方法を提供する
ことにある。
An object of the present invention is to manufacture a semiconductor device capable of simultaneously forming diffusion resistance elements having different sheet resistances without providing separate diffusion steps in forming resistance elements having two or more different sheet resistances. It is to provide a method.

【0008】[0008]

【課題を解決するための手段】本発明の半導体装置の製
造方法は、第1導電型の半導体基板に第2導電型の不純
物を導入し、前記半導体基板に2種類以上の異なるシー
ト抵抗を有する抵抗素子を形成する半導体装置の製造方
法において、前記半導体基板に前記不純物を選択的に導
入し抵抗素子領域を形成する工程と、CVD法を用いて
形成した膜で前記抵抗素子領域上を覆った抵抗素子領域
と前記CVD法を用いて形成した膜で前記抵抗素子領域
上を覆わない抵抗素子領域を形成する工程と、その後、
前記半導体基板を熱酸化する工程とを有して構成され
る。
According to a method of manufacturing a semiconductor device of the present invention, an impurity of a second conductivity type is introduced into a semiconductor substrate of a first conductivity type, and the semiconductor substrate has two or more different sheet resistances. In a method of manufacturing a semiconductor device for forming a resistance element, a step of selectively introducing the impurity into the semiconductor substrate to form a resistance element region, and covering the resistance element region with a film formed by a CVD method. Forming a resistive element region and a resistive element region that does not cover the resistive element region with a film formed using the CVD method;
Thermally oxidizing the semiconductor substrate.

【0009】[0009]

【実施例】次に本発明について、図面を参照して説明す
る。図1は本発明の一実施例を説明するために工程順に
示した半導体素子の断面図である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of a semiconductor device shown in the order of steps for explaining an embodiment of the present invention.

【0010】先ず、図1(a)に示すように、不純物濃
度が1014〜1016cm-3のN型半導体基板1の表面に
熱酸化により20〜50nmのシリコン酸化膜2aを形
成し、その後周知のフォトリソグラフィ技術により、第
1抵抗素子形成予定領域と第2抵抗素子形成予定領域を
開口するように、シリコン酸化膜2a上にフォトレジス
ト3aを形成し、続いてP型不純物であるホウ素を加速
エネルギー20keV〜50keV,ドーズ1012〜1
14cm-2でイオン注入し、第1抵抗素子領域4aと第
2抵抗素子領域4bを形成する。
[0010] First, as shown in FIG. 1 (a), a silicon oxide film 2a of 20~50nm by thermal oxidation on the impurity concentration is 10 14 ~10 16 cm -3 of N-type semiconductor substrate 1 of the surface, Thereafter, a photoresist 3a is formed on the silicon oxide film 2a by a well-known photolithography technique so as to open the first resistance element formation region and the second resistance element formation region, followed by boron as a P-type impurity. With acceleration energy of 20 keV to 50 keV and dose of 10 12 to 1
Ion implantation is performed at 0 14 cm -2 to form a first resistance element region 4a and a second resistance element region 4b.

【0011】次に減圧CVD法により、シリコン酸化膜
2a上に150〜1000nmの多結晶シリコン膜を成
長した後、図1(b)に示すように第1抵抗素子領域4
a上に多結晶シリコン膜5が残る様にパターニングす
る。このとき、第2抵抗素子領域4b上の多結晶シリコ
ン膜は除去される。
Next, after a polycrystalline silicon film having a thickness of 150 to 1000 nm is grown on the silicon oxide film 2a by the low pressure CVD method, as shown in FIG.
Patterning is performed so that the polycrystalline silicon film 5 remains on a. At this time, the polycrystalline silicon film on second resistance element region 4b is removed.

【0012】次に図1(c)に示すようにシリコン酸化
膜2aを除去した後に、図1(d)に示すように半導体
基板1および多結晶シリコン膜4の表面を熱酸化し、5
0〜100nmのシリコン酸化膜2bを形成する。この
とき、第1抵抗素子領域4a上にはシリコン酸化膜2a
と多結晶シリコン膜5がある為、第1抵抗素子領域4a
は熱酸化されないが、第2抵抗素子領域4b上にはそれ
らの膜が無い為、第2抵抗素子領域4b上には熱酸化さ
れ第2抵抗素子領域4b中にイオン注入したホウ素がシ
リコン酸化膜2b内に取り込まれ、第2抵抗素子領域4
bの不純物量が低下する。
Next, after removing the silicon oxide film 2a as shown in FIG. 1C, the surfaces of the semiconductor substrate 1 and the polycrystalline silicon film 4 are thermally oxidized as shown in FIG.
A 0-100 nm silicon oxide film 2b is formed. At this time, the silicon oxide film 2a is formed on the first resistance element region 4a.
And the polycrystalline silicon film 5, the first resistance element region 4a
Is not thermally oxidized, but since there is no such film on the second resistance element region 4b, boron is thermally oxidized on the second resistance element region 4b and boron ion-implanted into the second resistance element region 4b is a silicon oxide film. 2b, the second resistance element region 4
The amount of impurities of b decreases.

【0013】続いて、図1(e)に示すように900℃
〜1000℃の熱処理を行い、第1抵抗素子領域4aお
よび第2抵抗素子領域4bの不純物を活性化させる事に
より、ある所望のシート抵抗を有する抵抗素子が形成さ
れる。
Subsequently, as shown in FIG.
By performing a heat treatment at about 1000 ° C. to activate the impurities in the first resistance element region 4a and the second resistance element region 4b, a resistance element having a desired sheet resistance is formed.

【0014】こうして形成された抵抗素子は、第1抵抗
素子領域4aのシート抵抗が2KΩ/□程度にあるのに
対し、第2抵抗素子領域4bのシート抵抗は、シリコン
酸化膜2b内に取り込まれた分不純物濃度が低下した
為、約4.5KΩ/□程度となり、第1抵抗素子領域4
aのシート抵抗に比べ2倍以上の高い値になる。
In the resistance element thus formed, the sheet resistance of the first resistance element region 4a is about 2 KΩ / □, while the sheet resistance of the second resistance element region 4b is taken into the silicon oxide film 2b. Since the impurity concentration is reduced by the amount of about 4.5 KΩ / □, the first resistance element region 4
The value is more than twice as high as the sheet resistance a.

【0015】この場合、イオン注入するホウ素の量によ
り第1抵抗素子領域4aのシート抵抗を自由に変えるこ
とができ、熱酸化条件を変えることにより、第2抵抗素
子領域4bのシート抵抗も自由に変えることができる。
In this case, the sheet resistance of the first resistance element region 4a can be freely changed depending on the amount of boron to be ion-implanted, and the sheet resistance of the second resistance element region 4b can be freely changed by changing the thermal oxidation conditions. Can be changed.

【0016】尚、CVD法による膜は、多結晶シリコン
膜以外の窒化膜などの酸化されにくい膜であれば何でも
良い。
The film formed by the CVD method may be any film other than a polycrystalline silicon film, as long as the film is hardly oxidized such as a nitride film.

【0017】[0017]

【発明の効果】以上説明したように本発明は、抵抗素子
領域上に熱酸化を防ぐ膜がある抵抗素子領域と膜がない
抵抗素子領域を形成した後に、熱酸化を行う為、膜がな
い抵抗素子領域は熱酸化され、抵抗素子領域内の不純物
が熱酸化膜中に取り込まれる事により、不純物濃度が低
下し、シート抵抗が高くなる。従ってこの方法により、
1回のフォトリソグラフィ工程と1回のイオン注入工程
で、異なるシート抵抗を有する2種類の抵抗を同時に形
成することができ、工程数の削減ができるという結果を
有する。
As described above, according to the present invention, the thermal oxidation is performed after forming the resistive element region having the film for preventing thermal oxidation and the resistive element region having no film on the resistive element region. The resistance element region is thermally oxidized, and impurities in the resistance element region are taken into the thermal oxide film, so that the impurity concentration decreases and the sheet resistance increases. Therefore, by this method,
In one photolithography process and one ion implantation process, two types of resistors having different sheet resistances can be formed at the same time, and the number of processes can be reduced.

【0018】尚、本発明で用いる熱酸化を防ぐ膜は、通
常の半導体装置のゲート電極やエミッタ電極に用いられ
ているCVD膜を用いる事が可能であり、これらの膜を
使用する事により更に工程数を削減する事ができる。
As the film for preventing thermal oxidation used in the present invention, a CVD film used for a gate electrode or an emitter electrode of a normal semiconductor device can be used. The number of steps can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例を説明するために工程順に示
した半導体素子の断面図である。
FIG. 1 is a cross-sectional view of a semiconductor device shown in the order of steps for explaining one embodiment of the present invention.

【図2】従来技術の一例を説明するために工程順に示し
た半導体素子の断面図である。
FIG. 2 is a cross-sectional view of a semiconductor device shown in a process order for explaining an example of a conventional technique.

【符号の説明】 1 半導体基板 2a,2b シリコン酸化膜 3a,3b フォトレジスト 4a 第1抵抗素子領域 4b 第2抵抗素子領域 4c 第3抵抗素子領域 4d 第4抵抗素子領域 5 多結晶シリコン膜[Description of Signs] 1 Semiconductor substrate 2a, 2b Silicon oxide film 3a, 3b Photoresist 4a First resistance element area 4b Second resistance element area 4c Third resistance element area 4d Fourth resistance element area 5 Polycrystalline silicon film

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 第1導電型の半導体基板に第2導電型の
不純物を導入し、前記半導体基板に2種類以上の異なる
シート抵抗を有する抵抗素子を形成する半導体装置の製
造方法において、前記半導体基板に前記不純物を選択的
に導入し抵抗素子領域を形成する工程と、CVD法を用
いて形成した膜で前記抵抗素子領域上を覆った抵抗素子
領域と前記CVD法を用いて形成した膜で前記抵抗素子
領域上を覆わない他の抵抗素子領域とを形成する工程
と、その後前記半導体基板を熱酸化する工程とを有する
ことを特徴とする半導体装置の製造方法。
1. A method of manufacturing a semiconductor device, comprising: introducing a second conductivity type impurity into a first conductivity type semiconductor substrate to form resistance elements having two or more different sheet resistances on the semiconductor substrate. Forming a resistive element region by selectively introducing the impurity into a substrate; and forming a resistive element region covering the resistive element region with a film formed using a CVD method and a film formed using the CVD method. A method of manufacturing a semiconductor device, comprising: a step of forming another resistance element region that does not cover the resistance element region; and a step of thermally oxidizing the semiconductor substrate thereafter.
JP4344193A 1993-03-04 1993-03-04 Method for manufacturing semiconductor device Expired - Lifetime JP2919218B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4344193A JP2919218B2 (en) 1993-03-04 1993-03-04 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4344193A JP2919218B2 (en) 1993-03-04 1993-03-04 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH06260597A JPH06260597A (en) 1994-09-16
JP2919218B2 true JP2919218B2 (en) 1999-07-12

Family

ID=12663793

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4344193A Expired - Lifetime JP2919218B2 (en) 1993-03-04 1993-03-04 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2919218B2 (en)

Also Published As

Publication number Publication date
JPH06260597A (en) 1994-09-16

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