JPS6373550A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6373550A JPS6373550A JP21837686A JP21837686A JPS6373550A JP S6373550 A JPS6373550 A JP S6373550A JP 21837686 A JP21837686 A JP 21837686A JP 21837686 A JP21837686 A JP 21837686A JP S6373550 A JPS6373550 A JP S6373550A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- diffused
- polysilicon
- resistance
- temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000012535 impurity Substances 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 21
- 229920005591 polysilicon Polymers 0.000 abstract description 21
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052782 aluminium Inorganic materials 0.000 abstract description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 6
- 238000005468 ion implantation Methods 0.000 abstract description 6
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 6
- 239000011574 phosphorus Substances 0.000 abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 238000009792 diffusion process Methods 0.000 abstract description 3
- 230000000694 effects Effects 0.000 description 2
- 240000008881 Oenanthe javanica Species 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0802—Resistors only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に半導体抵抗を含む半導
体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device including a semiconductor resistor.
従来、この種の抵抗としては拡散抵抗、ポリシリコン抵
抗がある。Conventionally, this type of resistor includes a diffused resistor and a polysilicon resistor.
第３図は、拡散抵抗を示す縦断面図である。Ｐ型シリコ
ン基板１にイオン注入法にてＮ型不純物を導入し、Ｎ型
の拡散抵抗５ｔ−形成し、この抵抗の両端よｔ）ｐｓａ
からなる眉間絶縁膜３のコンタクト開口穴にてアルミ配
線６で接続する。FIG. 3 is a longitudinal cross-sectional view showing the diffused resistance. N-type impurities are introduced into a P-type silicon substrate 1 by ion implantation to form an N-type diffused resistor 5t, and both ends of this resistor are t) psa.
The aluminum wiring 6 is connected to the contact opening hole of the glabella insulating film 3 consisting of the above.
第４図はポリシリコン抵抗を示す縦断面図である。フィ
ールド酸化膜２０表面にポリシリコン層が成長され、イ
オン注入法にて所望の抵抗値のポリシリコン抵抗８に作
り込む。この抵抗の両端のコンタクト領域７は低抵抗で
あり、アルミ配線６とオーミック接続をとる。FIG. 4 is a longitudinal sectional view showing a polysilicon resistor. A polysilicon layer is grown on the surface of the field oxide film 20, and formed into a polysilicon resistor 8 having a desired resistance value by ion implantation. Contact regions 7 at both ends of this resistor have a low resistance and make an ohmic connection with the aluminum wiring 6.
上述し光従来の半導体装置における抵抗素子は温度依存
性があり、拡散抵抗で正の相関、ｔｅ、ポリシリコン抵
抗では負の相関がある。このため、低温（通常−２０℃
）あるいは高温（通常７０℃）にお埴て、常温からの抵
抗値変動が大きいという欠点がある。The resistance element in the conventional optical semiconductor device described above has temperature dependence, with a positive correlation for diffused resistance and a negative correlation for te and polysilicon resistance. For this reason, low temperatures (usually -20℃)
) or at high temperatures (usually 70°C), the resistance value fluctuates greatly from room temperature.
上述した従来の半導体装置に対し、本発明は正の温度係
数を持つ拡散抵抗と負の温度係数を持つ多結晶半導体抵
抗につφてそ詐ぞれの温に係数がシート抵抗に比例する
ことを利用し、拡散抵抗と多結晶半導体抵抗との温度変
化分を相殺することにより、この結合抵抗の温度変化を
少なくせしめる独創的内容を有する。In contrast to the conventional semiconductor device described above, the present invention has a diffusion resistance with a positive temperature coefficient and a polycrystalline semiconductor resistor with a negative temperature coefficient. It has an original content of reducing the temperature change of the combined resistance by canceling out the temperature change of the diffused resistance and the polycrystalline semiconductor resistance.
本発明の半導体装置は、半導体基板に第一の不純物を導
入してなる拡散抵抗と、前記半導体基板表面の結縁膜上
に形成さ１１、前記拡散抵抗に直列、並列または直並列
に接続され、第二の不純物を導入してなり、シート抵抗
値が前記拡散抵抗のシート抵抗値の１倍と５０倍との間
である多結晶半導体抵抗とを有している。The semiconductor device of the present invention includes a diffused resistor formed by introducing a first impurity into a semiconductor substrate, and a bonding film 11 formed on the surface of the semiconductor substrate, connected in series, in parallel, or in series-parallel to the diffused resistor, A polycrystalline semiconductor resistor is formed by introducing a second impurity and has a sheet resistance value between 1 and 50 times the sheet resistance value of the diffused resistor.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の縦断面図である。FIG. 1 is a longitudinal sectional view of one embodiment of the present invention.
拡散抵抗５とポリシリコン抵抗８をアルミ配線６で直列
に結合する。拡散抵抗５はリン（３１ｐ＋）のイオン注
入にて形成し、ポリシリコン抵抗８はＬＰ−ＣＶＤ
にて成長し、リン（Ｐ）のイオン注入にて形成する。拡
散抵抗５はＰ型シリーン基板１上に、また、ポリシリコ
ン抵抗８ｔｉフイールド酸化ＷＸｚ上に形放し、各抵抗
のアルミ配線６とのコンタクト領域４および７はリン拡
散にて高ａ［に形成する。A diffused resistor 5 and a polysilicon resistor 8 are coupled in series with an aluminum wiring 6. The diffused resistor 5 is formed by ion implantation of phosphorus (31p+), and the polysilicon resistor 8 is formed by LP-CVD.
It is grown by ion implantation of phosphorus (P). The diffused resistor 5 is formed on the P-type silicon substrate 1 and on the polysilicon resistor 8ti field oxide WXz, and the contact regions 4 and 7 with the aluminum wiring 6 of each resistor are formed to a high a[ by phosphorus diffusion. .
抵抗体の温度Ｔ （’０ ）における抵抗値１ｋＲ１［
Ω］、温！２５℃における抵抗値をＲ・ 〔Ω〕とし、
温度係数をα（１／”Ｏ）とすると％”１は一般に次式
で表わさ詐る。Resistance value 1kR1[ at temperature T ('0) of resistor
Ω], Warm! The resistance value at 25℃ is R・[Ω],
When the temperature coefficient is α(1/”O), %”1 is generally expressed by the following equation.
Ｒ１＝＝Ｒ，÷α（Ｔ−２５）Ｒ・
ここで、ポリシリコン抵抗の温度係数と拡散抵抗の温度
係数とｔ−絶対値で同じ値にし、また、２５℃における
そ牡ぞれの抵抗値も同じＲ′にすると、これら拡散抵抗
とポリシリコン抵抗との直列抵抗値Ｂ１１
Ｒ：２Ｒ’
とな）、温度に依存しない抵抗値が得られる。拡散抵抗
およびポリシリコン抵抗の温度係数は、第５図および第
６図にそれぞれ示す如くシート抵抗ρ３に依存し、ポリ
シリコン抵抗のｐｓが拡散抵抗のρ３の１倍から５０倍
でそれぞれの温度係数がほぼ等しくなる。R1==R, ÷α(T-25)R・Here, the temperature coefficient of the polysilicon resistance and the temperature coefficient of the diffused resistance are set to the same value in terms of t-absolute value, and the respective resistances at 25°C are If the value R' is also set to be the same, a series resistance value B11 R:2R' of these diffused resistors and the polysilicon resistor can be obtained, which is a resistance value that does not depend on temperature. The temperature coefficients of the diffused resistance and polysilicon resistance depend on the sheet resistance ρ3, as shown in FIGS. are almost equal.
第２図は、Ｍ１図に示す実施例における直列抵抗の温度
依存性を示すグラフでアク、拡散抵抗５とポリシリコン
抵抗８とのそれぞれの温度係数の絶対値が等しく、かつ
抵抗値が等しい場合の直列抵抗の温度依存性（曲線１１
）、および拡散抵抗５のρ３が５００Ω／口、ポリシリ
コン抵抗８のρ３が５００Ω／口であり、それぞれの抵
抗値が等し一場合の直列抵抗の温度依存性（曲線１２）
ｆｔそれぞれ示すものである。拡散抵抗５およびポリシ
リコン抵抗８単体の温度係数がそれぞれ１０００〜３０
００ｐｐｍ に対し直列抵抗では１１０００ｐＩ）
以内に抑えることができる。FIG. 2 is a graph showing the temperature dependence of the series resistance in the example shown in FIG. Temperature dependence of the series resistance of (curve 11
), and the temperature dependence of the series resistance when the ρ3 of the diffused resistor 5 is 500 Ω/unit, the ρ3 of the polysilicon resistor 8 is 500 Ω/unit, and the respective resistance values are equal (curve 12)
ft is shown respectively. The temperature coefficient of diffused resistor 5 and polysilicon resistor 8 alone is 1000 to 30, respectively.
00ppm vs. 11000pI for series resistance)
It can be kept within.
なお、拡散抵抗と多結晶半導体抵抗とを並列に接続した
り、拡散抵抗または多結晶半導体抵抗を２個以上用いて
これら３個以上の抵抗を直並列に接続することもでき、
これらの接続によ勺温度変化による抵抗直質動の少ない
抵抗を得ることができ、また所望の温度係数を有する抵
抗を得ることもできる。Note that a diffused resistor and a polycrystalline semiconductor resistor can be connected in parallel, or two or more diffused resistors or polycrystalline semiconductor resistors can be used and three or more resistors can be connected in series and parallel.
Through these connections, it is possible to obtain a resistance with little direct resistance variation due to temperature changes, and it is also possible to obtain a resistance having a desired temperature coefficient.
以上説明したように本発明は、拡散抵抗と多結係数の拡
散抵抗と負の温度係数の多結晶半導体抵抗との温度係数
の絶対ｆｉｔはぼ同じにすることにより、これを結合し
て温度変化の少ない抵抗を提供することができ、また、
抵抗を用いる回路の設計全行なう場合、温度変化による
抵抗値変動が少ないため、余裕のある設計ができるとい
う効果がある。As explained above, in the present invention, the absolute fit of the temperature coefficients of the diffused resistance, the diffused resistance with a multi-coupling coefficient, and the polycrystalline semiconductor resistor with a negative temperature coefficient are made to be approximately the same, so that they are combined and the temperature changes. can provide less resistance and also
When designing a circuit that uses resistors, there is little variation in resistance value due to temperature changes, so there is an effect that the design can be designed with a margin.
第１図は本発明の一実施例の縦断面圀、第２図は第１図
に示す実施例における直列抵抗の温度依４性を示すグラ
フ、第３図は拡散抵抗の縦断面図、第４図はポリシリコ
ン抵抗の縦断面図、第５図は拡散抵抗の温度依存性を示
すグラフ、第６図はポリシリコン抵抗の温度依存性を示
すグラブである。
１・・・・・・Ｐ型シリコン基板、２・山・・フィール
ド酸化膜、３・・・・・・層間絶縁膜、４・・・・・・
コンタクト領域、５・・・・・・拡散抵抗、６・・・・
・・アルミ配線、７・・・・・・コンタクト領域、８・
・・・・・ポリシリコン抵抗。
オ ／ｌ１ｆｆ
憂 ２ＷＪ
芹 ３ｖＪ
７：コンタフト４没（す’ Ｂ’−Ｆ・
１＞ツブシｘゴη−茅４凹
＄ ５ 男
増
一２ｏ θ ２５
７゜急度〔τ〕
募 乙 凹FIG. 1 is a longitudinal cross-sectional view of an embodiment of the present invention, FIG. 2 is a graph showing the temperature dependence of series resistance in the embodiment shown in FIG. 1, and FIG. 3 is a longitudinal cross-sectional view of a diffused resistance. FIG. 4 is a longitudinal cross-sectional view of a polysilicon resistor, FIG. 5 is a graph showing the temperature dependence of the diffused resistance, and FIG. 6 is a graph showing the temperature dependence of the polysilicon resistance. 1... P-type silicon substrate, 2... Mountain... field oxide film, 3... Interlayer insulating film, 4......
Contact region, 5...Diffused resistance, 6...
...Aluminum wiring, 7...Contact area, 8.
...Polysilicon resistor. O /l1ff Ui 2WJ Seri 3vJ 7: Contaft 4 death (Su'B'-F・
1> Tsubushi
7゜Steepness〔τ〕 Raised Otsu Concave
Claims (1)
抗に直列、並列または直並列に接続され、第二の不純物
を導入してなり、シート抵抗値が前記拡散抵抗のシート
抵抗値の１倍と５０倍との間である多結晶半導体抵抗と を有することを特徴とする半導体装置。[Scope of Claims] A diffused resistor formed by introducing a first impurity into a semiconductor substrate; 1. A semiconductor device comprising: a polycrystalline semiconductor resistor having a sheet resistance value between 1 and 50 times the sheet resistance value of the diffused resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21837686A JPS6373550A (en) | 1986-09-16 | 1986-09-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21837686A JPS6373550A (en) | 1986-09-16 | 1986-09-16 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6373550A true JPS6373550A (en) | 1988-04-04 |
Family
ID=16718925
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21837686A Pending JPS6373550A (en) | 1986-09-16 | 1986-09-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6373550A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5448103A (en) * | 1992-05-19 | 1995-09-05 | Texas Instruments Incorporated | Temperature independent resistor |
| JP2006203209A (en) * | 2005-01-22 | 2006-08-03 | Samsung Electronics Co Ltd | Resistance element having uniform resistance value, and semiconductor element using the same |
| JP2018037528A (en) * | 2016-08-31 | 2018-03-08 | キヤノン株式会社 | Semiconductor device, substrate for liquid discharge head, liquid discharge head, and liquid discharge device |
-
1986
- 1986-09-16 JP JP21837686A patent/JPS6373550A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5448103A (en) * | 1992-05-19 | 1995-09-05 | Texas Instruments Incorporated | Temperature independent resistor |
| JP2006203209A (en) * | 2005-01-22 | 2006-08-03 | Samsung Electronics Co Ltd | Resistance element having uniform resistance value, and semiconductor element using the same |
| JP2018037528A (en) * | 2016-08-31 | 2018-03-08 | キヤノン株式会社 | Semiconductor device, substrate for liquid discharge head, liquid discharge head, and liquid discharge device |
| CN107799154A (en) * | 2016-08-31 | 2018-03-13 | 佳能株式会社 | Semiconductor device, liquid-discharge-head substrate, liquid discharging head and device |
| CN107799154B (en) * | 2016-08-31 | 2021-12-10 | 佳能株式会社 | Semiconductor device, liquid discharge head substrate, liquid discharge head, and device |
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