JPH0360068A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To enable the production of a required high resistance even when a memory cell of a BiCMOSSRAM is micronized by providing a polycrystalline silicon film for restraining the diffusion of impurities in a connection part of a gate electrode of a driving MOSFET with a high-resistance load element. CONSTITUTION:In a connection part 8 of a gate 5 of driving MOSFET with a high-resistance element 10 consisting of a polycrystalline silicon film not including impurities, a polycrystalline silicon layer 9 is arranged which restrains the impurities (phosphorus) doped in the gate electrode 5 from diffusing toward the side of a high-resistance element by a heat treatment during a manufacturing process. This process can be effected very easily without an increasing number of PR processes. Accordingly, an area of an SRAM cell can be made a half of a conventional one or less. Also in a bipolar CMOSSRAM, the high-resistance element and an emitter electrode of a bipolar transistor can be formed by using the same polycrystalline silicon as in a conventional method and the reduction of an area of a memory cell becomes possible.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to semiconductor integrated circuit devices, and in particular to bipolar CMO5 equipped with static random access memory.
It is installed between a circuit device (hereinafter referred to as BiCMO5SRAM).

[Prior art and problems to be solved by the invention] SR
The AM memory cell is composed of a flip-flop circuit composed of two sets of high-resistance load elements and a driving MO5FET, and a pair of transfer MO5FETs each connected to a pair of input/output terminals of the flip-flop circuit. In order to reduce the memory cell area and achieve high integration, the high-resistance load element has a voltage of s1! It is composed of a second layer polycrystalline silicon film formed integrally with the pressure wiring, for example, by CVD. This resistance element is disposed on an interlayer insulating film covering the gate electrode of the driving MO5FET, and has a high resistance of about 10 to 100 gigaohms.

The polycrystalline silicon film used as this high resistance load element is formed without introducing n-type impurities (As, P) for reducing the resistance value so as to have high resistance. On the other hand, the polycrystalline silicon film used as the power supply voltage wiring is constructed by introducing the impurity described above.

However, as the length of the resistor element becomes shorter with the miniaturization of the constituent elements, there is a problem in that it becomes difficult to obtain a predetermined high resistance value. In other words, one end of the high-resistance load element is connected to the gate electrode of the driving MO5FET, and as the impurity (phosphorus) introduced into this gate electrode is miniaturized, it diffuses into the high-resistance element during heat treatment during the manufacturing process. do. Furthermore, since the other end of the resistance element is connected to the power supply wiring, impurities (As, P) introduced into the power supply wiring similarly diffuse into the high resistance element portion. still,
The amount of impurities diffused is larger in the former case.

It has been confirmed that the impurity diffusion coefficient in a polycrystalline silicon film is about 10 times higher than that in a single crystal.

For this reason, when the length of the resistance element becomes about 4 μm or less, the resistance value decreases rapidly.

One way to solve this problem is to use 5IPOS (Semi nsula), which has a small impurity diffusion coefficient in the film.
Although it is conceivable to use a high resistance element and a bipolar transistor emitter electrode, it is possible to use a BiC film as a resistance element.
This method cannot be applied to MO5SRAM because the diffusion of emitter impurities is also suppressed at the same time.

Therefore, the purpose of the present invention is to solve the above problems and
It is an object of the present invention to provide a technology that can generate the necessary high resistance even when the memory cells of O5 SRAM are miniaturized.

[Differences between the invention and the prior art] In contrast to the above-mentioned SRAM memory cell using the conventional high resistance load element, the present invention suppresses impurity diffusion in the connection between the gate electrode of the driving MO5FET and the high resistance load element. The difference is that a polycrystalline silicon film is provided.

[Means for Solving the Problems] The gist of the present invention is that one end is connected to a high impurity concentration power supply wiring and the other end is connected to a low impurity concentration high In a semiconductor memory device having a resistive load element and in which a memory circuit is configured by the high resistive load element and the field effect transistor, at least one of both ends of the high resistive load element is made of polycrystalline silicon that suppresses diffusion of impurities. It is connected to the power supply wiring or the high impurity concentration layer through the layer.

[Function of the Invention] In the semiconductor memory device having the above configuration, even if the high resistance load element and the power supply wiring or the high impurity concentration layer are exposed to high temperature during manufacturing, the diffusion of impurities to the high resistance load element is prevented. Suppressed by polycrystalline silicon layer.

[Example] Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a longitudinal sectional view showing an SRAM cell according to a first embodiment of the present invention. 4 is the gate electrode of MO3FET for delivery, 5
is the gate electrode of the driving MO5FET. MO for driving
The impurity (phosphorus) introduced into the gate electrode 5 is transferred to the connection part 8 between the gate 5 of the 5FET and the high-resistance element 10 formed of a polycrystalline silicon film containing no impurities to the high-resistance element side through heat treatment during manufacturing. A polycrystalline silicon layer 9 is provided to suppress the diffusion caused by. 5ipos (S em
i Upper insulating PolySilico
n) can be used. Impurity diffusion in the 5IPO8 film is affected by the N20 gas flow rate during film formation. FIG. 5 shows the relationship between the diffusion length of phosphorus in S I PO5 and the flow rate of N20 gas. As shown in the figure, the flow rate of N20 during film formation was
If it is 0SCCM or more, the diffusion length of phosphorus in polycrystalline silicon formed by the conventional method (if N20 is not included) is 1
/4 or less.

Next, the manufacturing method of this example will be explained using FIGS. 4(a) and 4(b). As shown in FIG. 4(a), after sequentially forming the gate 5 of the drive MOSFET, the gate 4 of the transfer MO5FET, and the source/drain electrodes 6 on the P-type substrate 1, the high resistance element and the gate of the drive MO5FET are formed. 5 is formed. Next, a 5IPO5 film 9 is grown over the entire surface. The growth conditions are LPCVD method, for example, SiH4 flow rate 400-300 SCCM, N20 flow f130-40
SCCM, N2 flow rate 500 SCCM, growth temperature 60
The film grows to a thickness of 2000 to 4000A at 0°C. Next, as shown in FIG. 4(b), the entire surface is covered with CF4. Etching back is performed by dry etching using an etching gas such as SF6, leaving the 5IPOS film 9 only within the connection window 8.

This elevation can be done extremely easily without increasing the number of PR steps. Next, a high resistance element 10 is formed from polycrystalline silicon into which no impurities have been introduced.

This polycrystalline silicon is bipolar CMO5SR as before.
The emitter electrode can be shared with the high resistance element of the AM memory cell.

FIG. 2 is a longitudinal sectional view of a second embodiment of the invention.

4 is the gate electrode of MO9FET for transfer, 5 is MO for drive
This is the gate electrode of 5FET. A 5IPO3 film 9 for suppressing impurity diffusion is provided at both the connection part 8 between the drive MO5FET gate 5 and the high resistance element 10 formed of a polycrystalline silicon film containing no impurities, and the connection part 8' with the power supply wiring 14. It is being

In this embodiment, since the s r pos film 9 is provided at both ends of the high resistance element 100, the resistance length can be made shorter than in the first embodiment, and furthermore, it is possible to downsize the SRAM cell.

[Effects of the Invention] As explained above, the present invention provides a polycrystalline silicon film that suppresses the diffusion of impurities at the connection portion between the gate electrode of the driving MO3FET and the high resistance element without increasing the PR process. The area of the SRAM cell can be reduced to 1/2 or less of the conventional size. Furthermore, even in a bipolar CMOSSRAM, the high resistance element and the emitter electrode of the bipolar transistor can be formed using the same polycrystalline silicon as in the past, and the memory cell area can be reduced.

[Brief explanation of drawings]

FIG. 1 is a longitudinal cross-sectional view showing a first embodiment of the present invention, FIG. 2 is a longitudinal cross-sectional view showing a second embodiment of the present invention, FIG. 3 is a plan view of the second embodiment, and FIG. a) and (b) are cross-sectional views showing the manufacturing method of the first embodiment, and FIG. 5 is a graph showing the diffusion of impurities in 5IPOS. 1. . ◆ ・ ◆ 11 ・ ・ ・ ◆ 7, 12. 1 13 ・ ・ ◆ ・ 14 ・ ◆ ・ ・ 16 ・ ・ ・ ・ P-type substrate, ... field oxide film, ... gate oxide film, ... transfer MOSFET gate electrode, ... drive MO5FET gate electrode,・・n9 source/drain, ・・gate-high resistance element connection window, ◆◆5IPO5゜・・high resistance polycrystalline silicon film, ・・polycrystalline silicon power supply wiring section, 5・・interlayer insulating film, ・・...Extractor electrode, ...Power supply (V CC) wiring, ...Direct contact window, 17. Ground wiring, 18° contact window.

Claims (1)

[Scope of Claims] A high resistance load element with a low impurity concentration, one end of which is connected to a power supply wiring with a high impurity concentration and the other end connected to a high impurity concentration layer of a field effect transistor, the high resistance load element In a semiconductor memory device in which a memory circuit is constituted by a field effect transistor and a field effect transistor, at least one of both ends of the high resistance load element is connected to the power supply wiring or the high impurity concentration via a polycrystalline silicon layer that suppresses diffusion of impurities. A semiconductor memory device characterized in that the semiconductor memory device is connected to layers.