JPS62147759A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To sufficiently lower the lateral diffusion of conductive impurity in the polysilicon and make small fluctuation due to small size and high yield by including one element among oxygen, nitrogen and carbon into the entire part of polysilicon. CONSTITUTION:An insulation film 2 is deposited on a semiconductor substrate 1, the polysilicon layer 3 is futher deposited and it is etched like islands. Next, the oxygen ion 4, for example, is introduced into the polysilicon 3 by the ion implantation method, a gate insulation film 5 is formed, an electrode 9 is then formed, and the conductive impurity ion 8 is introduced by the ion implantation method to form a diffused layer 6 which becomes the source and drain. An insulation film 10 is then deposited and the heat processing is carried out. In this case, the lateral diffusion of conductive impurity is suppressed in the diffusion layer 6 due to existence of oxygen and the diffusion layer 6 is not connected even when the gate electrode 9 has the width of 2mum or less. Thereafter, a contact hole is formed on the insulation film 10, the Al electrode 11 is then formed, thus completing small size polysilicon MOS transistor element.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method of manufacturing a semiconductor device, and in particular, to a method of manufacturing a semiconductor device using polysilicon, which is suitable for miniaturizing element dimensions, increasing yield, and reducing variation. The present invention relates to a method for manufacturing a MOS transistor element.

[Conventional technology]

Regarding conventional semiconductor devices, especially MOS transistors formed using polysilicon, see IE, Transactions on Electron, Devices, E.D. 32, No. 2 (1985).
Pages 258 to 281 (IEEE, Trans,
on Electron Device E D −
32.

Nα2 (1985) p, 258-281). That is, in order to improve the degree of integration of a semi-quartet integrated circuit and to measure electrical isolation.

A structure in which a polysilicon MOS transistor element is stacked on an insulating film formed on a single crystal semiconductor substrate or on a transistor element is used. The source and drain regions of a polysilicon MOS transistor element are formed using conductive impurities (for NHO2, phosphorus, arsenic, antimony, etc.) in polysilicon.

r'MO5 is formed by introducing boron, aluminum, gallium, etc.).

[Problem that the invention seeks to solve]

The above conventional technology does not take into account the fact that conductive impurities diffuse very quickly through grain boundaries in polysilicon, and because the diffusion is fast, heat treatment causes large lateral diffusion, so conductive impurities are introduced. If the spacing between the regions is narrow, the source region and drain region will be connected, resulting in the problem that it is impossible to form a polysilicon MO8)-transistor element with a minute gate length of about 2 μm or less.

An object of the present invention is to sufficiently reduce lateral diffusion of conductive impurities in polysilicon, and to provide a method for manufacturing a semiconductor device suitable for forming polysilicon MOS transistor elements with fine dimensions, high yield, and small variations. Our goal is to provide the following.

[Means for solving problems]

The above purpose is to inject oxygen and nitrogen throughout the polysilicon layer.

This is achieved by containing at least one element of carbon. Preferably here.

In order not to increase the threshold voltage, the element is contained at a low concentration near the polysilicon-insulating film interface where the channel of the polysilicon MOS transistor element is formed, and at a higher concentration in other regions. . Also preferably oxygen and nitrogen.

The concentration of at least one element of carbon is 101f
It is set in the range of l to 10z2 pieces/d.

[Effect]

By introducing at least one element among oxygen, nitrogen, and carbon into the entire polysilicon layer, the physical properties of polysilicon change. In particular, when silicon oxide, silicon nitride, or silicon carbide is partially formed at the grain boundaries of polysilicon, the physical properties of the grain boundaries change, acting to suppress impurity diffusion through the grain boundaries. .

As a result, lateral diffusion in polysilicon is reduced, so that polysilicon MOS transistor elements with fine dimensions can be formed. Furthermore, since the diffusion rate is low, variations are small and the yield is high.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention.

First, as shown in FIG. 1(a), an insulating film 2 is deposited on a semiconductor substrate or a semiconductor element 1, and then a polysilicon layer 3 is deposited using, for example, a low pressure CVD method. The polysilicon layer 3 is etched into an island shape using a normal photoetching method to form an element formation region. Next, for example, oxygen ions 4 are introduced (contained) into the polysilicon 3 using an ion implantation method. Here, the ion implantation of oxygen ions 4 may be performed before etching the polysilicon 3. The implantation conditions are set such that oxygen is introduced into the entire polysilicon layer 3 in consideration of the thickness of the polysilicon layer 3. The introduced oxygen concentration is preferably 1
It is set within the range of 018 to 1022 pieces/d. Also,
Preferably a channel forming region, that is, a polysilicon layer 3
The oxygen concentration near the top surface is low, for example 1020/-
Set as below. This prevents the threshold voltage from increasing due to the introduction of oxygen. Next, as shown in FIG. 1(b), a gate insulating film 5 is formed by thermal oxidation or insulating film deposition. Next, as shown in FIG. 1(c), a gate electrode 9 of a polysilicon MOS transistor element is formed, conductive impurity ions 8 are introduced using an ion implantation method, and diffusion layers that will become source and drain regions are formed. form 6. Next, as shown in FIG. 1(d), an insulating film 10 is deposited and heat treated. At this time, the lateral diffusion of conductive impurities in the diffusion layer 6 is suppressed by the presence of oxygen, and even if the width of the gate electrode 9 is 2 μm or less (for example, 0.8 μm), the diffusion layer 6 is not connected. , conductive impurities are not diffused throughout the channel region 7. Next, as shown in FIG. 1 (θ), a contact hole is formed in the insulating film 10, and, for example, an A11l electrode 11 is formed to form a polysilicon MOS transistor element with minute dimensions.

In the above, oxygen may be introduced using a method of incorporating oxygen during the deposition of polysilicon. Furthermore, the inventors have discovered that similar impurity diffusion suppression occurs not only by the introduction of oxygen but also by the introduction of nitrogen or carbon.

FIG. 2 shows a CMO with a laminated structure as another embodiment of the present invention.
3J child is shown. That is, an N-type diffusion layer 12 and a gate electrode 9 are formed on a semiconductor substrate 1 to form an N-channel MOS transistor element, and then, for example, oxygen is deposited within a concentration range of 1019 to 1022 atoms/d. A P-type impurity is introduced into the diffusion layer 6 of the polysilicon MO5)-transistor element, which forms the polysilicon MOS transistor element, and the gate electrode 9 is made of polysilicon, which is common to the N-channel MOS transistor. A silicon P-channel MOS transistor element is formed. Preferably, the oxygen concentration near the bottom surface of the polysilicon layer is set low. Drain of N-channel MOS transistor element and polysilicon P-channel MOS
The sources of the transistor elements are connected. As a result, a CMO5 element with a fiv layer structure is formed.

FIG. 3 shows a circuit diagram of a static operation type flip-flop memory cell formed by the CMO5 elements shown in FIG. 2. Namely.

Trl, Tr2. Tr5. Tr6 is an N-channel MOS transistor, Tr3. Tr4 is a polysilicon P-channel MOS transistor.

Tr5. Tr6 is a transfer MOS transistor, and according to the potential change of the word line W, the bit line Dxt
Da and the memory cell are passed through four times. Tr3゜Tr4 is the second
As shown in the figure, they are stacked on top of Trl and Tr2, and serve as loads MO8 for Tri and Tr2, respectively, forming a current path from the power supply terminal Vcc to Vss to form two stable states. It has a circuit structure. Here, polysilicon PMO8) - transistor Tr3. Tr
For example, since Tr3.4 contains oxygen, Tr3. Tr4
The dimensions of Tr and Tr2 can be made as fine as those of Tri and Tr2. This enables high integration of memory cells.

In addition, PNP and NPN are used as MOS transistors.

The present invention can be applied to structures of N+NN+ and P+PP÷, and impurity introduction can be performed using various known introduction methods such as ion implantation or diffusion method.

〔Effect of the invention〕

As described above, according to the present invention, since the lateral diffusion of impurities in polysilicon is suppressed, it is possible to form a polysilicon MOS transistor element with fine dimensions and high yield (small variation).

[Brief explanation of drawings]

1(a) to (e) are cross-sectional structural diagrams showing one embodiment of the process of forming a polysilicon MO3 element to which the present invention is applied, and FIG. 2 is a diagram showing another embodiment of the present invention. P
CMO formed by stacking channel MOS transistors
A cross-sectional structural diagram of three elements, and FIG. 3 is a circuit diagram of a flip-flop memory cell using three CMO elements. 1... Semiconductor substrate, 2... Insulating film, 3... Polysilicon. 4... At least one element ion of oxygen, nitrogen, and carbon, 5... Gate insulating film, 6... Diffusion layer, 7
... Channel region, 8 ... Conductive impurity ion, 9
...Gate electrode, 10...Insulator, 11...Al
t, 12-N type impurity diffusion layer・
1. −． 1. Agent: Patent attorney Katsuo Ogawa (Par°) 2. -1 spear? Illustration 3 b

Claims (1)

[Claims] 1. A method for manufacturing a semiconductor device in which a MOS transistor element is formed in a polysilicon layer on a semiconductor substrate, wherein the entire polysilicon layer contains at least one element among oxygen, nitrogen, and carbon. 1. A method for manufacturing a semiconductor device, which comprises: forming a MOS transistor element by introducing impurities. 2. The MOS transistor element of the polysilicon layer has a common gate electrode with the MOS transistor element formed on the semiconductor substrate, and the MOS transistor element formed on the semiconductor substrate has a common gate electrode.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is formed by stacking the semiconductor device on an OS transistor element with an insulating film interposed therebetween. 3. At least one element among oxygen, nitrogen, and carbon is contained at a low concentration near the polysilicon-insulating film interface where the channel of the MOS transistor element in the polysilicon layer is formed, and in the other polysilicon layers. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the layer contains the compound at a high concentration. 4. At least one element among oxygen, nitrogen, and carbon is 10^1^9 pieces/cm^3 to 10^2^2 pieces/cm
3. The method of manufacturing a semiconductor device according to claim 1, wherein the concentration is ^3. 5. A method for manufacturing a semiconductor device, wherein the polysilicon layer is provided on a semiconductor substrate with an insulating film interposed therebetween.