JPH05283650A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent lowering of impurity concentration in a first conductivity electrode layer by doping the first conductivity electrode layer with first conductivity impurities through a contact hole. CONSTITUTION:A gate electrode layer 18a of a TFT is connected to a gate electrode layer 8a at the side of a substrate through a contact hole 14. In the process, P-type impurities contained in the gate electrode layer 18a are diffused to a gate electrode layer 8a at the side of the substrate; however, concentration of N-type impurities is raised in advance in a part of the gate electrode layer 8a which is relevant to the contact hole 14. Therefore, a concentration of N-type impurities in the gate electrode layer 8a is not lowered more than required. Furthermore, P-type impurities are not diffused as far as an N<+> diffusion region 10a through the gate electrode layer 8a and a concentration of N<+> impurities at the part is not lowered.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a semiconductor substrate having a first conductivity type transistor of one polarity formed on the surface thereof and having a polarity opposite to the first conductivity type. When forming a two-conductivity type thin film transistor,
The present invention relates to a method for manufacturing a semiconductor device that prevents adverse effects on a first conductivity type transistor.

[0002]

2. Description of the Related Art In a semiconductor device such as an SRAM, a thin film transistor (TFT) is used as a load transistor due to a demand for high integration. SR
In the AM, a driving transistor and a selecting transistor are formed on the surface of a semiconductor substrate, and a thin film such as a semiconductor layer is formed on the driving transistor and the selecting transistor to form a TFT serving as a load transistor.

Generally, in an SRAM, a driving transistor and a selecting transistor are N type transistors, and a TFT serving as a load transistor is a P type transistor. It is known that with such a configuration, the retention characteristic and the soft error resistance are improved and the standby current becomes low.

[0004]

However, in the process of manufacturing such an SRAM, the gate electrode layer of the TFT forming the load transistor is contacted with the gate electrode layer of the driving transistor located on the lower layer side. It is necessary to connect through a hole, and it has been found that the following problems arise at that time. That is, the gate electrode layer of the TFT is doped with P-type impurities such as boron, and the gate electrode layer of the driving transistor is doped with N-type impurities such as phosphorus. The P-type impurities contained in the electrode layer are
There is a risk of diffusion to the gate electrode layer of the driving transistor, lowering the N ⁺ concentration of the gate electrode layer of the driving transistor, and raising the threshold voltage Vth of the driving transistor. Further, since the gate electrode layer of the driving transistor is connected to the N ⁺ diffusion layer which is the source / drain region formed in the semiconductor substrate through the contact hole, the P-type impurity diffused in the gate electrode layer is formed. Diffuses to the N ⁺ diffusion layer formed on the semiconductor substrate,
There are problems that the junction leak of the N ⁺ diffusion layer increases, the number of junction capacitors decreases, and the contact resistance between the gate electrode layer of the driving transistor and the N ⁺ diffusion layer increases.

The present invention has been made in view of the above circumstances, and has a polarity opposite to that of the first conductivity type on the surface of a semiconductor substrate on which a first conductivity type transistor of one polarity is formed, such as SRAM. An object of the present invention is to provide a method for manufacturing a semiconductor device capable of forming a thin film transistor on an upper layer side without adversely affecting a transistor located on a lower layer side when forming the second conductivity type thin film transistor of And

[0006]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises: a first conductivity type electrode layer forming a part of a first conductivity type transistor;
When the insulating layer is laminated and the second conductive type electrode layer forming a part of the second conductive type thin film transistor is connected to the first conductive type electrode layer through the contact hole formed in the insulating layer. , Through the contact hole in the insulation layer
The conductive type electrode layer is doped with the first conductive type impurity, and then the second conductive type electrode layer is laminated on the insulating layer so as to enter the contact hole. The amount of impurities of the first conductivity type doped through the contact hole is preferably equal to or more than the amount of impurities doped in the electrode layer of the second conductivity type.

[0007]

According to the method of manufacturing a semiconductor device of the present invention, before the second-conductivity-type electrode layer is laminated, the first-conductivity-type electrode is passed through the contact hole which is a portion to which the second-conductivity-type electrode layer is connected. Since the layer is doped with impurities of the first conductivity type, the concentration of the impurities of the first conductivity type in that portion can be increased. Therefore, after that, the second conductivity type electrode layer is
When the second conductivity type electrode layer is laminated on the insulating layer so as to be connected to the first conductivity type electrode layer through the contact hole, the second conductivity type impurities contained in the second conductivity type electrode layer are of the first conductivity type. Even if diffused into the electrode layer, the concentration of the first conductivity type impurity is increased in that portion, so that the concentration of the first conductivity type impurity is lowered more than necessary by the diffusion of the second conductivity type impurity. Disappears. It is possible to increase the concentration of the first conductivity type impurity in advance with respect to the entire lower first conductivity type electrode layer. In that case, in this case, the polysilicon film or polycide forming the electrode layer is formed. The grain growth of the film proceeds too much and the surface tends to be rough, which is not preferable.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device manufacturing method according to an embodiment of the present invention will be described in detail below with reference to the drawings.
1 to 5 are schematic cross-sectional views of a main part showing a manufacturing process of an SRAM according to an embodiment of the present invention, and FIG. 6 is an equivalent circuit diagram showing a memory cell of the SRAM.

1 to 6 show an example in which the method of the present invention is applied to an SRAM manufacturing method. Before describing in detail a method of manufacturing an SRAM according to an embodiment of the present invention, an equivalent circuit diagram of a memory cell using a TFT as a load transistor will be briefly described with reference to FIG. As shown in the figure, an SRAM memory cell using a TFT as a load transistor includes a pair of driving transistors Q1 and Q2 forming a flip-flop circuit, selection transistors Q3 and Q4 for selecting a memory cell, and a load transistor. It has Q5 and Q6. Selection transistors Q3, Q4
Turns on the transistor according to the gate voltage generated on the word line W, and transmits the information stored in the flip-flop circuit composed of the driving transistors Q1 and Q2 to the bit line b and the inverted bit line b '. It is supposed to do.

In this embodiment, in order to manufacture an SRAM having the memory cell shown in the equivalent circuit diagram, first, as shown in FIG. 1, a P well, which is a P type impurity diffusion region, is formed on the surface of a semiconductor substrate. Region 2 is formed, and field insulating layer 4 and gate insulating layer 6 are formed on the surface of P well region 2. Gate electrode layers 8a and 8b are formed on the surface of the gate insulating layer 6. The field insulating layer 4 and the gate insulating layer 6 are formed, for example, by thermally oxidizing the surface of the semiconductor substrate, and are made of SiO ₂ or the like. The thickness of field insulating layer 4 is not particularly limited, but is about 950 nm, for example. The oxidation temperature for forming the field insulating layer is not particularly limited, but is about 1000 ° C., for example. The thickness of the gate insulating layer 6 is not particularly limited, but is about 40 nm, for example.
The gate electrode layers 8a and 8b are composed of, for example, a polysilicon film formed by a CVD method or a polycide film having a laminated structure of silicide and polysilicon. When forming the gate electrode layers 8a and 8b, the ground electrode layer 8c is also formed of the same material at the same time.

On the surface of the P well region 2, N ⁺ diffusion layers 10a, 10b and 10c of N type impurities are self-aligned with the gate electrode layers 8a and 8b and the ground electrode layer 8c by an ion implantation method or the like. Formed. Gate electrode layer 8
a ⁺ 8b ⁺ 8c and N ⁺ to be the source / drain regions
The diffusion layers 10a, 10b, 10c are the SRAM shown in FIG.
A pair of driving transistors Q1 and Q2 in the equivalent circuit of the memory cell for selection and a selection transistor Q3 for selection.
Q4 is formed in a pattern such that it is formed on the surface of the P well region 2. As a result, the driving transistor Q1
, Q2 and the selection transistors Q3 and Q4 are N type M
It is composed of an OS transistor. The electrode layers 8a, 8b, 8c made of a polysilicon layer are doped with N-type impurities such as phosphorus (Phos) in order to increase the conductivity thereof.

Next, in this embodiment, as shown in FIG. 2, an interlayer insulating layer 12 is formed on the surface of the semiconductor substrate on which the electrode layers 8a, 8b and 8c are formed. The interlayer insulating layer 12 is not particularly limited, but is composed of, for example, a silicon oxide layer formed by a CVD method. This interlayer insulating layer 1
2, a contact hole 14 facing a specific gate electrode layer 8a is formed by a photolithography method or the like. Figure 6
As shown in FIG. 5, in the SRAM memory cell, the gate electrode layers of the driving transistors Q1 and Q2 formed on the surface of the semiconductor substrate are connected to the gate electrode layers of the load transistors Q5 and Q6 formed of TFTs. It is necessary to do so. Further, the specific gate electrode layer 8a is connected to the specific N ⁺ diffusion layer 10a. This is because, as shown in FIG. 6, the gate electrode layers of the driving transistors Q1 and Q2 need to be connected to the source / drain regions of the selecting transistors Q3 and Q4.

After the contact hole 14 is formed in the interlayer insulating layer 12, an impurity of the same conductivity type as that of the gate electrode layer 8a is doped through the contact hole 14 by the ion implantation method. In the case of this embodiment, since the gate electrode layer 8a is of N-type conductivity, impurities such as Phos ⁺ are doped into the gate electrode layer 8a through the contact holes. At that time, it is preferable to cover the surface of the interlayer insulating layer 12 other than the contact holes 14 with the resist film 16. The dose amount of the impurity doped through the contact hole 14 is not particularly limited, but the opposite conductivity type (the present embodiment) that is doped to the gate electrode layers 18 a and 18 b of the TFT stacked on the interlayer insulating layer 12. In the case of the example, the amount is preferably about the same as the amount of P-type impurities. Specifically, for example, the dose amount is 1 ×
It is on the order of 10 ¹⁵ cm ^-2 .

By performing such ion implantation, the portion of the specific gate electrode layer 8a corresponding to the contact hole 14 has a higher N-type impurity concentration than the other portions.

In this embodiment, next, as shown in FIG.
The gate electrode layer 18 of the TFT is formed on the surface of the interlayer insulating layer 12.
a and 18b are formed in a predetermined pattern so as to form the load transistors Q5 and Q6 of the SRAM memory cell shown in FIG. The gate electrode layers 18a and 18b are not particularly limited, but are composed of, for example, a polysilicon film formed by a CVD method. The film thickness of the interlayer insulating layer 12 is, for example, about 50 to 100 nm. The film thickness of the polysilicon film forming the gate electrode layer is, for example, about 40 nm. In this embodiment, since the TFT serving as a load transistor is composed of a P-type MOS transistor, the gate electrode layer 18 composed of a polysilicon film is used.
A and 18b are doped with P-type impurities. This T
The specific gate electrode layer 18a forming the FT is connected to the gate electrode layer 8a on the substrate side located on the lower layer side through the contact hole 14. As shown in FIG.
This is because the gate electrode layers of the load transistors Q5 and Q6 composed of TFTs need to be connected to the gate electrode layers of the driving transistors Q1 and Q2.

As shown in FIG. 3, when the gate electrode layer 18a of the TFT is connected to the gate electrode layer 8a on the substrate side through the contact hole 14, the gate electrode layer 1
The P-type impurity contained in 8a diffuses into the gate electrode layer 8a on the substrate side. However, in the portion of the gate electrode layer 8a corresponding to the contact hole, N-type impurities are previously formed in the step shown in FIG. Since the type impurity concentration is increased, the N type impurity concentration in the gate electrode layer 8a is not lowered more than necessary. Further, the P-type impurity does not diffuse through the gate electrode layer 8a to the N ⁺ diffusion region 10a, and the N ⁺ impurity concentration in that portion is not lowered.

In the present embodiment, next, as shown in FIG.
The gate insulating layer 2 is formed on the surfaces of the gate electrode layers 18a and 18b.
0 is deposited. Although not particularly limited, the gate insulating layer 20 is composed of a silicon oxide film formed by the LP-CVD method, an ONO film (SiO ₂ / SiN / SiO ₂ ), or the like. The film thickness is not particularly limited, but is 2
It is about 5 mm.

On the surface of the gate insulating layer 20, a semiconductor layer 22 in which a channel region and source / drain regions of the TFT are formed is formed in a predetermined pattern. The semiconductor layer 22 is composed of, for example, a polysilicon film (for example, having a thickness of about 40 mm) formed by the LP-CVD method. When the semiconductor layer 22 is formed of a polysilicon film, the power supply line Vdd is simultaneously formed of the same material. In order to form a source / drain region and a channel region with respect to the semiconductor layer 22 made of a polysilicon film, a portion of the semiconductor layer 22 corresponding to the channel region is masked with a resist film 24 to form a source / drain region. Ion implantation is performed. Impurity species used for ion implantation are P-type MOS
To obtain a TFT, a P-type impurity such as BF ₂ is used.

After forming the source / drain regions for the semiconductor layer 22, as shown in FIG.
An interlayer insulating layer 26 is formed on the surface of, and a contact hole facing the N ⁺ diffusion layer 10b is formed in the interlayer insulating layer 26. Next, a plug 28 made of a refractory metal such as tungsten is formed on the surface of the interlayer insulating layer 26 so as to be connected to the N ⁺ diffusion layer 10b, and the interlayer insulating layer including the plug 28 is formed. An interlayer insulating layer 30 is further laminated on 26, and a metal wiring layer 32 made of, for example, aluminum is formed thereon. This metal wiring layer 32 becomes the bit line b or the inverted bit line b ′ shown in FIG. On the surface of the metal wiring layer 32,
An SRAM is manufactured by forming a passivation film and the like. In FIG. 5, reference numeral 34 indicates a P-type semiconductor substrate, and reference numeral 36 indicates an N well region.

The present invention is not limited to the above-mentioned embodiments, but can be variously modified within the scope of the present invention. For example, in the above-described embodiments, the method of the present invention is applied to the method of manufacturing the P-type MOSTFT load type SRAM, but it can be applied to the method of manufacturing other semiconductor devices.

[0021]

As described above, according to the present invention, by doping the first conductivity type electrode layer with the first conductivity type impurity through the contact hole, the impurity concentration of the portion is reduced. Since it has been raised, after that,
The second conductivity type electrode layer is formed through the contact hole to the first
When connecting to the conductivity type electrode layer, even if the impurities of the second conductivity type contained in the electrode layer of the second conductivity type diffuse into the electrode layer of the first conductivity type, the impurities in the electrode layer of the first conductivity type Of the second conductivity type is prevented from being unnecessarily lowered by the diffusion of the second conductivity type impurity.

As a result, it is possible to prevent adverse effects on the transistor located on the lower layer side. For example, when the method of the present invention is applied to a method for manufacturing a PMOS / TFT load type SRAM, the threshold voltage of a driving transistor is prevented from rising and a source / drain region formed on the semiconductor substrate side is formed. an increase in junction leak N ⁺ diffusion layer to prevent made to prevent the decrease in the junction capacitor of the N ⁺ diffusion layer, it becomes possible to suppress an increase in contact resistance of the gate electrode layer to the N ⁺ diffusion layer ..

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view of an essential part showing the manufacturing process of an SRAM according to an embodiment of the present invention.

FIG. 2 is a schematic sectional view of a key portion showing the manufacturing process of the SRAM according to the embodiment.

FIG. 3 is a main-portion schematic cross-sectional view showing the manufacturing process of the SRAM according to the embodiment;

FIG. 4 is a schematic sectional view of a key portion showing the manufacturing process of the SRAM according to the embodiment.

FIG. 5 is a schematic sectional view of a key portion showing the manufacturing process of the SRAM according to the embodiment.

FIG. 6 is an equivalent circuit diagram showing a memory cell of SRAM.

[Explanation of symbols]

2 ... P well region 6 ... Gate insulating layer 8a, 8b ... Gate electrode layer 8c ... Ground electrode layer 10a, 10b, 10c ... N ⁺ diffusion layer 12 ... Interlayer insulating layer 14 ... Contact hole 18a, 18b ... Gate electrode layer 22 … Semiconductor layers Q1, Q2… Driving transistors Q3, Q4… Selection transistors Q5, Q6… Load transistors (TFT)

Claims (2)

[Claims] 1. A method of manufacturing a semiconductor device, wherein a thin film transistor of a second conductivity type having a polarity opposite to that of the first conductivity type is formed on a surface of a semiconductor substrate on which a transistor of a first conductivity type of one polarity is formed. A part of the second conductive type thin film transistor is formed by stacking an insulating layer on a first conductive type electrode layer forming a part of the first conductive type transistor and passing through a contact hole formed in the insulating layer. When connecting the second-conductivity-type electrode layer constituting the first-conductivity-type electrode layer to the first-conductivity-type electrode layer, the first-conductivity-type electrode layer is doped with the first-conductivity-type impurity through the contact hole of the insulating layer. Then, a method of manufacturing a semiconductor device, characterized in that an electrode layer of the second conductivity type is laminated on the insulating layer so as to be inserted into the contact hole. 2. The amount of impurities of the first conductivity type doped through the contact hole is equal to or more than the amount of impurities doped in the electrode layer of the second conductivity type. 1. The method for manufacturing a semiconductor device according to 1.