JP2005251776A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a fully-depleted SOI transistor in which threshold voltage can be set to an arbitrary value and current can be enlarged and a high speed operation is realized with low power consumption and low leakage current while a characteristic of the fully depleted-type SOI transistor is maintained by conventional manufacture technology. <P>SOLUTION: Desired impurity is introduced into a support substrate just below a region where the hyperfine fully depleted SOI transistor is formed, and threshold voltage is controlled. A gate input signal is applied to a well diffusion layer just below the transistor. Thus, large driving current/low power consumption are realized even with low power voltage by controlling substrate potential through a thin embedded insulating film. The gate input signal is connected to the well diffusion layer by using gate electrode wiring being the lowermost wiring. Consequently, an increase of an occupied area is suppressed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an insulated gate field effect transistor, and more particularly to a high-performance and ultrafine insulated gate field effect transistor provided in a semiconductor thin film on an insulating film, and a manufacturing method thereof.

  An insulated gate field effect transistor (referred to as IGFET) which is called SOI (Silicon On Insulator) and is formed of a thin single crystal thin film arranged on a support substrate via an insulating film is known. Further, a method of arbitrarily controlling the threshold voltage value of the IGFET by applying a voltage to the support substrate immediately below the IGFET is known as shown in Non-Patent Document 1, for example, and has a structure shown in FIG. In the figure, an IGFET is manufactured in a single crystal Si film 3 formed from a support substrate 1 through a buried insulating film 2, wherein 6 and 9 are source diffusion layers, 7 and 8 are drain diffusion layers, and 20 is a gate. Insulating films 10 and 11 are gate electrodes, and 4 is an element isolation insulating film composed of a single crystal Si film 3. A well diffusion layer 5 electrically separated from the support substrate 1 by a PN junction is formed on the support substrate 1 immediately below the IGFET, and a desired voltage signal can be applied by the metal electrode wirings 13 and 14 through the openings. It has become. When the IGFET on the well diffusion layer 5 is an n-channel IGFET by applying a positive voltage to the well diffusion layer 5, it can be controlled so that the threshold voltage is reduced and the threshold voltage is increased to a positive value by applying a negative voltage. Although the threshold voltage control of a normal IGFET formed on a semiconductor substrate is also possible by controlling the substrate applied voltage, when a positive voltage is applied to the substrate, a forward voltage is applied to the source diffusion layer of the n-channel IGFET. The diode forward current is unavoidable, and therefore there is an upper limit in the applied voltage value. In the structure of FIG. 2, in the structure of IGFET, even if the positive applied voltage that can be applied to the well diffusion layer 5 is sufficiently high, the buried insulating film Due to the existence, there is no current component flowing into the N conductivity type source diffusion layer 6, and the upper limit of the applied voltage value does not exist in principle. In the known IGFET shown in FIG. 2, it is naturally possible to introduce an impurity having an arbitrary distribution into a channel region, that is, a desired region of the single-crystal Si film 3 as a threshold voltage control means as in the prior art.

As IGFETs are becoming increasingly miniaturized, it is necessary to increase the concentration of impurities to be introduced into the channel region and substrate region in order to control the threshold voltage and suppress punch-through in IGFETs that should support further miniaturization. However, the required maximum impurity concentration in an ultrafine IGFET having a gate length of 50 nm or less is 5 × 10 ¹⁸ / cm ³ or more. In this state, the drain leakage current (GIDL) due to the gate electric field and the leakage current between drain substrates due to the band-to-band tunneling current cannot be ignored. Further, when impurities of the above-mentioned concentration are introduced into the channel and substrate region of the ultrafine IGFET, fluctuations in the amount of introduced impurities combined with variations in gate processing dimensions cause variations in threshold voltage values. For example, low voltage operation SRAM ( A write failure in the static random access memory).

In the ultrafine SOIIGFET, the structure in which the single crystal silicon film 3 constituting the transistor is sufficiently thin and the impurity introduced into the channel region is extremely low in concentration is referred to as a fully depleted type. Therefore, the punch-through path is difficult to occur. Therefore, future ultrafine IGFETs must be completely depleted SOIIGFETs. However, in a fully depleted SOIIGFET, threshold voltage control is only known by selecting a work function using a gate electrode material and a well potential control method shown in FIG.
A double gate structure is known as another conventional technique related to SOIIGFET (see, for example, Patent Document 1). In the SOIIGFET, a source diffusion layer and a drain diffusion layer are formed in the SOI layer 105 in a self-alignment with the dummy gate electrode, then a reverse pattern groove of the dummy gate electrode is formed, and impurity ions are implanted into the support substrate 1 from the groove. The buried gate is sequentially formed, and then, a metal film such as W is selectively buried in the groove region to form an upper gate electrode. Realization of a double gate structure is an effective means for improving the performance of SOIIGFET, but in a double gate structure based on a currently known method, a high-concentration diffusion layer or the like is embedded in a support substrate without adversely affecting the SOI layer. This is extremely difficult and has not yet been put into practical use. Considering the difficulty of manufacturing and considering the essential concept of the double gate structure, it is assumed that the buried gate is accurately aligned with the upper gate, and it is inevitably required to be arranged for each individual element. There is basically no concept of sharing the role of the buried gate electrode among a plurality of IGFETs. In the ultrafine SOIIGFET, the alignment error of the buried gate is fatal, and directly connected to variations in parasitic capacitance and drive current. Therefore, even if the parasitic capacitance is effectively used for stabilizing the dynamic operation, it cannot be used for stabilization unless capacitance variation is essentially suppressed. Further, the threshold voltage of the double gate structure SOIIGFET is determined only by the work functions of the upper and buried gate materials, excluding the SOI layer thickness component, and it is virtually impossible to set the threshold voltage value for each desired IGFET. The connection between the buried gate electrode and the upper gate electrode is also assumed to be performed outside the IGFET active region, that is, in the element isolation region, and consistency in consideration of the peripheral element layout is essential.

JP 2000-208770 A

“Variable threshold-voltage SOI CMOSFETs with implanted back-gate electrodes for power-managed low-power and high-speed sub-1-V ULSIs”, T. Kachi et al., 1996 Symp. VLSI Tech. Pp.124-125

  The first problem to be solved by the present invention is that the threshold voltage value of a fully depleted SOI IIFET is principally determined by the work function of the upper gate electrode 10, and other means are within the support substrate shown in FIG. The problem is that only the technique of controlling the well potential can be applied. For example, in a plurality of fully depleted SOI IIFETs, in order to design the threshold voltage to a desired individual value, each IGFET is manufactured using a different gate material, or a well formation and its control electrode are provided for each individual IGFET. Each of them must be formed and cannot be manufactured in practice. An object of the present invention is to provide a means for solving a fundamental problem relating to threshold voltage control in a conventional fully depleted type SOIIGFET, and in a fully depleted type characteristic without changing a gate material in an adjacent IGFET in the same substrate. It is to provide a new structure that can be controlled to an arbitrary threshold voltage while maintaining.

  The second problem to be solved by the present invention is to provide a structure capable of further improving the performance of the ultrafine fully depleted SOIIGFET with a good yield with the current semiconductor device manufacturing technology. That is, the second problem of the present invention is to increase the drive current without increasing the leakage current in individual IGFETs or individual IGFETs constituting a logic circuit without increasing the occupied area in the ultrafine fully depleted SOIIGFET. Further, it is to realize performance improvement such as suppression of the so-called short channel effect by further suppressing the punch-through phenomenon, and to operate a finer SOIIGFET normally. The above-mentioned improvement in performance is called the sub-threshold coefficient, which reduces the slope near the threshold voltage value in the gate voltage dependency of the source / drain current, enables a sharp on / off operation, and reduces the high-speed operation and low It also includes the characteristics that make leakage current compatible.

  A third problem of the present invention is a fully depleted SOI IIFET using a technique for improving mobility by controlling semiconductor physical properties, for example, a technique for imparting strain such as modifying the lattice constant of a silicon single crystal. The concept of further improving the performance by enabling the combination with such a transistor structure corresponds to the fact that has not been proposed previously. That is, the present invention is to provide a new structure capable of further improving the performance of a fully depleted SOIIGFET having a strained silicon thin film while maintaining the state in which the lattice constant of the silicon single crystal is modified.

  The fourth problem of the present invention is to essentially eliminate the problems of difficulty of realization, drive current variation and parasitic capacitance variation resulting from alignment error of the buried gate electrode, while taking advantage of the performance improvement characteristics of the double gate type SOIIGFET. is there. Furthermore, the premise that a buried gate is required for each individual element is eliminated, and the increase of the occupied area is suppressed by sharing the role of the buried gate among a plurality of elements. From the viewpoint of suppressing an increase in the occupied area, it is included in the problem that the restriction on the connection region between the buried gate and the upper gate is essentially eliminated. Another object of the present invention is to solve the problem that the threshold voltage value in the double gate structure is substantially determined by the upper and buried gate electrode materials and cannot be arbitrarily controlled for each individual element. The voltage value can be controlled.

  In the present invention, it is assumed that a single crystal semiconductor substrate and an SOI substrate made of a thin single crystal semiconductor thin film (SOI layer) separated from the single crystal semiconductor substrate by a thin buried insulating film are used. The present invention is premised on application to an ultrafine fully depleted SOI IIFET having a gate length of 100 nm or less, and further 50 nm or less. The buried insulating film is 50 nm or less, preferably 10 nm or less, and the thin single crystal semiconductor thin film is 20 nm or less, preferably An SOI substrate having a thickness of about 10 nm is used.

  As a means for solving the above problems, in the present invention, a so-called mesa isolation structure for removing the SOI layer is used for isolation between individual elements of the SOIIGFET, and a well-known insulating isolation structure as an element isolation structure by a normal substrate is used as a support substrate. Arranged in a desired area in a reaching configuration. In the support substrate region surrounded by the insulating isolation structure, a well diffusion layer region is formed by introducing impurities and electrically separated from other well regions. In the present invention, in the SOIIGFET, element isolation uses both mesa isolation and an insulating isolation structure inside the SOI layer. The advantage of using the insulation isolation structure that reaches the support substrate is that the connection hole with the source / drain diffusion layer is opened in the wiring process even if there is a pattern shift. Generation | occurrence | production of generation | occurrence | production can prevent generation | occurrence | production of the defect which a drain or a source electrode short-circuits with a support substrate. That is, it is not necessary to secure an extra margin for the opening pattern and the source / drain regions, and the disadvantage of increasing the occupied area is solved. In the known SOI layer mesa isolation structure, when the SOI layer and the buried insulating film are as thin as about 10 nm, a thin buried insulating film is formed due to the deviation of the opening pattern unless an extra margin for the opening pattern and the source and drain regions is secured. It is easily removed in the opening process, and the risk of short circuit failure with the support substrate is not solved. When the SOI layer is thin, the insulating isolation film reaching the buried oxide film from the main surface is too thin to be suitable for eliminating short-circuit defects due to opening pattern deviation. Therefore, in the conventionally known mesa isolation structure and the insulation isolation structure up to the buried insulating film, it is required to secure a sufficient alignment margin between the opening pattern and the source / drain diffusion layer regions. That is, the occupation area is increased. The present invention aims at solving fundamental problems such as difficulty in manufacturing, dispersion of drive current and parasitic capacitance, and increase in occupied area, while taking advantage of the inherent performance improvement characteristics of SOIIGFETs with a conventionally known double gate structure. The present invention proposes a new method that enables a new dynamic operation of an SOIIGFET having an effective gate insulating film.

  In the present invention, a pair of complementary SOIIGFETs are formed on the same well diffusion, and a method of applying the same signal as that applied to the gate electrode to the well is also used. Completely different. The use of the insulating isolation structure that reaches the inside of the support substrate from the main surface also has the effect of reducing the parasitic capacitance of the well diffusion region whose side surface is surrounded by the insulating isolation film. That is, when a dynamic signal is applied to the well diffusion region, high speed operation is possible due to the parasitic capacitance reduction effect. A plurality of SOIIGFETs sharing a well may not have a complementary relationship if desired.

As a technique for controlling the individual threshold voltage values of the fully depleted SOIIGFET, which is the first problem described above, the present invention avoids introducing impurities into the SOI layer immediately below the gate electrode, while avoiding the maximum impurity in the upper region of the support substrate immediately below the gate electrode. A desired amount of N-conductivity type or P-conductivity type impurities is selectively introduced in a distribution such as a concentration. The introduction uses an ion implantation method, and the control of the distribution shape is based on the setting of the acceleration energy. In the case of the semiconductor device of the present invention, it is sufficient that the implanted impurity amount is 1 × 10 ¹⁹ cm ⁻³ or less, and further 5 × 10 ¹⁸ cm ⁻³ or less. The reason for avoiding the introduction of impurities into the SOI layer is to ensure a fully depleted type. The technique of controlling the threshold voltage of the SOIGFET directly above by introducing impurities into the upper region of the support substrate causes an increase in drain capacitance, that is, parasitic capacitance, when the buried insulating film is thin. If it is not desired to increase the parasitic capacitance, or if it is desirable to control the capacitance value, a desired amount of an impurity having a conductivity type opposite to the introduced impurity is introduced immediately below the source / drain diffusion layer in the impurity introduction region above the support substrate. That's fine. Impurity introduction for compensation can be realized by ion implantation using the gate electrode of SOIIGFET as an implantation blocking mask. As a result, the parasitic capacitance can be arbitrarily controlled, and the occurrence of variations in parasitic capacitance based on the alignment can be essentially eliminated. It is desirable to reduce the resistance of the well when applying a dynamic signal to the well diffusion region. Impurity distribution is to increase the well concentration and reduce the well resistance in the deep portion of the well except the threshold voltage control impurity introduction region near the well surface. Can be controlled. In any case, the amount of impurities to be introduced into the well region is configured to be orders of magnitude lower than that of a buried gate in a known double gate structure. The reduction in the impurity concentration suppresses the performance improvement due to the increase in resistance, but it is essentially free from problems due to the introduction of impurities, the introduction of high impurities against the intention of the SOI layer, the occurrence of crystal defects, and the like. Furthermore, since the region can be shared by a plurality of elements in the formation of the well region, there is an effect of reducing the occupied area including the connection region.

In the present invention, the threshold voltage value can be essentially controlled by the work function based on the gate electrode material, but in the structure of the present invention, by introducing impurities into the supporting substrate region, the threshold voltage value can be controlled for adjacent transistors having the same gate electrode material. Can also change the threshold voltage. In fully depleted SOIIGFETs, the threshold voltage value is set to nearly zero by using a high melting point metal material having a work function corresponding to the vicinity of the forbidden band center of a silicon single crystal or a silicide thereof as the upper gate electrode material. it can. In the structure of the present invention, the threshold voltage value can be easily moved by about 0.2 V by introducing impurities of about 10 ¹⁸ cm ⁻³ into the support substrate region. Although the present invention is based on the SOI structure, threshold voltage control similar to that of a normal substrate is possible, and the field of application of fully depleted SOIIGFETs for which application fields are limited can be dramatically expanded. In particular, fields that can be applied as ultra-fine semiconductor devices with low power consumption and large driving capability are dramatically expanded.

  In order to solve the second problem, in the present invention, an input signal to be applied to the gate electrode is applied to the well diffusion layer immediately below the SOIIGFET at the same timing. When applying a high potential to the gate electrode to make the SOIIGFET conductive, the conductive state of the SOIIGFET is further accelerated by applying a high potential of the well potential through the thin buried insulating film, and the drive current is greatly increased, that is, a large current Is brought about. When the gate potential is applied to a low potential, the well potential also follows and decreases, so that the non-conduction state can be reached more quickly. That is, in the above operation mode, it is possible to realize a characteristic that the drive current is further increased under the same leakage current condition, and it is possible to perform conduction / non-conduction switching at higher speed. The isolation of the side surface of the well diffusion layer contributes to the reduction of parasitic capacitance, that is, the delay time constant of the applied signal. In addition, the thinner the buried insulating film, the more effective the improvement of the driving current is, and ideally the film thickness condition is equivalent to that of the gate insulating film of SOIIGFET.

  In solving the second problem, if the occupied area is increased, the parasitic capacitance is increased as a result, and the performance improvement effect cannot be expected. In the present invention, in order to achieve an improvement in performance without causing an increase in the occupied area, the present invention newly adopts a configuration in which the well region and the gate electrode are directly connected in the gate electrode formation step. The reason why the gate electrode is directly connected to the well region is that in the IGFET configuration, the gate electrode is the lowermost wiring. That is, the lower layer wiring is generally configured to have a higher arrangement density. In order to connect the upper wiring to the base well diffusion region, it is necessary to carry out in a region where the lower layer wiring does not exist, resulting in the occupation. This leads to an increase in area. Especially in memory cell areas where high-density layout is required, there is almost no area where the upper metal wiring connects to the underlying well area in areas where no gate electrode wiring exists, and it is almost difficult without increasing the occupied area. is there.

In order to enable connection with the well region by the gate electrode, in the present invention, after forming the gate insulating film and depositing the thin first gate electrode material, silicon thin film, a thin buried insulating film on the well region to be connected, The gate insulating film and the first gate electrode material are selectively removed. Subsequently, a second gate electrode material may be deposited on the entire surface, and a gate electrode wiring may be formed by a desired pattern processing. As a result, the well diffusion layer and the gate electrode are directly connected in a desired region, and a wiring that functions as a normal gate electrode is formed in the other regions. By the above method, even in a region requiring a high-density layout such as a memory cell, wiring connection to the well region can be performed without increasing the occupied area.
Regarding the third problem, in the semiconductor device according to the present invention, a multilayer SOI substrate is manufactured in a state in which lattice strain is applied in advance to an ultrathin single crystal silicon film on which the semiconductor device is to be manufactured. It is only necessary to manufacture the semiconductor device according to the technique described in detail in the examples. In the manufacturing of the above-mentioned multilayer structure SOI substrate, the points to be noted are described in detail in the embodiments of the present invention, but the bonding is performed after the bonding process of the substrate to be the support substrate and the ultrathin single crystal silicon film. The heat treatment for strengthening the strength is performed at a low temperature of about 900 ° C. or less so that the lattice strain is not relaxed. To the strained semiconductor thin film, the operation of a large current is further improved by the characteristics of the semiconductor device according to the present invention and the effect of increasing the mobility by the strained semiconductor thin film.

  The semiconductor device according to the present invention is fundamentally different from a low resistance buried gate electrode disposed under a thin buried insulating film and a conventional structure called a double gate structure controlled by the upper gate electrode. In other words, in the semiconductor device according to the present invention, the connection between the gate electrode and the active region lower well region may be at an arbitrary position of the well region, whereas in the double gate structure, accurate alignment to the buried gate electrode is possible. Required. A further difference is in the fully depleted type SOIIGFET. The threshold voltage value control of the semiconductor device according to the present invention can be arbitrarily set in each IGFET by setting the conductivity type, impurity concentration, and distribution of impurities in the lower well region of the channel region. Although it is easy to set the value, in a so-called double gate structure, since it is determined by the work function of the buried gate electrode, it is practically impossible to control to an arbitrary value for each IGFET. In order to keep the resistance value of the buried gate electrode low, even when an impurity diffusion layer is used to make the buried gate electrode, a high impurity concentration is essentially required, and the work function is fixed.

  According to the present invention, an SOIIGFET that can achieve an increase in driving current and a reduction in leakage current can be realized by using the existing manufacturing process. Accordingly, it is possible to realize a semiconductor device capable of sufficiently high-speed operation even under a low power supply voltage condition and capable of reducing current consumption. Furthermore, according to the present invention, an arbitrary threshold voltage value can be set between adjacent IIGFETs, which cannot be achieved by means other than the means for changing the gate electrode material, in the fully depleted SOIIGFET without changing the gate electrode material. Therefore, it is possible to realize a semiconductor device having a greatly improved degree of freedom in circuit configuration without problems of variations in threshold voltage, and there is an effect that low cost can be achieved by improving the yield of non-defective products. Furthermore, according to the present invention, it can be applied to a semiconductor having a lattice strain that can improve the mobility by 1.5 times or more from the viewpoint of semiconductor physical properties. Combined with this, there is an effect that the insulated gate field effect transistor can be further reduced in power consumption and operated at high speed.

In the following embodiments, when necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other, and one is the other. Some or all of the modifications, details, and supplementary explanations exist.
Further, in the following examples, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), unless explicitly stated and in principle limited to a specific number in principle, It is not limited to the specific number, and it may be more or less than the specific number.
Further, in the following embodiments, it is needless to say that the constituent elements (including element steps and the like) are not necessarily essential unless otherwise specified and apparently essential in principle. .

Similarly, in the following embodiments, when referring to the shape and positional relationship of components and the like, it is substantially approximate to the shape, etc., unless otherwise specified or otherwise considered in principle. It shall also include similar items. The same applies to the above numerical values and ranges.
Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted.
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Needless to say, the material, conductivity type, manufacturing conditions, and the like of each part are not limited to those described in the present embodiment, and many modifications are possible.

<Example 1>
3 to 5 and FIG. 7 are cross-sectional views showing the order of manufacturing steps of the semiconductor device according to the first embodiment of the present invention, FIGS. 1 and 8 are completed cross-sectional views, and FIG. 6 is a completed layout view. For convenience of explanation, the semiconductor substrate and the semiconductor film will be described with the conductivity type fixed, but the combination of conductivity types may be arbitrary, and is not limited to the conductivity type described in this embodiment. A silicon thermal oxide film 2 having a thickness of 10 nm is formed on a semiconductor substrate 1 made of single crystal Si having a plane orientation (100), a P conductivity type, a resistivity of 10 ohm · cm, and a diameter of 20 cm. The semiconductor substrate was made. Hydrogen ion implantation was performed on the first substrate based on a known ultra-thin SOI substrate manufacturing method. The injection amount was 5 × 10 ¹⁶ / cm ² . As a result of the ion implantation, a crystal defect layer 31 was formed at a depth of about 40 nm from the main surface of the single crystal Si substrate. From this state, each of the second semiconductor substrates having the same specifications as the first semiconductor substrate having no silicon oxide film on the surface was subjected to a hydrophilic treatment, and the main surfaces were brought into close contact with each other at room temperature. Next, the two Si substrates that were brought into close contact with each other were heated to 500 ° C., but this heat treatment resulted in the formation and increase of microvoids in the crystal defect layer, and the single crystal Si substrate was peeled off at the crystal defect layer portion and supported. A silicon thermal oxide film 2 having a thickness of 10 nm was adhered on the substrate 1, and a single crystal Si thin film 3 having a thickness of about 20 nm was adhered thereon. By applying a high-temperature heat treatment at 1100 ° C. from this state, the adhesive strength between the silicon thermal oxide film 2 and the support substrate 1 was remarkably improved, and the adhesive strength was comparable to that of a normal single crystal substrate. From this state, the surface of the single crystal Si thin film 3, that is, the peeled surface is mirror-polished by a surface polishing method that does not include abrasive grains, and a thin embedded gate insulating film 2 is formed on the support substrate 1 in order under the single crystal Si thin film 3 The manufactured SOI substrate was manufactured. The SOI substrate described above does not need to be manufactured based on the above method, and there is no problem even if it is based on the purchase of a commercially available substrate having similar specifications.

  In the SOI substrate, an N conductivity type well diffusion layer 5 was selectively formed in a desired region of the support substrate 1 by ion implantation through the thin single crystal Si film 3 and the thin buried insulating film 2. Further, threshold voltage control diffusion layer regions 52 and 53 were also formed by ion implantation in one part of the support base below the region where the channel region is to be formed. Subsequently, a silicon oxide film 18 having a thickness of 10 nm and a silicon nitride film 19 having a thickness of 100 nm are deposited on the thin single crystal Si film 3, and then patterning for determining an active region of the single crystal Si film 3 is performed. It was applied together with the silicon nitride film 19. Subsequently, As is implanted at a high concentration in the vicinity of the surface of the support substrate 1 immediately below the buried insulating film 2 by ion implantation using the resist mask used for the patterning as a blocking mask, an N conductivity type high concentration diffusion layer 50 is formed ( FIG. 3).

From the state of FIG. 3, the second resist mask is left in the desired region, and the support substrate 1 and the buried oxide film 2 in the desired region are selectively removed by a synthetic mask with the first resist mask 90. The elements constituting the pair of complementary IGFETs were patterned so as to be disposed on the same well diffusion layer 5. The element separation between the complementary IGFETs was performed by selectively removing the thin single crystal Si thin film 3. (Figure 4)
After removing the resist mask from the state shown in FIG. 4, a thick silicon oxide film 4 is formed so as to fill the patterning region and form a thin thermal oxide film on the exposed Si region based on a known element isolation insulating film formation method. The whole surface was deposited. Subsequently, a thick silicon oxide film exposed by selectively removing the silicon nitride film on the region left by selective deposition and deposition of a silicon nitride film (not shown) and a predetermined distance from the region. Was removed by chemical mechanical polishing. The polishing end point is the silicon nitride film deposited last and the silicon nitride film 19 left on the pattern. Subsequently, the silicon nitride film 19 and the like are selectively removed with hot phosphoric acid to expose the surface of the single crystal Si thin film 3, and then a thermal oxide film of 1.8 nm is formed and the surface is nitrided with NO gas, thereby nitriding to a thickness of 0.2 nm. A film was stacked on the main surface to form a gate insulating film 20. The film thickness of the single crystal Si thin film 20 in the state before forming the gate insulating film 4 was reduced to 10 nm by surface cleaning treatment or the like. Subsequently, a first polycrystalline Si film 21 having a thickness of 10 nm is deposited on the gate insulating film 20 by chemical vapor deposition, and then the first polycrystalline Si film 21 and the gate insulating film 20 in the connection region with the well region are deposited. Was selectively removed. (Figure 5)
From the state of FIG. 5, a gate protection film 23 composed of a second polycrystalline Si film 22 having a thickness of 40 nm and mainly a silicon nitride film is deposited on the entire surface, and then a gate electrode formed by patterning by a conventionally known IGFET manufacturing method. Then, the gate protective film 23 was formed. The minimum width of the gate electrode, that is, the gate length is 50 nm, and the height of the gate electrode is 100 nm including the gate protective insulating film 23. Here, the polycrystalline Si of the gate electrode on the connection region with the well diffusion layer is directly connected to the N conductivity type high concentration diffusion layer 50 in the well region. In this embodiment, no impurity for reducing the resistance is introduced into any of the gate electrodes 50 of the N conductivity type IGFET and the P conductivity type IGFET. The thin gate insulating film 4 in the exposed region was also removed at this time.

Next, an As ion is applied to the N-conducting IGFET region, and a BF ₂ ion is applied to the P-conducting IGFET region under the conditions of an implantation amount of 4 × 10 ¹⁵ / cm ² with acceleration energy of 1 keV and 600 eV, respectively. Are implanted using an implantation blocking mask as a mask, and an ultra-shallow N-conductivity type high-concentration source diffusion layer 6, an ultra-shallow N-conduction type high-concentration drain diffusion layer 7, and an ultra-shallow P-conduction type high-concentration source diffusion layer 9, An extremely shallow P conductivity type high concentration drain diffusion layer 8 was formed in the main surface region of the single crystal Si film 3. By the ion implantation, the bottom region of the single crystal Si film 3 was slightly monocrystalline and its upper part was almost amorphous. From this state, the semiconductor surface temperature was raised to about 1200 ° C. by laser irradiation with an irradiation time of about several tens of nanoseconds, and the introduced impurities were thermally activated. The activation heat treatment has no problem even if it is based on other methods such as short-time high-temperature lamp irradiation of 1 second or less. Subsequently, a laminated film of a silicon oxide film and a silicon nitride film having a thickness of 70 nm was deposited on the entire surface, and then anisotropic dry etching was performed to selectively leave the gate electrode side wall portion to form the gate side wall insulating film 26. Next, an alumina (Al ₂ O ₃ ) film having a thickness of 15 nm, a silicon oxide film 12 having a thickness of 100 nm, and a silicon nitride film having a thickness of 50 nm are sequentially deposited on the entire surface by chemical vapor reaction, and then chemical mechanical polishing is performed. Then, the surface was flattened by removing the protrusions on the gate electrode. The polishing end point is the uppermost silicon nitride film. Next, an opening was made in the connection region with the source / drain diffusion layer. In the opening, the alumina film showed a resistance of 20 times or more as compared with the etching rate of the silicon oxide film, and the gate sidewall insulating film was sufficiently prevented from being scraped. From this state, a polycrystalline Si film is deposited over the entire surface by a chemical vapor reaction so that the opening is completely filled, and then chemical mechanical polishing is performed again on the planarized opening surface to form polycrystalline Si 25. It was left selectively only inside the opening. In addition, instead of selectively leaving polycrystalline Si at the source / drain connection port by chemical mechanical polishing, a Si film having a thickness of 60 nm is selectively formed on a single-crystal Si region exposed using a known selective epitaxial method. A technique of depositing may be used. Thereafter, high-concentration ion implantations of As and B were performed on the polycrystalline Si film regions on the N-conductivity type IGFET and the P-conductivity type IGFET, respectively, to form an N-conductivity type high-concentration stacked region 25. (Fig. 7)
The gate protective film 23 is selectively removed from the state of FIG. 7 to expose the gate polycrystalline Si film, and then a 30 nm thick Ni (nickel) film is deposited on the entire surface by sputtering, and the exposed gate electrode The entire region 22 and at least the upper region of the N conductivity type high concentration accumulation region 25 were selectively silicided by a heat treatment at 450 ° C. to form a silicide gate electrode 22, a silicide metal source, and a drain region 28. In the silicidation process, the silicon gate electrode to which no impurities were added was converted into a nickel silicide film up to the region in contact with the gate insulating film, and the resistance was reduced. The stacked Si film on the source / drain diffusion layer is not entirely silicided, a low-resistance polycrystalline Si film is left in the bottom region, and the very shallow source / drain diffusion layers 6 and 7 in the thin single crystal Si are preserved. It was done. After the above silicidation treatment, only the unreacted Ni film on the insulating film is selectively removed with an etching solution using a mixed aqueous solution of hydrochloric acid and hydrogen peroxide, and then again, the interlayer insulating film is deposited and planarized. In addition, a wiring process including the wiring interlayer insulating films 15 and 17 was performed, and a semiconductor device was manufactured through a second wiring process. (Figure 8)
FIG. 6 is a completed plan view of the semiconductor device according to this embodiment, FIG. 1 is a completed sectional view at ab in FIG. 6, and FIG. 8 is a completed sectional view at cd in FIG. The completed sectional view at ef in FIG. 6 corresponds to the P-conductivity type IGFET, but the display is omitted because it has the same configuration in which the conductivity type in FIG. 8 is reversed. In FIG. 6, reference numeral 51 denotes a connection region between the gate electrode 22 and the well diffusion layer region. In FIG. 6, the left half is an N conductivity type IGFET, the right half is a P conductivity type IGFET, 6 is an N conductivity type high concentration source region, 7 is an N conductivity type high concentration drain region, and 8 is a P conductivity type high concentration source. A region 9 is a P-conductivity type high-concentration drain region, and an N-conductivity type IGFET and a P-conduction type IGFET region are separated from each other by an element isolation insulating film 4, and the IGFETs are separated from each other by a thin Si film mesa isolation region 49. Has been.

  The gate electrode 22 was composed of a metal silicide film. As a result, in the semiconductor device according to the present embodiment, the threshold voltage value can be set to approximately 0 V in both the N-conducting IGFET and the P-conducting IGFET regardless of the fully depleted SOIIGFET. In addition, despite the fact that the single crystal Si thin film 3 constituting the channel is finally formed to be as thin as 10 nm, the source and drain regions have a stacked structure, and most of the stacked structure is a metal silicide film. Since it was constructed, it was possible to solve the problem of increase in contact resistance between the semiconductor and the metal silicide film and increase in series resistance. Further, in the semiconductor device according to this embodiment, the gate electrode 22 common to the N-conductivity type IGFET and the P-conductivity type IGFET is connected to the well region formed below each IGFET in a serial relationship with the gate electrode. The gate input signal of the complementary IGFET is also applied from the back side of each IGFET through the thin buried oxide film 2. As a result, when the input potential is switched from the ground potential to a positive high potential, the N conductivity type IGFET is switched to the conductive state and the P conductivity type IGFET is switched to the cutoff state, but the well potential is also switched from the ground potential to the positive high potential. Through the thin buried insulating film 2, the N-conductivity type IGFET acts to decrease the threshold voltage value, and as the conduction state increases, the P-conduction type IGFET acts to increase the threshold voltage value and Acts like strengthening. That is, the N conductivity type IGFET acts to increase the current operation and the drive current, and the P conductivity type IGFET acts to further reduce the leakage current. When the input potential is switched from a positive high potential to the ground potential, the opposite effect occurs. Accordingly, in the complementary IGFET configuration in which the N conductivity type IGFET and the P conductivity type IGFET are paired, that is, in the inverter circuit, the switching of the output potential acts so as to be realized at higher speed.

  In the semiconductor device according to this embodiment, a large driving current of the IGFET can be realized, but it is necessary to consider the addition of parasitic capacitance related to the well diffusion layer 5. In this embodiment, by adopting a configuration in which the periphery of the well diffusion layer 5 is separated by the element isolation structure, the parasitic capacitance of the well diffusion layer 5 is greatly reduced. It is possible to achieve both the reduction of the bottom parasitic capacitance of the well diffusion layer 5 and the reduction of the well resistance. The impurity distribution should be set so that the impurity concentration is low in the well bottom region and high in the vicinity of the buried insulating film. It ’s fine. As a result, the parasitic capacitance can be reduced by about one digit even in the same well occupation area configuration as compared with the well structure of the known structure shown in FIG. Further, in the semiconductor device according to the present embodiment, since it can be directly connected to the well diffusion layer by the gate electrode which is the lowermost layer wiring, the connection region can be set regardless of the upper wiring. As a result, it is possible to realize a large current and high driving capability of the semiconductor device without increasing the occupied area because the connection with the upper wiring does not require the connection in the margin area considering the layout of the lower wiring as in the conventionally known structure. . Features that do not increase the occupied area are effective in further reducing the parasitic capacitance. Accordingly, there are a wide variety of circuits applicable to the semiconductor device according to the present embodiment, which are applied to SRAM memory cells, I / O buffer circuits, and critical path drive regions that define the operating speed of the integrated circuit as described later. Is most effective.

In the semiconductor device based on the present embodiment, it is called a double gate structure and has an effect equivalent to that of a double gate IGFET for which an element structure has been proposed but an ultrafine IGFET has not yet been realized. It is essentially eliminated from various problems related to the introduction of a practical construction method of the low resistance buried region to be constructed. It has been confirmed that the semiconductor device based on this embodiment exhibits a high-speed operation of about 1.5 times the switching speed with the same occupied area as compared with an inverter manufactured using a conventionally known SOI substrate.
In the semiconductor device according to the present embodiment, it is desirable that the thin buried insulating film 2 be as thin as possible within a film thickness range in which leakage current is negligible, and it is preferably 10 nm or less, more preferably about the same as the gate insulating film 20. A film thickness of about 2 nm is desirable.

  In the semiconductor device according to this embodiment, the gate electrode material is not limited to the Ni silicide film, but is a metal such as Ni, Co, Ti, W, Ta, Mo, Cr, Al, Pt, Pa, Ru, or a metal silicide film. Alternatively, any material may be used as long as the work function of the metal nitride film is approximately in the center of the forbidden band of the single crystal Si thin film 20.

<Example 2>
FIG. 9 is a completed plan view of the semiconductor device according to the second embodiment of the present invention. In the present embodiment, the semiconductor device was manufactured according to the first embodiment. However, the gate electrode 22 was directly connected to the well diffusion layer with a different layout, and the gate electrode 22 was formed in the region via the drain diffusion layers 7 and 9 of the IGFET. And performed in parallel. Thereby, the path from the well connection region to the channel region is configured to correspond to the channel width. In general, in the IGFET, the channel width is usually designed to be larger than the channel length. Therefore, a path extending from the connection region to the bottom of the channel can be made large, and the effective well resistance can be reduced. The case of an N conductivity type IGFET will be described. When the drain potential is high, the surface of the well region immediately below the drain diffusion layer forms the gate connection region and the region directly below the SOIIGFET channel by forming an N-conductivity type layer having the drain diffusion layer as a gate electrode and a thin buried insulating film as a gate insulating film. An equivalent second IGFET is formed between them and becomes conductive. That is, depending on the drain potential, the gate input potential is applied at high speed to the region immediately below the SOIIGFET channel via the low resistance well surface region of the second IGFET, and the threshold voltage of the SOIIGFET is set via the buried insulating film 2. It acts to increase the drive current as it decreases.

  In the P-conduction type IGFET, the threshold voltage value is increased, and the leakage current is further reduced. That is, in an inverter using a complementary SOIIGFET, the output potential of the inverter approaches the ground potential from the high potential at a higher speed due to the conduction of the IGFET that is configured equivalently. When the output potential is at the ground potential and the input potential is switched from the high potential to the ground potential, a similar equivalent IGFET is formed immediately below the P conductivity type SOIIGFET, and the conduction state of the P conductivity type SOIIIFET is improved. The output potential is quickly switched from the ground potential to the high potential. The SOIIGFET based on the present embodiment shown in FIG. 9 operates so as to be able to operate at a higher speed corresponding to the dynamic behavior of the output potential.

<Example 3>
FIG. 10 is a cross-sectional view showing the order of manufacturing steps of a semiconductor device according to the third embodiment of the present invention, a cross-sectional view in a region orthogonal to the gate electrode, and FIG. 11 is a completed cross-sectional view. In this embodiment, a semiconductor device based on SOIIGFET is basically manufactured according to the above embodiment, but prior to the formation of the gate insulating film, the well diffusion layer 5 via the thin single crystal Si film 3 and the thin buried insulating film 2 is used. An impurity region for adjusting the threshold voltage of SOIIGFET was introduced into the surface region by ion implantation. A P-conductivity type impurity region 52 is introduced immediately below the N-conductivity type SOIIIFET, and an N-conductivity type impurity region 53 is introduced just below the P-conductivity-type SOIIGFET. However, the desired impurity circuit has a maximum impurity concentration of 1 × 10 ¹⁹ / cm ³ or less. After selectively setting and introducing the amount in accordance with the structure, the manufacturing process based on the above-described embodiment was carried out until the gate sidewall insulating film 26 was formed. There is no problem even if the implantation ion species for adjusting the threshold voltage based on a desired circuit configuration is an N-conducting ion species directly under the N-conducting SOIIGFET or a P-conducting ion species immediately under the P-conducting SOIIGFET. . (Fig. 10)
In the state of FIG. 10, ions of opposite conductivity type are implanted at a concentration and acceleration energy to compensate for the threshold voltage adjusting implanted ions previously implanted by ion implantation using the gate protective film 23 and the gate sidewall insulating film 26 as an implantation element mask. Impurity compensation regions 54 and 55 which are implanted and approach the intrinsic impurity region are formed. Thereafter, a semiconductor device was manufactured according to Example 1. (Fig. 11)
In the semiconductor device according to the present embodiment, the drain junction bottom capacitance of the SOIIGFET is determined by the series connection of the capacitance of the buried insulating film 2 and the depletion layer capacitance in the impurity compensation region, so that the depletion layer capacitance approximated by the intrinsic impurity concentration is obtained. Adoption results in a significant reduction in parasitic capacitance, which can contribute to the high-speed operation of the SOIIIFET, and the threshold voltage value can be designed with any value regardless of the fully depleted SOIIGFET. . Since the introduction of the threshold voltage control impurity region based on the present embodiment is introduced before the gate electrode is formed, the gate electrode end as in the so-called pocket impurity introduction for punch-through suppression of the fine IGFET on the normal substrate is used as the ion implantation mask end. Needless to say, this method eliminates the problem of increased variation in threshold voltage based on the gate electrode shape, unlike the impurity introduction method.

<Example 4>
FIG. 12 is a sectional view showing the order of manufacturing steps of a semiconductor device according to the fourth embodiment of the present invention, and FIG. 13 is a completed sectional view thereof. This embodiment is different in the method of manufacturing the SOI substrate in the first embodiment. A mixed crystal layer 31 of Si and Ge (germanium) was grown on the main surface of the single crystal Si substrate 32 by an epitaxial method. The mixed crystal layer 31 is composed of a 3 μm thick region grown by increasing the Ge composition ratio from 0 to 40% and a 2 μm thick region having a constant Ge composition ratio of 40%. The mixed crystal layer 31 is referred to as a strain relaxation layer. In succession to the formation of the strain relaxation layer 31, a Si strain layer 30 having a thickness of 10 nm was grown. It was confirmed that the amount of lattice strain in the Si strained layer 30 was about 1.6% as a deviation from the single crystal Si lattice spacing by Raman spectroscopy. Prior to the above-described epitaxial process, the warpage of the wafer after the epitaxial growth is compensated, and a silicon nitride film (not shown) is deposited on the back surface of the single crystal Si substrate 32 so as to become flat, and then a known ultra-thin SOI from the main surface side. Hydrogen ion implantation based on the substrate manufacturing method was performed. As a result of the ion implantation, a crystal defect layer (not shown) was formed at a depth of about 40 nm from the surface of the Si strained layer 30. Here, a single crystal Si substrate 1 having a 10 nm thick silicon oxide film 2 grown on the surface was separately prepared. (Fig. 12)
Based on Example 1, two substrates were bonded and peeled in the strain relaxation layer 32 above the Si strained layer 33 using peeling at the crystal defect layer. The heat treatment for enhancing the adhesive strength was performed at 900 ° C. for the purpose of minimizing strain relaxation in the Si strained layer 30. From this state, the thin strain relaxation layer 31 is completely removed by mirror polishing and mixed crystal layer selective etching of the peeled surface by a surface polishing method that does not include abrasive grains, and a 10 nm thick single crystal Si strained layer 30 and a 10 nm thick embedded thin film. An SOI substrate in which the gate insulating film 2 was sequentially formed on the support substrate 1 was manufactured. In accordance with the first embodiment, formation of an inter-element isolation insulating region 4 having a depth reaching the buried oxide film 2 defining the active region, formation of the well diffusion layer 5, and high concentration diffusion on the multilayer structure SOI substrate having the strained Si layer Formation of the layer 50, selective removal of the single crystal Si strained layer 30 in the desired region, and subsequent formation of the gate insulating film 21 were performed based on Example 1. Next, a gate electrode was formed. In this embodiment, a polycrystalline SiGe film having a thickness of 20 nm and 30% Ge and B added at a high concentration is deposited as a first gate electrode film, and well diffusion is performed. After selectively removing the first gate electrode film, the gate insulating film 21 and the thin buried insulating film 2 in the connection region with the layer region, the second gate electrode film was deposited on the entire surface. As the second gate electrode film, a polycrystalline Si film 220 with a thickness of 40 nm was deposited by a chemical vapor reaction and processed together with a gate protection film 23 with a thickness of 40 nm so as to have a gate length of 30 nm. The reason why the high-concentration P-type impurity polycrystalline SiGe film is used as the gate electrode material immediately above the gate insulating film is that the threshold voltage value in the n-channel fully-depleted SOI IIFET can be set to about 0 V by the work function of the gate electrode material. . High-concentration source diffusion layer 6, high-concentration drain diffusion layer 7, gate sidewall insulating film 26, N-type high-concentration stacked source by As ion implantation using gate electrode 220 and gate protective film 23 as an implantation blocking mask and its activation heat treatment A region, N-type high concentration stacked drain region was formed according to Example 1 above. The selective formation of the N-type high-concentration stacked source region and the N-type high-concentration stacked drain region is performed in the chemical vapor phase of an amorphous or polycrystalline Si film to which P (phosphorus) is added at a high concentration regardless of the first embodiment. There is no problem based on the deposition. From this state, the selective removal of the gate protection insulating film 23 and selective silicidation treatment are performed on the stacked source / drain region, the gate electrode upper region, the high concentration region 15 and the like in accordance with the first embodiment. A drain region, a gate silicide film, and the like were formed. Subsequently, after depositing the wiring interlayer insulating film 12 and opening the desired region, the wiring metal is embedded and planarized in the opening, and the wiring process including the wiring electrodes 15 and 17 is performed. A semiconductor device was manufactured through a wiring process. (Fig. 13)
In the semiconductor device according to the present embodiment, the threshold voltage value is set to almost 0 V by the gate electrode structure of 30 nm length by the polycrystalline SiGe film to which B is added at a high concentration, and has a high driving capability, and has a conventional structure. High-speed operation almost twice that of complementary IGFET inverters has been demonstrated. The high-speed operation is considered to be due to the significant increase in drive current and the leakage current reduction effect of the SOIIGFET based on this embodiment. The first reason is based on the fact that the SOIIGFET according to this example is formed of a single crystal Si thin film having a lattice strain amount of about 1.6% in the direction parallel to the (100) plane. By introducing crystal lattice strain, the degeneration of the conduction band, valence band, and conduction band of the Si single crystal is solved, the light hole effective mass component becomes the main subject of conduction, and the scattering of energy valleys is suppressed. This is considered to be a result of the appearance of both electrons and holes with improved mobility. The amount of lattice strain introduced in the Si single crystal is controlled by the Ge content in the SiGe mixed crystal layer 31, but in the manufacture of the semiconductor device based on the present embodiment, the Ge content in the SiGe mixed crystal layer 31 is changed to change the Si content. The single crystal film 30 is separately manufactured using a semiconductor substrate in which the lattice strain amount is controlled from 2% to 0.01%. However, as the lattice strain amount increases, the current drive capability of the SOIIGFET is 0.01%. Although a tendency to increase from the degree is seen, the tendency is completely saturated when the lattice strain is about 2%. On the contrary, the amount of crystal defects generated in the Si single crystal film 30 increases rapidly as the lattice strain increases. From the above results, the lattice strain amount of the Si single crystal film 30 is desirably 0.01% or more and 2% or less. In this embodiment, the SiGe mixed crystal layer 31 that causes distortion in the Si single crystal film 30 during the manufacturing process of the SOI substrate is completely removed after the bonding process with the support substrate 1. Strain is maintained by bonding, and crystal defects are generated in the Si single crystal layer 30 in which lattice strain is introduced, or new crystal defects are generated by heat treatment during the manufacturing process by removing the SiGe mixed crystal layer 31. I was able to prevent it.

  The second reason for the significant increase in driving current and the reduction in leakage current of the SOIIGFET according to this embodiment is that the gate input potential is directly applied to the well diffusion region 5 directly below the SOIIGFET formed in the support substrate 1. It is thought that it is based on. Application of the gate input potential to the well diffusion region 5 lowers the threshold voltage value so that the drive current becomes larger in the conductive state of the SOIIGFET through the thin buried insulating film 2, and more quickly at the time of switching to the non-conductive state. It works as if the threshold voltage value is further increased so that the leakage current is reduced. The significant performance improvement of the SOIIGFET based on this embodiment is considered to be based on the above two reasons.

<Example 5>
In this example, only the P-conductivity type SOIIGFET was manufactured in Example 1 described above. That is, the introduction of impurities into the source and drain diffusion layers depended on the high concentration B. The main difference from the first embodiment is that the orientation of the source / drain diffusion layers of the P-conductivity type IGFET formed in the single crystal Si thin film 3 is not the normal <110> direction but the <100> direction. That is, the impurity region 53 for adjusting the threshold voltage is introduced into the well diffusion layer region 5 through the buried gate insulating film 2 below the channel region of the P-conductivity type IGFET which is the main transistor. Impurities were introduced so as to penetrate the single crystal Si thin film 3 and the buried gate insulating film 2 by ion implantation. For the implantation type, the threshold voltage value in the P-conductivity type IGFET is changed in the positive direction to increase the drive current and leakage current, and B and In are changed, and the threshold voltage value is changed in the negative direction and the drive current and leakage current are changed. As (Ar), P (phosphorus), Sb (antimony), etc. may be used to reduce the above. The implantation amount may be 1 × 10 ¹⁴ / cm ² or less, so that the implantation damage in the single crystal Si thin film 3 and the buried insulating film 2 in the penetrating region can be suppressed to an extent that can be effectively ignored. The implantation region is controlled by determining an implantation blocking mask before forming the gate insulating film 20. In this step, the entire surface is implanted without using an implantation blocking mask, and after the formation of the gate electrode, implantation of an opposite conductivity type using the gate electrode 22 or the gate side wall insulating film 26 as an implantation blocking mask is performed. The compensation impurity region 55 may be left in the well diffusion layer region 5 in a self-aligned relationship with the gate electrode 22 by effectively compensating the impurity. The threshold voltage value is determined by the amount of impurities in the single-crystal Si thin film 3, the work function of the gate electrode, the amount of impurities in the impurity region 53, and the thicknesses of the gate insulating film and the buried gate insulating film. In the SOIIGFET according to the present embodiment, the single crystal Si thin film 3 is as extremely thin as 10 nm, and the amount of impurities inside is completely depleted with a negligible concentration. The thicknesses of the gate insulating film 4 and the buried insulating film 2 are also different. Since the equivalent thickness of the silicon oxide film is as thin as about 2 nm to 10 nm, it is almost determined by the work function of the gate electrode, the total amount of impurities in the impurity region 53 and their distribution state. In the SOIIGFET according to this embodiment, a threshold voltage value is set to be almost 0 V by using a metal silicide film as a gate electrode material, and a desired impurity is selectively selected in a desired amount for each IGFET on the same semiconductor substrate according to a desired circuit configuration. Impurity regions 53 introduced into the were formed. In this embodiment, the high-concentration region 50 connected to the gate electrode 5 and connected to the well diffusion layer 5 is provided at one place from the viewpoint of reducing the occupied area. Although the P-conductivity type IGFET manufactured based on this embodiment is a fully depleted type SOIIGFET, the threshold voltage value is independent from each other between adjacent IGFETs that are configured with the same gate material according to the desired circuit configuration. A large driving current and a low leakage current can be achieved by setting the gate input potential to an effective value and controlling the substrate potential of the SOIIGFET through a thin buried insulating film. Further, in the P-conductivity type IGFET based on the present embodiment, the effect of improving the hole mobility is also exhibited due to the effect that the source / drain directions are arranged in the <100> direction. Even when compared with a P-conductivity type IGFET whose direction is arranged in the <110> direction, an improvement in driving current of about 10% was achieved without variation in threshold voltage value and increase in leakage current.

  The IGFET based on this embodiment is based on a fully depleted operation mechanism, and it is not necessary to introduce punch-through suppression impurities into the single crystal Si thin film 3 constituting the channel region. For this reason, the problem of increased leakage current due to direct tunneling current between drain substrates due to an increase in the amount of punch-through suppression impurities, which is a problem in ultra-fine IGFETs manufactured on a normal substrate, and the introduction increased as the amount of introduced impurities increases This eliminates fundamental fatal defects such as an increase in threshold voltage variation due to an increase in the relative fluctuation amount of impurities. Accordingly, a dramatic improvement in the yield of good products can be achieved. In order to maintain the above fully depleted operation mechanism, it is necessary to manufacture an ultrafine IGFET in a single crystal semiconductor thin film that is sufficiently thinner than the gate length and close to an intrinsic semiconductor in the SOI structure. When the power supply voltage is 1 V or less, the thickness of the single crystal Si thin film 3 is preferably 1/3 or less of the gate electrode length, and preferably 1/5 or less for complete depletion.

<Example 6>
FIG. 14 is a cross-sectional view showing the order of manufacturing steps of a semiconductor device according to the sixth embodiment of the present invention. In the semiconductor device manufactured according to the first embodiment, element isolation between a plurality of SOIIGFETs formed on the same well diffusion layer region 5 is based on mesa isolation of a thin single crystal Si film 3. When the gate electrode 22 is directly connected to the well diffusion layer region 5 with this configuration, a short circuit may occur between the gate electrode 22 and the thin single crystal Si film 3 at the end of the mesa etching, and there is a concern that the yield of good products may be reduced. Is done. It is probable that the short circuit is a side portion of the gate electrode 22 and the thin mesa-etched thin single crystal Si film 3. In the semiconductor device according to this example, an SOI substrate having a thin specification with a thin single crystal Si film 3 having a thickness of 40 nm was prepared in advance for the purpose of preventing the short circuit. After the formation of the well diffusion layer 5 in the first embodiment, the main surface of the thin single crystal Si film 3 is formed on the entire surface by a thermal oxidation method or the like, and then the insulating film 33 and the thin single crystal Si film are formed. Patterning to determine 3 active areas was performed. Thereafter, the insulating film 34 was left only on the side wall portion of the activated region pattern by depositing the whole surface of another type of insulating film having a thickness of 30 n, for example, a silicon nitride film 34 and anisotropic etching thereof. With respect to the method of manufacturing the insulating film 34 with the side wall remaining, the insulating film 33 is used as an etching mask, and the Si film 3 is selectively removed from the exposed side wall of the thin single crystal Si film 3 by a desired thickness and then removed. The insulating film 34 may be buried and left. (Fig. 14)
After selectively removing the insulating film 33 while leaving the insulating film 34 left from the state of FIG. 14, the semiconductor device was manufactured according to the first embodiment. In the semiconductor device according to the present embodiment, it is found that the short-circuit failure between the gate electrode 22 connected to the well diffusion layer 5 and the source and drain regions formed in the thin single crystal Si film 3 is completely eliminated. did.

<Example 7>
FIG. 15 is a cross-sectional view showing the order of manufacturing steps of a semiconductor device according to a seventh embodiment of the present invention, and FIG. 16 is a completed cross-sectional view thereof. The semiconductor device according to the present embodiment is a semiconductor device that includes a fully depleted SOIIGFET as a main constituent element and also includes a circuit group that partially requires high breakdown voltage characteristics. In particular, the present invention relates to a semiconductor device including an electrostatic breakdown prevention circuit related to input / output of an external signal. In the active region determination step of the first embodiment for processing the thin single crystal Si film 3, the thin single crystal Si film 3 and the thin buried insulating film 2 in the region where the electrostatic breakdown prevention circuit or the like is to be disposed are selectively removed and supported. The main surface of the substrate 1 was exposed. Subsequently, the well connection hole concentration diffusion layer 50, the inter-element isolation insulating film 4, the gate insulating film 20, and the first gate electrode material film 21 are formed according to the first embodiment, and then the desired well connection hole concentration diffusion layer 50 is formed. The gate insulating film 20 and the first gate electrode material film 21 on the region were selectively removed. (Fig. 15)
A semiconductor device was manufactured based on Example 1 starting from the entire deposition of the second gate electrode material film in the state of FIG. In the semiconductor device of this example, the IGFET was also configured on the support substrate 1 in the same manner as on the thin single crystal Si film. (Fig. 16)
In the semiconductor device based on the present embodiment, it is possible to realize a semiconductor device in which a fully-depleted SOI IIFET having high driving capability even with a low voltage power source based on Embodiment 1 and an IGFET on a normal substrate excellent in high withstand voltage characteristics are integrated. It was.

<Example 8>
FIG. 17 is a layout diagram of a semiconductor device according to an eighth embodiment of the present invention, and FIG. 18 is an equivalent circuit diagram thereof. In accordance with the first embodiment, a semiconductor device including an SRAM in which a unit cell is configured by six transistors was manufactured. 17 and 18, Tr1 and Tr2 are transfer elements that control data input / output, and a storage node is configured by two pairs of complementary transistors Ld1 and Dr1 and Ld2 and Dr2. Each of the transistors Ld1 and Ld2 is a P-conductivity type transistor, and Dr1, Dr2 and Tr1, and Tr2 are N-conductivity type transistors. In FIG. 17, 51 is a connection hole between the well connection hole concentration diffusion layer 50 and the gate electrode, and the capacitor element in FIG. 18 has a capacitance due to the thin diffusion insulating film 2 with the well diffusion layer 5 and the substrate node of the transistor as the counter electrode. It is shown equivalently. A pair of complementary transistors constituting the storage node is formed on a common well diffusion layer region, and the two pairs are insulated and isolated by an element isolation insulating film 4. That is, Ld1 and Dr1, and Ld2 and Dr2 each share a well diffusion layer region. The transfer element is electrically connected to a common support substrate by a well of opposite conductivity type in the enclosed inter-element isolation insulating film. That is, the pair of complementary transistors constituting the storage node and the supporting substrate region immediately below each of the transfer elements are separated by a well diffusion layer by a PN junction. In the semiconductor device and SRAM according to the present embodiment, the driving capability of complementary transistors forming a pair is remarkably improved by the effect of applying the well diffusion layer of the gate input signal, so that the driving capability in the ratio of the transfer element increases. As a result, the instability in the SRAM read mode is eliminated, and it is possible to operate stably even under a low power supply voltage. As a result, it was possible to realize an SRAM in which a significant improvement in power consumption was achieved. Furthermore, the layout problem for applying the well diffusion layer that brings about the above effect can be realized by using the gate electrode wiring which is the lowermost layer wiring and connecting it in series with the gate electrode without requiring any increase in the occupied area. Was made. In the SRAM according to this embodiment, a parasitic capacitance based on the well diffusion layer is added to the storage node. The parasitic capacitance has a function of relaxing current flowing through the transfer element during dynamic operation, and has a feature of further improving stable operation. In the semiconductor device according to the present embodiment, it is desirable not to implement the structure having the effect of reducing the parasitic capacitance, such as the compensation diffusion layers 54 and 55, and to increase the parasitic procedure. In the semiconductor device according to the present embodiment, stable operation is ensured even when the operating voltage is lowered as compared with the prior art, and therefore it is possible to realize an SRAM with lower power consumption.

<Example 9>
19 is a layout diagram of a semiconductor device according to a ninth embodiment of the present invention, FIGS. 20 and 21 are equivalent circuit diagrams thereof, and FIG. 21 is a current of each transistor constituting the semiconductor device according to the ninth embodiment of the present invention. It is a figure which shows a voltage characteristic. The difference between FIG. 20 and FIG. 21 is the relationship in which the transistor conductivity type and the potential relationship are reversed, and normal memory operation is possible in either type. In accordance with the first embodiment, a semiconductor device including an SRAM in which a unit cell is composed of four transistors by two pairs of complementary transistors was manufactured. In FIG. 19, G indicates a gate electrode of a transistor, L indicates a source / drain active region and well diffusion layer connection region, WL indicates a word line, and DL indicates a data line. Tr and Dr in the figure correspond to the transistors in FIGS. 21 and 22, and represent a transfer transistor and a driver transistor, respectively. Cp1 and Cp2 indicate the respective parasitic capacitances due to the well diffusion layer and the support substrate PN junction that are shared by each of Tr1 and Dr1, and Tr2 and Dr2. Tr1 and Dr1, and Tr2 and Dr2 each share a well diffusion layer region. 20 and 21 indicate a capacitive element based on a thin buried insulating film between the well diffusion layer and the SOI layer. In FIG. 20 and FIG. 21, the SRAM itself in which a unit cell is composed of two p-conductivity type IGFETs and two n-conductivity type IGFETs that do not have a capacitive element is well known. The threshold voltage values of Tr1 and Tr2 made of conductive IGFET are set lower than the threshold voltage values of Dr1 and Dr2 made of n conductive IGFET. In FIG. 20, in the standby state in which the word line and both bit lines are held at “1” potential, “1” is stored in the connection node of Dr2 and Tr2, and “0” potential is stored in the connection node of Dr1 and Tr1. Assuming this condition, Tr2 performs a power supply operation that also serves as a load element so that the connection node of Dr2 and Tr2 maintains the "1" state due to the difference in threshold voltage value between Tr2 and Dr2, thereby guaranteeing the SRAM operation. . At this time, the connection node of Tr1 and Dr1 on the opposite side is at “0” potential, but this node is held at “0” potential because Dr1 is in a conducting state and the Vss potential is supplied. However, since the threshold voltage value of Tr1 is relatively low, a leakage current corresponding to the threshold voltage value of Tr1 is unavoidable. The first problem of the known SRAM in which the unit cell is constituted by the four transistors is that the operation as the SRAM cannot be guaranteed unless the threshold voltage value of the constituent transistor is strictly controlled, and Tr1 or Tr2 The leakage current based on the low threshold voltage value is inevitable. The advantage is that the occupied area can be reduced as compared with a normal SRAM based on 6 transistors.

  In the semiconductor device according to this embodiment, in which the unit cell is composed of four transistors, the unit cell is composed of two pairs of complementary IGFETs sharing a well diffusion layer, but each complementary IGFET has one gate thereof. The electrode is connected to the well diffusion layer, and the substrate potential of the pair of complementary transistors is controlled through a thin buried insulating film. As a result, in the driver transistors Dr1 and Dr2, as apparent from FIG. 22, the power supply voltage is 1 V and the leakage current is 1.3 times that of the conventional transistor having the same dimensions, and the N-channel IGFET is 1.3 times the P-channel IGFET. .4 times the driving capability, enabling high-speed operation.

  Further, under a word line signal condition (“1” potential in FIG. 20 and “0” potential in FIG. 21) in which the transfer IGFET is inoperative, a potential based on the storage potential of the storage node is applied to the well diffusion layer. The transfer IGFET is applied through a thin buried insulating film so as to maintain the potential of the storage node. That is, the transfer IGFET acts as if it holds the role of a load IGFET that holds the storage node potential of the memory cell. Specifically, in FIG. 20, the word line signal is “1”, Tr1 and Tr2 are in the non-passing state, and the Tr2 and Dr2 connection nodes are stored and held at “1”. Since the “0” potential is applied and Tr2 is converted to the low threshold voltage state, the bit line potential “1” is transmitted through Tr2 so as to maintain the storage node potential “1” state. At this time, “1” is applied to the well diffusion layer of Tr1, and the high threshold voltage state is maintained because Tr1 and the Dr1 connection node potential “0” are disconnected from the bit line potential “1”. Is retained. In order to enable normal SRAM operation in the semiconductor device according to the present embodiment, it is a condition that the difference between the absolute values of the leakage currents of Tr and Dr at a gate voltage of zero V is sufficiently large in the current-voltage characteristics of FIG. However, it can be seen that in the semiconductor device according to the present embodiment, the value reaches three digits. Furthermore, in the semiconductor device according to the present embodiment, the application state of Tr1 and Tr2 from the well diffusion layer side is based on the dynamic potential of the connection node, and the opposite potentials, “0” potential and “1” potential are automatically set. It becomes a relationship to be applied. That is, each transfer IGFET is controlled by the well diffusion layer potential so that the transfer IGFET is more cut off in the cut-off state and more in the power feed state than in the conventional four-transistor SRAM in which the threshold voltage value is fixed. Leakage current is reduced by orders of magnitude. Furthermore, the operational instability due to variations in threshold voltage values, which is a drawback of SRAMs in which unit cells are composed of four transistors, is essentially a problem due to the effect of reducing variations in threshold voltage values, which is a unique feature of fully depleted SOI transistors. Absent. Thus, conventionally, the SRAM operation in which the unit cell is configured by six IGFETs can be configured by four IGFETs in the semiconductor device according to the present embodiment. Compared to the eighth embodiment, the SRAM of this embodiment is more unstable in operation, but has a feature that a higher density can be achieved with a low leakage current characteristic because the number of constituent elements is small. Furthermore, it has the effect of relaxing the current flowing through the transfer IGFET during dynamic operation due to the added effect of the parasitic capacitances Cp1 and Cp2 based on the well diffusion layer connected to the storage node, and further improves the stable operation. doing. In the semiconductor device according to the present embodiment, it is desirable not to implement the structure having the effect of reducing the parasitic capacitance, such as the compensation diffusion layers 54 and 55, and to increase the parasitic procedure. In the semiconductor device according to the present embodiment, stable operation is ensured even when the operating voltage is lowered as compared with the conventional one. Therefore, it is possible to realize a lower power consumption SRAM with a further reduced area. In the configuration of the peripheral circuit of the SRAM and other logic circuits, the substrate region may be configured as a well diffusion layer similar to the SRAM, or may be set to other ion implantation conditions. The voltage application to the well diffusion layer may be arbitrarily set according to the circuit configuration, such as applying a constant potential or not applying it as desired.

<Example 10>
FIG. 23 is a diagram showing an equivalent circuit of the semiconductor device according to the tenth embodiment of the present invention. In accordance with the first embodiment, a logic circuit and a NAND circuit in which transistors are connected in series were manufactured. FIG. 10 shows a three-input NAND circuit composed of three pairs of complementary IGFETs, TP1 and TN1, TP2 and TN2, TP3 and TN3, IN1, IN2, and IN3 are input signal terminals, and OUT is an output signal terminal. The capacitive element is a capacitive element based on a buried insulating film between the SOI layer and the in-substrate diffusion layer. In the semiconductor device according to the present embodiment, the well diffusion layer in the lower part of the region where the three pairs of complementary IGFETs are configured is shared, and the well diffusion layer and IN1 are electrically connected. It is possible to connect only the diffusion layer planted in the N conductivity type IGFET region and connect the well diffusion layer in the lower region of the P conductivity type IGFET to the power supply voltage line by another wiring from the viewpoint of reducing the parasitic capacitance. By connecting the IN1 signal line to the well diffusion layer, a signal of IN1 is applied to each channel region of TN2 and TN3 through a thin buried insulating film. As a result, the current drop (the threshold voltage rise effect due to the source-substrate bias in the corresponding IGFET) based on the substrate bias effect, which is a drawback of the conventional NAND logic circuit, compared to the TN1 of the TN3 and NTN conductivity type at all input terminals. In the state where the “1” signal for turning on the IGFET is input, the threshold voltage values of TN2 and TN3 are lowered, so that high-speed operation becomes possible. Note that when a non-conducting signal is input to IN1 and a non-conducting signal with IN3 being "0", a slight leakage current flows when the N-conducting IGFET connected in series is non-conducting, and well diffusion to IN1 Since some problems such as the addition of layer capacitance also occur, the semiconductor device according to the present embodiment is applied to high-speed operation of the logic part such that the additional capacitance is originally large like a critical path and some capacitance addition is ignored. It is preferable.

<Example 11>
FIG. 24 is an equivalent circuit diagram in the case where the capacitors connected to the substrates Ld1 and Ld2 shown in FIG. 18 are removed. In accordance with the first embodiment, a semiconductor device including an SRAM in which a unit cell is configured by six transistors was manufactured. In FIG. 24, Tr1 and Tr2 are transfer elements that control input / output of data, and a storage node is configured by two pairs of complementary transistors of Ld1 and Dr1 and Ld2 and Dr2. Each of the transistors Ld1 and Ld2 is a P-conductivity type transistor, and Dr1, Dr2 and Tr1, and Tr2 are N-conductivity type transistors.
According to the present embodiment, it is possible to improve the data write margin in the SRAM.

1 is a cross-sectional view of a region parallel to a gate electrode of a semiconductor device according to a first embodiment of the present invention. Sectional drawing which shows the SOI structure transistor of the conventional substrate potential control system. Sectional drawing which shows the manufacturing process order of the semiconductor device by 1st Example of this invention. Sectional drawing which shows the manufacturing process order of the semiconductor device by 1st Example of this invention. Sectional drawing which shows the manufacturing process order of the semiconductor device by 1st Example of this invention. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention. FIG. 4 is a cross-sectional view orthogonal to the gate electrode showing the order of manufacturing steps of the semiconductor device according to the first embodiment of the present invention. FIG. 3 is a completed cross-sectional view orthogonal to the gate electrode of the semiconductor device according to the first embodiment of the present invention. FIG. 7 is a completed plan view of a semiconductor device according to a second embodiment of the present invention. Sectional drawing with a gate electrode which shows the manufacturing process order of the semiconductor device by 3rd Example of this invention. FIG. 10 is a completed cross-sectional view orthogonal to the gate electrode of the semiconductor device according to the third embodiment of the present invention. Sectional drawing which shows the order of the manufacturing process of the semiconductor device by the 4th Example of this invention. FIG. 7 is a completed sectional view of a semiconductor device according to a fourth embodiment of the present invention. Sectional drawing which shows the order of the manufacturing process of the semiconductor device by the 6th Example of this invention. Sectional drawing which shows the order of the manufacturing process of the semiconductor device by the 7th Example of this invention. FIG. 10 is a completed sectional view of a semiconductor device according to a seventh embodiment of the present invention. FIG. 10 is a layout diagram of a semiconductor device according to an eighth embodiment of the present invention. The equivalent circuit diagram of the semiconductor device by the 8th Example of this invention. FIG. 20 is a layout diagram of a semiconductor device according to a ninth embodiment of the present invention. The equivalent circuit schematic of the semiconductor device by the 9th Example of this invention. The equivalent circuit schematic of the semiconductor device by the 9th Example of this invention. The figure which shows each transistor characteristic of the semiconductor device by the 9th Example of this invention. The equivalent circuit schematic of the semiconductor device by the 10th Example of this invention. The equivalent circuit schematic of the semiconductor device by the 11th Example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Support substrate, 2 ... Embedded oxide film, 3 ... Single crystal semiconductor thin film, 4 ... Inter-element isolation insulating film, 5 ... Well diffusion layer, 6 ... N type high concentration source diffusion layer, 7 ... N type high concentration drain diffusion 8 ... P-type high-concentration source diffusion layer, 9 ... P-type high-concentration drain diffusion layer, 10, 11, 22, 100 ... gate electrode, 12 ... wiring layer insulating film, 13 ... wiring connection hole metal, 14 ... Source electrode, 15 ... ground electrode, 16 ... output node electrode, 17 ... power supply potential electrode, 18, 24, 33,34 ... insulating film, 19 ... silicon nitride film, 20 ... gate insulating film, 21 ... first silicon film , 23 ... Gate protective insulating film, 25 ... Source, drain stacked semiconductor, 26 ... Gate side wall insulating film, 27 ... Wiring connection hole, 28 ... Metal silicide film, 33 ... Protective insulating film, 34 ... Side wall protective insulating film, 50 ... Well connection hole concentration diffusion layer, 51 ... Gateway Connecting holes, 52 and 53 ... threshold voltage control diffusion layers, 54, 55 ... compensation diffusion layer.

Claims (28)

A single crystal semiconductor thin film disposed via a first insulating film formed on a semiconductor substrate;
A plurality of fully depleted insulated gate field effect transistors including at least a gate electrode disposed via a second insulating film formed on the single crystal semiconductor thin film;
The gate electrode is made of a film containing metal or metal silicide,
A semiconductor device, wherein a first impurity region for controlling a threshold voltage is formed in a region located in the semiconductor substrate region and below the gate electrode. The gate electrode is made of a metal having a level whose work function is located in the vicinity of the forbidden band energy level of the single crystal semiconductor thin film, or a film containing a material made of a metal silicide film,
2. The semiconductor device according to claim 1, wherein the film is formed in contact with the first insulating film. At least a single crystal semiconductor thin film disposed via a first insulating film formed on a semiconductor substrate and a gate electrode disposed via a second insulating film formed on the single crystal semiconductor thin film Including a plurality of fully depleted insulated gate field effect transistors,
The gate electrode is made of a film containing metal or metal silicide,
A first impurity region for controlling a threshold voltage formed in the semiconductor substrate region so as to be self-aligned with the gate electrode by introducing impurities using a pattern opposite to the gate electrode as a mask; A featured semiconductor device.   2. The transistor according to claim 1, wherein the transistor includes a complementary transistor including a transistor having a first conductivity type and a transistor having a second conductivity type opposite to the conductivity type. Semiconductor device.   2. The material of the gate electrode is made of Ni, Co, Ti, W, Ta, Mo, Cr, Al, Pt, Pa, Ru, or a metal silicide film or metal nitride film thereof. A semiconductor device according to 1.   The semiconductor device according to claim 1, wherein the first impurity layer is set to have a desired conductivity type and a desired impurity amount for each of the transistors.   A second impurity region is formed so as to sandwich a region located in the single crystal semiconductor thin film and immediately below the gate electrode, and applied to at least one gate electrode of the plurality of transistors in the second impurity region. 2. The semiconductor device according to claim 1, wherein the same signal as that to be applied is applied.   8. The semiconductor device according to claim 7, wherein at least one side surface of the second impurity region is in contact with a structure including an insulating film.   The single crystal semiconductor thin film includes a first transistor having a second impurity region of a first conductivity type, and a second impurity region of a second conductivity type different from the first conductivity type. The semiconductor device according to claim 1, wherein a second transistor is formed, and a pair of transistors is formed by the first and second transistors.   The connection electrode for applying a signal potential to the second impurity region is an electrode configured by a step that is the same as the gate electrode manufacturing step of the transistor, and is disposed in a desired region of the second impurity region. The semiconductor device according to claim 1, wherein:   11. The semiconductor device according to claim 10, wherein the connection electrode is arranged in series with a pair of transistors of the first and second conductivity types sharing a gate electrode.   11. The semiconductor device according to claim 10, wherein the connection electrode is arranged in parallel with a gate electrode shared by a pair of transistors having the first and second conductivity types.   2. The semiconductor device according to claim 1, wherein the single crystal semiconductor thin film in which the transistor is formed is separated from each other, and an insulating film is formed at least in a side region of the single crystal semiconductor thin film.   The semiconductor substrate region located immediately below the second impurity region serving as the source and drain of the transistor and in contact with the first insulating film compensates for impurities present in the first impurity region. 3. The semiconductor device according to claim 1, wherein three impurity regions are introduced.   The semiconductor device according to claim 1, wherein the single crystal semiconductor thin film is formed of a single crystal silicon film.   2. The single crystal semiconductor thin film is a single crystal silicon film, and a tensile strain stress of 0.01% to 2% is applied in at least one direction of the single crystal silicon film. A semiconductor device according to 1.   2. The semiconductor device according to claim 1, wherein the single crystal semiconductor thin film has a film thickness smaller than an electrode length of the gate electrode.   2. The semiconductor device according to claim 1, wherein the first insulating film is thinner than an electrode length of the gate electrode.   The single crystal silicon film has a (100) plane, and the source and drain diffusion layers are arranged perpendicularly or parallel to the <100> direction of the single crystal silicon film via the gate electrode. The semiconductor device according to claim 14.   The semiconductor device according to claim 14, wherein the source and drain diffusion layer regions include a semiconductor film stacked on the single crystal semiconductor thin film. The complementary semiconductor device sharing the gate electrode has a unit cell composed of two pairs and two transistors for controlling input / output of data signals,
The second impurity region is located below the pair of complementary semiconductor devices, is electrically connected to the gate electrode, and each of the second impurity regions is electrically isolated from each other. A semiconductor device.   8. The semiconductor device according to claim 7, wherein a PN junction capacitor formed between the second impurity region and the semiconductor substrate is connected to a memory node. A single crystal semiconductor thin film disposed via a first insulating film formed on a semiconductor substrate;
A plurality of fully depleted insulated gate field effect transistors including at least a gate electrode disposed via a second insulating film formed on the single crystal semiconductor thin film;
The plurality of transistors include at least unit cells each composed of two pairs of a first conductivity type transistor and a second conductivity type transistor;
A common second impurity region separated from the outside by a PN junction in a semiconductor substrate region located below the transistor region constituting the pair;
The semiconductor device, wherein the second impurity region is electrically connected to at least one gate electrode of the semiconductor device constituting each pair. In a semiconductor device including a unit cell in which a transfer transistor of a first conductivity type and a driver transistor of a second conductivity type are connected in series,
The transistor constituting the unit cell is composed of a fully-depleted insulated gate field effect transistor controlled by a first gate electrode configured as if sandwiching a channel region and a second gate electrode to which a capacitor element is added. The semiconductor device is configured such that the first gate of the driver transistor is electrically connected to the second gate of the transfer transistor connected in series to actuate the transfer transistor in a non-conducting state. apparatus.   23. The semiconductor device according to claim 1, wherein the semiconductor device is electrically connected to a semiconductor device formed on a main surface of the same semiconductor substrate on which the semiconductor device is formed. A plurality of insulations comprising an impurity introduction region in a first semiconductor thin film disposed on a semiconductor substrate via at least a first insulating film, and a gate electrode on a second insulating film formed on the semiconductor thin film In a method for manufacturing a semiconductor device including a gate field effect transistor,
Forming the second insulating film and the second semiconductor thin film in order on the first semiconductor thin film;
Selectively removing the second insulating film and the second semiconductor thin film using a desired pattern as a mask;
Forming a third semiconductor film on a main surface including the second semiconductor thin film;
Patterning the third semiconductor thin film;
A method of manufacturing a semiconductor device, comprising: patterning a laminated film composed of the second semiconductor thin film and the third semiconductor thin film. Selectively removing the third insulating film and the semiconductor thin film in the same pattern;
Selectively removing a part of the side surface of the semiconductor thin film exposed by the removing step;
27. A step of selectively leaving a fourth insulating film in a selectively removed region of the semiconductor thin film and removing the third insulating film on the surface of the semiconductor thin film. Device manufacturing method. A semiconductor film formed on the single crystal semiconductor thin film via a second insulating film;
A gate protection film deposited on the semiconductor;
A gate sidewall insulating film formed on a side surface of a gate electrode made of a film including the semiconductor film and the gate protective film;
Impurities are implanted into the second impurity region using the gate protective film and the gate sidewall insulating film as an impurity implantation mask, and a third impurity region is formed so as to compensate for the impurities present in the first impurity region. 27. A method of manufacturing a semiconductor device according to claim 26, wherein:

Images